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SH7750, SH7750s, SH7750r group user?s manual: hardware rev.7.02 sep 2013 renesas 32-bit risc microcomputer superh? risc engine family / SH7750 series 32
page ii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013
r01uh0456ej0702 rev. 7.02 page iii of lii sep 24, 2013 notice 1. descriptions of circui ts, software and other related information in this do cument are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the inco rporation of these circuits, software, and information in the design of your equipment. renesas el ectronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing th e information included in this do cument, but renesas electronics does not warrant that such information is error free. renesa s electronics assumes no liabili ty whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 3. renesas electronics does not assume any liability for infringe ment of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby un der any patents, copyrights or other intellectual property right s of renesas electronics or others. 4. you should not alter, modify, copy, or ot herwise misappropriate any renesas electroni cs product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherw ise misappropriation of rene sas electronics product. 5. renesas electronics products are classifi ed according to the following two quality grades: ?standard? and ?high quality?. t he recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. ?standard?: computers; office equipment; communications equi pment; test and measurement equipment; audio and visual equipment; home electronic appliances; ma chine tools; personal electronic equipment; and industrial robots etc. ?high quality?: transportation equipment (aut omobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized fo r use in products or systems that may pose a direct threat t o human life or bodily injury (art ificial life support devices or systems, surgical implantations etc.), or may cause serious pro perty damages (nuclear reactor control systems, military equipment etc.). you must check the quality grade of each renesas electronics product before usin g it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurre d by you or third parties arising from the use of any renesas el ectronics product for which the product is not intended by renesa s electronics. 6. you should use the renesas electronics prod ucts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, move ment power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electr onics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fu rther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a ren esas electronics product, such as safety design for hardware and soft ware including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degr adation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the sa fety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the incl usion or use of controlled substances, includin g without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and techno logy may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable do mestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this do cument for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics produc ts, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no re sponsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority-owned subsidiaries. (note 2) ?renesas electronics product(s)? means any produc t developed or manufactured by or for renesas electronics. (2012.4)
page iv of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. if something is connect ed to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefi ned until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the system?s operation is not guaranteed if they are accessed. 5. reading from/writing to reserved bit of each register note: treat the reserved bit of register used in each module as follows except in cases where the specifications for values which are read from or written to the bit are provided in the description. the bit is always read as 0. the write value should be 0 or one, which has been read immediately before writing. writing the value, which has been read immediately before writing has the advantage of preventing the bit from being affected on its extended function when the function is assigned.
r01uh0456ej0702 rev. 7.02 page v of lii sep 24, 2013 preface the sh-4 (SH7750 group: SH7750, SH7750s, SH7750r) microprocessor incorporates the 32-bit sh-4 cpu and is also equipped with peripheral functions necessary for configuring a user system. the SH7750 group is bu ilt in with a variety of peripheral functions such as cache memory, memory management unit (mmu), interrupt co ntroller, timers, two serial communication interfaces (sci, scif), real-tim1e clock (rtc), user break controller (ubc), bus state controller (bsc) and smart card interface. this lsi can be used in a wide range of multimedia equipment. the bus controller is compatible with rom, sram, dram, synchronous dram and pcmcia, as well as 64-bit synchronous dram 4-bank system and 64-bit data bus. target readers: this manual is designed for use by people who design application systems using the SH7750, SH7750s, or SH7750r. to use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. purpose: this manual provides the information of the hardware functions and electrical characteristics of the SH7750, SH7750s, and SH7750r. the sh-4 software manual contains detailed info rmation of executable instructions. please read the software manual together with this manual. how to use the book: ? to understand general functions read the manual from the beginning. the manual explains the cpu, system control functions, peripheral functions and electrical characteristics in that order. ? to understanding cpu functions refer to the separate sh-4 software manual. explanatory note: bit sequence: upper bit at left, and lower bit at right list of related documents: the latest documents are available on our web site. please make sure that you have the latest version. (http://www.renesas.com/)
page vi of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? user manuals for SH7750, SH7750s, and SH7750r name of document document no. SH7750, SH7750s, SH7750r group hardware manual this manual sh-4 software manual rej09b0318-0600 ? user manuals for development tools name of document document no. superh ? risc engine c/c++ compiler, assembler, optimizing linkage editor user's manual rej10j1571-0100 superh ? risc engine simulator/debugger user's manual rej10b0210-0400 high-performance embedded workshop user's manual rej10j1737-0100
r01uh0456ej0702 rev. 7.02 page vii of lii sep 24, 2013 main revisions for this edition item page revision (s ee manual for details) all ? added onpac-bga products (hd6417750sba200v and hd6417750rba240hv) 1.1 SH7750, SH7750s, SH7750r groups features table 1.1 lsi features 8 table amended item features product lineup abbre- viation voltage (internal) operating frequency model no. package SH7750s 1.95 v 200 mhz hd6417750sbp200 256-pin bga hd6417750sba200 hd6417750sf200 1.8 v 167 mhz hd6417750sf167 1.5 v 133 mhz hd6417750svf133 208-pin qfp hd6417750svbt133 264-pin csp SH7750r 1.5 v 240 mhz hd6417750rbg240 292-pin bga hd6417750rbp240 256-pin bga hd6417750rba240h section 22 electrical characteristics ? added descriptions of hd6417750rba240hv and hd6417750sba200v 22.1 absolute maximum ratings table 22.1 absolute maximum ratings 895 table and table note amended item symbol value unit i/o, pll, rtc, cpg power supply volta g e v ddq v dd-pll1/2 v dd-rtc v dd-cpg ?0.3 to 4.2, ?0.3 to 4.6 * 1 v internal power supply volta g e v dd ?0.3 to 2.5, ?0.3 to 2.1 * 1 v input volta g e v in ?0.3 to v ddq +0.3 v operatin g temperature t opr ?20 to 75, ?40 to 85 * 2 c stora g e temperature t st g ?55 to 125 c notes: 1. hd6417750r only 2. hd6417750rba240hv only 22.2 dc characteristics table 22.2 dc characteristics (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba240hv) t a = ?20 to +75 c * 3 896, 897 table title amended and note added notes: 3. t a = ?40 to 85c for the hd6417750rba240hv.
page viii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 item page revision (s ee manual for details) 22.2 dc characteristics table 22.4 dc characteristics (hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba240hv * 3 ) t a = ?20 to +75 c * 4 900, 901 table title amended and note added notes: 3. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 4. t a = ?40 to 85c for the hd6417750rba240hv. table 22.6 dc characteristics (hd6417750sbp200 (v), hd6417750sba200v) 904 table title amended 22.3 ac characteristics table 22.15 clock timing (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba240hv) 920 table title amended table 22.17 clock timing (hd6417750bp200m (v), hd6417750sbp200 (v), hd6417750sba200v * , hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba240hv * ) table title amended and note added note: * this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 22.3.1 clock and control signal timing table 22.23 clock and control signal timing (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba240hv) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c * 2 , c l = 30 pf 922,923 table title amended and note added item standby return oscillation settlin g time 1 * 1 standby return oscillation settlin g time 2 * 1 standby return oscillation settlin g time 3 * 1 notes: 1. when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. 2. t a = ?40 to 85c for the hd6417750rba240hv.
r01uh0456ej0702 rev. 7.02 page ix of lii sep 24, 2013 item page revision (s ee manual for details) 22.3.1 clock and control signal timing table 22.25 clock and control signal timing (hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba240hv * 2 ) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c * 3 , c l = 30 pf 926, 927 table title amended and note added item standby return oscillation settlin g time 1 * 1 standby return oscillation settlin g time 2 * 1 standby return oscillation settlin g time 3 * 1 notes: 1. when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. 2. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 3. t a = ?40 to 85c for the hd6417750rba240hv. table 22.27 clock and control signal timing (hd6417750bp200m (v), hd6417750sbp200 (v), hd6417750sba200v) 930 table title amended 22.3.2 control signal timing table 22.32 control signal timing 946 table title and table amended hd6417750r bp240 (v) hd6417750r bg240 (v) hd6417750r ba240hv hd6417750r bp200 (v) hd6417750r bg200 (v) hd6417750r ba240hv * 5 hd6417750r f240 (v) hd6417750r f200 (v) * 1 * 1 * 1 * 1 item symbol min max min max min max min max unit figure table 22.33 control signal timing 947 table title, table and table note amended hd6417750v f128 (v) hd6417750 svf133 (v) hd6417750s vbt133 (v) hd6417750f 167 (v) hd6417750s f167 (v) hd6417750s f200 (v) hd6417750b p200m (v) hd6417750s bp200 (v) hd6417750s ba200v * 2 * 2 * 3 * 4 item symbol min max min max min max min max unit figure notes: 1. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c * 6 , c l = 30 pf, pll2 on 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 3. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 4. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 5. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 6. t a = ?40 to 85c for the hd6417750rba240hv.
page x of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 item page revision (s ee manual for details) 22.3.3 bus timing table 22.34 bus timing (1) 950,951 table and table note amended hd6417750r bp240 (v) hd6417750r bg240 (v) hd6417750r ba240hv hd6417750r bp200 (v) hd6417750r bg200 (v) hd6417750r ba240hv * 2 hd6417750r f240 (v) hd6417750r f200 (v) * 1 * 1 * 1 * 1 item symbol min max min max min max min max unit notes notes: 1. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c * 3 , c l = 30 pf, pll2 on 2. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 3. t a = ?40 to 85c for the hd6417750rba240hv. table 22.35 bus timing (2) 952, 953 table amended hd6417750 svf133 (v) hd6417750 svbt133 (v) hd6417750 sf167 (v) hd6417750 sf200 (v) hd6417750 sbp200 (v) hd6417750 sba200v * 1 * 2 * 3 item symbol min max min max min max unit notes 22.3.4 peripheral module signal timing table 22.37 peripheral module signal timing (1) 1003, 1005 table and table note amended hd6417750 rbp240 (v) hd6417750 rbg240 (v) hd6417750 rba240hv hd6417750 rbp200 (v) hd6417750r bg200 (v) hd6417750 rba240hv * 3 hd6417750 f240 (v) hd6417750 rf200 (v) * 2 * 2 * 2 * 2 module item symbol min max min max min max min max unit figure notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf * 4 , pll2 on 3. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 4. t a = ?40 to 85c for the hd6417750rba240hv. table 22.38 peripheral module signal timing (2) 1005, 1006 table amended hd6417750s vf133 (v) hd6417750s vbt133 (v) hd6417750 sf167 (v) hd6417750 sf200 (v) hd6417750 sbp200 (v) hd6417750 sba200v * 2 * 3 * 4 module item symbol min max min max min max unit figure table 22.39 peripheral module signal timing (3) 1007 table amended hd6417750s vf133 (v) hd6417750s vbt133 (v) hd6417750 sf167 (v) hd6417750 sf200 (v) hd6417750 sbp200 (v) hd6417750 sba200v * 2 * 3 * 4 module item symbol min max min max min max unit figure
r01uh0456ej0702 rev. 7.02 page xi of lii sep 24, 2013 item page revision (s ee manual for details) appendix b package dimensions figure b.1 package dimensions (256-pin bga: devices other than hd6417750rba240hv and hd6417750sba200v) 1023 figure title amended figure b.5 package dimensions (256-pin bga: hd6417750rba240hv and hd6417750sba200v) 1027 figure newly added appendix i product lineup table i.1 SH7750/ SH7750s/SH7750r product lineup 1067 table and table note amended product name voltage operating frequency operating temperature * 1 part number * 2 package SH7750s 1.95 v 200 mhz ?20 to 75?c hd6417750sbp200 (v) 256-pin bga ?20 to 75?c hd6417750sba200v ?20 to 75?c hd6417750sf200 (v) 208-pin qfp 1.8 v 167 mhz ?20 to 75?c hd6417750sf167 (v) 208-pin qfp 1.5 v 133 mhz ?20 to 75?c hd6417750svf133 (v) ?30 to 70?c hd6417750svbt133 (v) 264-pin csp SH7750r 1.5 v 240 mhz ?20 to 75?c hd6417750rbp240 (v) 256-pin bga ?20 to 75?c hd6417750rba240hv notes: 1. contact a renesas sales office regarding product versions with specifications for a wider temperature range (?40 to +85c). the wide temperature range (?40 to +85c) is the standard specification for the hd6417751rba240hv.
page xii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 all trademarks and registered trademarks ar e the property of th eir respective owners.
r01uh0456ej0702 rev. 7.02 page xiii of lii sep 24, 2013 contents section 1 overview................................................................................................1 1.1 SH7750, SH7750s, SH7750 r groups f eatures .................................................................... 1 1.2 block diagram .................................................................................................................. ..... 9 1.3 pin arrangement ................................................................................................................ .. 10 1.4 pin functions .................................................................................................................. ..... 14 1.4.1 pin functions (2 56-pin bg a)................................................................................. 14 1.4.2 pin functions (2 08-pin q fp).................................................................................. 24 1.4.3 pin functions (2 64-pin cs p) .................................................................................. 32 1.4.4 pin functions (2 92-pin bg a)................................................................................. 42 section 2 programming model ............................................................................53 2.1 data formats................................................................................................................... ..... 53 2.2 register conf igura tion......................................................................................................... 54 2.2.1 privileged mode and banks .................................................................................... 54 2.2.2 general registers.................................................................................................... 57 2.2.3 floating-point registers.......................................................................................... 59 2.2.4 control registers .................................................................................................... 62 2.2.5 system regi sters..................................................................................................... 63 2.3 memory-mapped registers.................................................................................................. 65 2.4 data format in registers...................................................................................................... 6 6 2.5 data formats in memory ..................................................................................................... 66 2.6 processor states ............................................................................................................... .... 67 2.7 processor modes ................................................................................................................ .. 69 section 3 memory management unit (mmu) ....................................................71 3.1 overview....................................................................................................................... ....... 71 3.1.1 features................................................................................................................... 71 3.1.2 role of the mmu.................................................................................................... 71 3.1.3 register conf iguration............................................................................................ 74 3.1.4 caution.................................................................................................................... 74 3.2 register de scriptions .......................................................................................................... .75 3.3 address space.................................................................................................................. .... 79 3.3.1 physical addr ess space .......................................................................................... 79 3.3.2 external memory space.......................................................................................... 82 3.3.3 virtual addr ess space............................................................................................. 83 3.3.4 on-chip ram space.............................................................................................. 84 3.3.5 address translation ................................................................................................ 85
page xiv of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 3.3.6 single virtual memory mode and multiple virtual memory mode ...................... 85 3.3.7 address space iden tifier (a sid) ............................................................................ 85 3.4 tlb functions .................................................................................................................. ... 86 3.4.1 unified tlb (utlb) configuration ...................................................................... 86 3.4.2 instruction tlb (itlb ) configuration................................................................... 90 3.4.3 address transla tion met hod................................................................................... 90 3.5 mmu functions.................................................................................................................. .93 3.5.1 mmu hardware management................................................................................ 93 3.5.2 mmu software management ................................................................................. 93 3.5.3 mmu instructio n (ldtlb).................................................................................... 93 3.5.4 hardware itlb miss handling .............................................................................. 94 3.5.5 avoiding synonym problems................................................................................. 95 3.6 mmu excep tions................................................................................................................. 96 3.6.1 instruction tlb multiple hit exception................................................................. 96 3.6.2 instruction tlb miss exception............................................................................. 96 3.6.3 instruction tlb protection violation exception .................................................... 98 3.6.4 data tlb multiple hit except ion .......................................................................... 98 3.6.5 data tlb miss exception ...................................................................................... 99 3.6.6 data tlb protection viol ation exception............................................................ 100 3.6.7 initial page write exception................................................................................. 101 3.7 memory-mapped tlb co nfiguration ............................................................................... 102 3.7.1 itlb address array ............................................................................................. 103 3.7.2 itlb data array 1................................................................................................ 104 3.7.3 itlb data array 2................................................................................................ 105 3.7.4 utlb address array............................................................................................ 106 3.7.5 utlb data array 1 .............................................................................................. 107 3.7.6 utlb data array 2 .............................................................................................. 108 3.8 usage notes .................................................................................................................... ... 109 section 4 caches................................................................................................ 111 4.1 overview....................................................................................................................... ..... 111 4.1.1 features................................................................................................................. 111 4.1.2 register config uration.......................................................................................... 113 4.2 register desc riptions......................................................................................................... 1 14 4.3 operand cach e (oc) ......................................................................................................... 116 4.3.1 configura tion........................................................................................................ 116 4.3.2 read operat ion ..................................................................................................... 120 4.3.3 write operation .................................................................................................... 121 4.3.4 write-back buffer ................................................................................................ 122 4.3.5 write-through buffer........................................................................................... 122
r01uh0456ej0702 rev. 7.02 page xv of lii sep 24, 2013 4.3.6 ram mode ........................................................................................................... 123 4.3.7 oc index mode .................................................................................................... 124 4.3.8 coherency between cache an d external memory ................................................ 125 4.3.9 prefetch operation ................................................................................................ 125 4.3.10 notes on using cache enhanced mode (SH7750r only) ................................... 125 4.4 instruction ca che (ic)........................................................................................................ 1 28 4.4.1 configura tion ........................................................................................................ 128 4.4.2 read opera tion ..................................................................................................... 130 4.4.3 ic index mode ...................................................................................................... 131 4.5 memory-mapped cache configura tion (SH7750, SH7750s) ........................................... 131 4.5.1 ic address array .................................................................................................. 131 4.5.2 ic data a rray........................................................................................................ 132 4.5.3 oc address array ................................................................................................ 133 4.5.4 oc data array ...................................................................................................... 135 4.6 memory-mapped cache config uration (sh7 750r).......................................................... 136 4.6.1 ic address array .................................................................................................. 137 4.6.2 ic data a rray........................................................................................................ 138 4.6.3 oc address array ................................................................................................ 139 4.6.4 oc data array ...................................................................................................... 141 4.6.5 summary of the memory-m apping of the oc...................................................... 142 4.7 store queues ................................................................................................................... ... 142 4.7.1 sq configuration.................................................................................................. 142 4.7.2 sq writes.............................................................................................................. 143 4.7.3 transfer to exte rnal memory................................................................................ 143 4.7.4 sq protec tion........................................................................................................ 145 4.7.5 reading the sqs (SH7750r only) ....................................................................... 145 4.7.6 sq usage notes .................................................................................................... 146 section 5 exceptions..........................................................................................149 5.1 overview....................................................................................................................... ..... 149 5.1.1 features................................................................................................................. 149 5.1.2 register config uration.......................................................................................... 149 5.2 register desc riptions ......................................................................................................... 1 50 5.3 exception handlin g functi ons........................................................................................... 151 5.3.1 exception hand ling flow ..................................................................................... 151 5.3.2 exception handling vect or addresses ................................................................. 151 5.4 exception types an d priorities .......................................................................................... 152 5.5 exceptio n fl ow ................................................................................................................. .155 5.5.1 exception flow ..................................................................................................... 155 5.5.2 exception source acceptance............................................................................... 156
page xvi of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 5.5.3 exception requests and bl bit ............................................................................ 158 5.5.4 return from excep tion handling.......................................................................... 158 5.6 description of exceptions.................................................................................................. 158 5.6.1 resets .................................................................................................................... 159 5.6.2 general exceptions............................................................................................... 164 5.6.3 interrupts............................................................................................................... 178 5.6.4 priority order with mu ltiple exceptions .............................................................. 181 5.7 usage notes .................................................................................................................... ... 182 5.8 restric tions ................................................................................................................... ..... 183 section 6 floating-point unit (fpu)................................................................. 185 6.1 overview....................................................................................................................... ..... 185 6.2 data formats................................................................................................................... ... 185 6.2.1 floating-point format........................................................................................... 185 6.2.2 non-numbers (nan) ............................................................................................ 187 6.2.3 denormalized nu mbers ........................................................................................ 188 6.3 registers ...................................................................................................................... ...... 189 6.3.1 floating-point re gisters ....................................................................................... 189 6.3.2 floating-point status/contro l register (fpscr) ................................................. 191 6.3.3 floating-point communicati on register (fpul) ................................................. 192 6.4 rounding....................................................................................................................... ..... 193 6.5 floating-point exceptions.................................................................................................. 193 6.6 graphics support functions............................................................................................... 195 6.6.1 geometric operation instructio ns......................................................................... 195 6.6.2 pair single-precision data transfer...................................................................... 196 6.7 usage notes .................................................................................................................... ... 197 6.7.1 rounding mode and un derflow flag ................................................................... 197 6.7.2 setting of overflow flag by fi pr or ftrv instruction ...................................... 198 6.7.3 sign of operation result when usin g fipr or ftrv instruction ....................... 199 6.7.4 notes on double-preci sion fadd and fsub instructions .................................. 199 6.7.5 notes on fpu double-precision opera tion instructions (s h7750 only)............. 200 section 7 instruction set.................................................................................... 209 7.1 execution envi ronment ..................................................................................................... 209 7.2 addressing modes ............................................................................................................. 21 1 7.3 instruction set ................................................................................................................ .... 215 7.4 usage notes .................................................................................................................... ... 227 7.4.1 notes on trapa instruction, sleep instruction, and undefined instruction (h'fffd) .............................................................................................................. 227
r01uh0456ej0702 rev. 7.02 page xvii of lii sep 24, 2013 section 8 pipelining ...........................................................................................231 8.1 pipelines...................................................................................................................... ....... 231 8.2 parallel-ex ecutab ility ......................................................................................................... 238 8.3 execution cycles and pipeline sta lling ............................................................................. 242 8.4 usage notes .................................................................................................................... ... 258 section 9 power-down modes ..........................................................................259 9.1 overview....................................................................................................................... ..... 259 9.1.1 types of power-down modes .............................................................................. 259 9.1.2 register config uration.......................................................................................... 261 9.1.3 pin configuration.................................................................................................. 261 9.2 register desc riptions ......................................................................................................... 2 62 9.2.1 standby control regi ster (st bcr)...................................................................... 262 9.2.2 peripheral module pin high impedance control.................................................. 264 9.2.3 peripheral module pin pull-up cont rol................................................................ 265 9.2.4 standby control regist er 2 (st bcr2)................................................................. 265 9.2.5 clock-stop register 00 (clk stp00) (SH7750r only) ...................................... 267 9.2.6 clock-stop clear register 00 (clk stpclr00) (SH7750r only) ..................... 268 9.3 sleep mode ..................................................................................................................... ... 268 9.3.1 transition to sl eep mode...................................................................................... 268 9.3.2 exit from sleep mode........................................................................................... 269 9.4 deep sleep mode............................................................................................................... 2 69 9.4.1 transition to deep sleep mode ............................................................................ 269 9.4.2 exit from deep sleep mode ................................................................................. 269 9.5 standby mode ................................................................................................................... .270 9.5.1 transition to st andby mode.................................................................................. 270 9.5.2 exit from standby mode....................................................................................... 271 9.5.3 clock pause f unction ........................................................................................... 271 9.6 module standby function.................................................................................................. 272 9.6.1 transition to module standby function ............................................................... 272 9.6.2 exit from module st andby func tion .................................................................... 273 9.7 hardware standby mode (s h7750s, SH7750r only) ...................................................... 274 9.7.1 transition to hardware standby mode................................................................. 274 9.7.2 exit from hardware standby m ode ...................................................................... 274 9.7.3 usage notes .......................................................................................................... 275 9.8 status pin chan ge timing ............................................................................................ 275 9.8.1 in reset ................................................................................................................. 276 9.8.2 in exit from standby mode .................................................................................. 277 9.8.3 in exit from sleep mode....................................................................................... 279 9.8.4 in exit from deep sleep mode ............................................................................. 281
page xviii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 9.8.5 hardware standby mo de timing (SH7750s, SH7750r only) ............................ 283 9.9 usage notes .................................................................................................................... ... 286 9.9.1 note on current consumption .............................................................................. 286 section 10 clock oscillation circuits ............................................................... 287 10.1 overview....................................................................................................................... ..... 287 10.1.1 features................................................................................................................. 287 10.2 overview of cpg............................................................................................................... 2 89 10.2.1 block diagram of cpg......................................................................................... 289 10.2.2 cpg pin config uration......................................................................................... 292 10.2.3 cpg register conf iguratio n................................................................................. 292 10.3 clock operatin g modes ..................................................................................................... 293 10.4 cpg register de scription.................................................................................................. 295 10.4.1 frequency control re gister (f rqcr) ................................................................. 295 10.5 changing the frequency .................................................................................................... 298 10.5.1 changing pll circuit 1 starting/stoppin g (when pll circuit 2 is off) ............ 298 10.5.2 changing pll circuit 1 starting/stoppin g (when pll circuit 2 is on)............. 298 10.5.3 changing bus clock division ratio (when pll circuit 2 is on)....................... 299 10.5.4 changing bus clock division ratio (when pll circuit 2 is off) ...................... 299 10.5.5 changing cpu or peri pheral module clock division ra tio ................................ 299 10.6 output clock control......................................................................................................... 29 9 10.7 overview of watchdog timer ........................................................................................... 300 10.7.1 block diag ram...................................................................................................... 300 10.7.2 register config uration.......................................................................................... 301 10.8 wdt register de scriptions............................................................................................... 301 10.8.1 watchdog timer coun ter (wtcnt).................................................................... 301 10.8.2 watchdog timer control/statu s register (w tcsr)............................................ 302 10.8.3 notes on regist er access ..................................................................................... 305 10.9 using the wdt.................................................................................................................. 305 10.9.1 standby clearing procedure ................................................................................. 305 10.9.2 frequency changing procedure............................................................................ 306 10.9.3 using watchdog ti mer mode .............................................................................. 306 10.9.4 using interval timer mode .................................................................................. 307 10.10 notes on boar d design ...................................................................................................... 307 10.11 usage notes .................................................................................................................... ... 309 10.11.1 invalid manual reset triggered by watchdog timer (SH7750 and SH7750s)... 309 section 11 realtime clock (rtc)..................................................................... 311 11.1 overview....................................................................................................................... ..... 311 11.1.1 features................................................................................................................. 311
r01uh0456ej0702 rev. 7.02 page xix of lii sep 24, 2013 11.1.2 block diag ram...................................................................................................... 312 11.1.3 pin configuration.................................................................................................. 313 11.1.4 register config uration.......................................................................................... 313 11.2 register desc riptions ......................................................................................................... 3 15 11.2.1 64 hz counter (r64cnt)..................................................................................... 315 11.2.2 second counter (rseccnt) ............................................................................... 316 11.2.3 minute counter (r mincnt) ............................................................................... 316 11.2.4 hour counter (rhrcnt)..................................................................................... 317 11.2.5 day-of-week counte r (rwkcnt)...................................................................... 317 11.2.6 day counter (r daycnt) ................................................................................... 318 11.2.7 month counter (r moncnt) .............................................................................. 318 11.2.8 year counter (ryrcnt) ..................................................................................... 319 11.2.9 second alarm regist er (rsecar) ...................................................................... 320 11.2.10 minute alarm regist er (rminar)...................................................................... 320 11.2.11 hour alarm regist er (rhrar) ........................................................................... 321 11.2.12 day-of-week alarm regi ster (rwkar)............................................................. 321 11.2.13 day alarm register (rdaya r).......................................................................... 322 11.2.14 month alarm regist er (rmonar) ..................................................................... 323 11.2.15 rtc control regist er 1 (rcr1)........................................................................... 323 11.2.16 rtc control regist er 2 (rcr2)........................................................................... 325 11.2.17 rtc control register 3 (rcr3) and year-alarm register (ryrar) (SH7750r only) ................................................................................................... 327 11.3 operation ...................................................................................................................... ..... 329 11.3.1 time setting pr ocedures ....................................................................................... 329 11.3.2 time reading pr ocedures ..................................................................................... 330 11.3.3 alarm func tion ..................................................................................................... 332 11.4 interrupts..................................................................................................................... ....... 333 11.5 usage notes .................................................................................................................... ... 333 11.5.1 register initia lization............................................................................................ 333 11.5.2 carry flag and interrupt fl ag in standb y mode ................................................... 333 11.5.3 crystal oscillato r circuit ...................................................................................... 333 11.5.4 rtc register settings (SH7750 on ly).................................................................. 334 section 12 timer unit (tmu) ...........................................................................337 12.1 overview....................................................................................................................... ..... 337 12.1.1 features................................................................................................................. 337 12.1.2 block diag ram...................................................................................................... 338 12.1.3 pin configuration.................................................................................................. 338 12.1.4 register config uration.......................................................................................... 339 12.2 register desc riptions ......................................................................................................... 3 41
page xx of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 12.2.1 timer output control register (t ocr)............................................................... 341 12.2.2 timer start regist er (tstr) ................................................................................ 342 12.2.3 timer start register 2 (t str2) (SH7750r only) ............................................... 343 12.2.4 timer constant regi sters (tco r) ....................................................................... 344 12.2.5 timer counters (tcnt) ....................................................................................... 344 12.2.6 timer control regi sters (tcr) ............................................................................ 345 12.2.7 input capture regist er 2 (tcpr2) ....................................................................... 350 12.3 operation ...................................................................................................................... ..... 350 12.3.1 counter operation ................................................................................................ 350 12.3.2 input capture function ......................................................................................... 353 12.4 interrupts..................................................................................................................... ....... 355 12.5 usage notes .................................................................................................................... ... 355 12.5.1 register wr ites ..................................................................................................... 355 12.5.2 underflow flag writes (SH7750 only)................................................................. 356 12.5.3 tcnt register reads........................................................................................... 356 12.5.4 resetting the rtc fre quency divider.................................................................. 356 12.5.5 external clock frequency .................................................................................... 356 section 13 bus state controller (bsc) ............................................................. 357 13.1 overview....................................................................................................................... ..... 357 13.1.1 features................................................................................................................. 357 13.1.2 block diag ram...................................................................................................... 359 13.1.3 pin configuration.................................................................................................. 360 13.1.4 register config uration.......................................................................................... 364 13.1.5 overview of areas................................................................................................ 365 13.1.6 pcmcia s upport ................................................................................................. 368 13.2 register desc riptions......................................................................................................... 3 72 13.2.1 bus control regist er 1 (bcr1) ............................................................................ 372 13.2.2 bus control regist er 2 (bcr2) ............................................................................ 381 13.2.3 bus control register 3 ( bcr3) (SH7750r only)................................................ 383 13.2.4 bus control register 4 ( bcr4) (SH7750r only)................................................ 384 13.2.5 wait control regist er 1 (wcr1) ......................................................................... 388 13.2.6 wait control regist er 2 (wcr2) ......................................................................... 391 13.2.7 wait control regist er 3 (wcr3) ......................................................................... 399 13.2.8 memory control re gister (m cr)......................................................................... 401 13.2.9 pcmcia control re gister (p cr) ........................................................................ 409 13.2.10 synchronous dram mode register (s dmr) ..................................................... 413 13.2.11 refresh timer control/statu s register (r tcsr)................................................. 415 13.2.12 refresh timer coun ter (rtcnt)......................................................................... 418 13.2.13 refresh time constant register (rtcor) .......................................................... 419
r01uh0456ej0702 rev. 7.02 page xxi of lii sep 24, 2013 13.2.14 refresh count regi ster (rfcr) ........................................................................... 420 13.2.15 notes on accessing refres h control regi sters .................................................... 420 13.3 operation ...................................................................................................................... ..... 421 13.3.1 endian/access size and da ta alignment.............................................................. 421 13.3.2 areas ..................................................................................................................... 433 13.3.3 sram interface.................................................................................................... 438 13.3.4 dram interface ................................................................................................... 447 13.3.5 synchronous dram interface ............................................................................. 465 13.3.6 burst rom in terface ............................................................................................ 497 13.3.7 pcmcia interface................................................................................................ 500 13.3.8 mpx interface....................................................................................................... 511 13.3.9 byte control sram interface .............................................................................. 529 13.3.10 waits between a ccess cycl es............................................................................... 534 13.3.11 bus arbitra tion ..................................................................................................... 536 13.3.12 master mo de......................................................................................................... 539 13.3.13 slave mode ........................................................................................................... 540 13.3.14 partial-sharing ma ster mode................................................................................ 541 13.3.15 cooperation between ma ster and slave................................................................ 542 13.3.16 notes on usage ..................................................................................................... 543 section 14 direct memory access controller (dmac) ...................................545 14.1 overview....................................................................................................................... ..... 545 14.1.1 features................................................................................................................. 545 14.1.2 block diagram (sh7 750, SH7750 s) .................................................................... 547 14.1.3 pin configuration (s h7750, SH7750s)................................................................ 549 14.1.4 register configuration (SH7750, sh 7750s)........................................................ 550 14.2 register descriptions (SH7750, sh77 50s) ....................................................................... 552 14.2.1 dma source address register s 0?3 (sar0?sar3) ........................................... 552 14.2.2 dma destination address regi sters 0?3 (dar0?dar3)................................... 553 14.2.3 dma transfer count registers 0?3 (dmatcr0?dmatcr3).......................... 554 14.2.4 dma channel control register s 0?3 (chcr0?chcr3).................................... 555 14.2.5 dma operation regist er (dmaor) ................................................................... 564 14.3 operation ...................................................................................................................... ..... 567 14.3.1 dma transfer pr ocedure ..................................................................................... 567 14.3.2 dma transfer requests ....................................................................................... 569 14.3.3 channel prio rities ................................................................................................. 573 14.3.4 types of dma transfer........................................................................................ 576 14.3.5 number of bus cycle states and dreq pin sampling timing ........................... 585 14.3.6 ending dma tr ansfer .......................................................................................... 599 14.4 examples of use ................................................................................................................ 602
page xxii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.4.1 examples of transfer between extern al memory and an external device with dack........................................................................................................... 602 14.5 on-demand data transfer mode (ddt mode) ................................................................ 603 14.5.1 operation .............................................................................................................. 603 14.5.2 pins in ddt mode................................................................................................ 605 14.5.3 transfer request acceptance on each channel ................................................... 608 14.5.4 notes on use of ddt module .............................................................................. 631 14.6 configuration of the dmac (sh7 750r)........................................................................... 634 14.6.1 block diagram of the dmac............................................................................... 634 14.6.2 pin configurati on (SH7750r) .............................................................................. 636 14.6.3 register configurat ion (sh775 0r) ...................................................................... 637 14.7 register descripti ons (SH7750r)...................................................................................... 640 14.7.1 dma source address registers 0 ? 7 (sar0 ? sar7)........................................... 640 14.7.2 dma destination address registers 0 ? 7 (dar0 ? dar7) .................................. 640 14.7.3 dma transfer count registers 0 ? 7 (dmatcr0 ? dmatcr7) ......................... 641 14.7.4 dma channel control registers 0 ? 7 (chcr0 ? chcr7) ................................... 641 14.7.5 dma operation regist er (dmaor) ................................................................... 645 14.8 operation (s h7750r) ........................................................................................................ 647 14.8.1 channel specification for a normal dma transfer............................................. 647 14.8.2 channel specification for ddt -mode dma tr ansfer ......................................... 647 14.8.3 transfer channel notifi cation in dd t mode....................................................... 648 14.8.4 clearing request queues by dtr format ........................................................... 649 14.8.5 interrupt-request codes ....................................................................................... 649 14.9 usage notes .................................................................................................................... ... 652 section 15 serial communication interface (sci)............................................ 655 15.1 overview....................................................................................................................... ..... 655 15.1.1 features................................................................................................................. 655 15.1.2 block diag ram...................................................................................................... 657 15.1.3 pin configuration.................................................................................................. 658 15.1.4 register config uration.......................................................................................... 658 15.2 register desc riptions......................................................................................................... 6 59 15.2.1 receive shift regist er (scrsr1) ........................................................................ 659 15.2.2 receive data regist er (scrdr1 ) ........................................................................ 660 15.2.3 transmit shift regi ster (sctsr1) ....................................................................... 660 15.2.4 transmit data regi ster (sct dr1)....................................................................... 661 15.2.5 erial mode regist er (scsmr1)............................................................................ 661 15.2.6 serial control regi ster (scs cr1)........................................................................ 664 15.2.7 serial status regi ster (scssr1) .......................................................................... 667 15.2.8 serial port regist er (scsptr1) ........................................................................... 671
r01uh0456ej0702 rev. 7.02 page xxiii of lii sep 24, 2013 15.2.9 bit rate regist er (scbrr1 ) ................................................................................ 676 15.3 operation ...................................................................................................................... ..... 684 15.3.1 overview............................................................................................................... 684 15.3.2 operation in asynch ronous mode ........................................................................ 686 15.3.3 multiprocessor co mmunication f unction............................................................. 698 15.3.4 operation in sync hronous mode .......................................................................... 707 15.4 sci interrupt sources and dmac ..................................................................................... 717 15.5 usage notes .................................................................................................................... ... 718 section 16 serial communication interface with fifo (scif) ........................725 16.1 overview....................................................................................................................... ..... 725 16.1.1 features................................................................................................................. 725 16.1.2 block diag ram...................................................................................................... 727 16.1.3 pin configuration.................................................................................................. 728 16.1.4 register config uration.......................................................................................... 729 16.2 register desc riptions ......................................................................................................... 7 29 16.2.1 receive shift regist er (scrsr2 )......................................................................... 729 16.2.2 receive fifo data regi ster (scfrd r2) ............................................................ 730 16.2.3 transmit shift regist er (sctsr2) ....................................................................... 730 16.2.4 transmit fifo data regi ster (scftdr2) ........................................................... 731 16.2.5 serial mode regist er (scsmr2).......................................................................... 731 16.2.6 serial control regi ster (scs cr2)........................................................................ 734 16.2.7 serial status regi ster (scfsr2) .......................................................................... 737 16.2.8 bit rate regist er (scbrr2 ) ................................................................................ 744 16.2.9 fifo control regist er (scfcr2) ........................................................................ 745 16.2.10 fifo data count regi ster (scfdr2) .................................................................. 749 16.2.11 serial port regist er (scsptr2) ........................................................................... 750 16.2.12 line status regist er (sclsr2) ............................................................................ 756 16.3 operation ...................................................................................................................... ..... 757 16.3.1 overview............................................................................................................... 757 16.3.2 serial oper ation .................................................................................................... 758 16.4 scif interrupt sources and the dmac ............................................................................. 769 16.5 usage notes .................................................................................................................... ... 770 section 17 smart card interface ........................................................................775 17.1 overview....................................................................................................................... ..... 775 17.1.1 features................................................................................................................. 775 17.1.2 block diag ram...................................................................................................... 776 17.1.3 pin configuration.................................................................................................. 777 17.1.4 register config uration.......................................................................................... 777
page xxiv of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 17.2 register desc riptions......................................................................................................... 7 78 17.2.1 smart card mode regi ster (scscm r1) .............................................................. 778 17.2.2 serial mode regist er (scsmr1).......................................................................... 779 17.2.3 serial control regi ster (scs cr1)........................................................................ 780 17.2.4 serial status regi ster (scssr1) .......................................................................... 781 17.3 operation ...................................................................................................................... ..... 782 17.3.1 overview .............................................................................................................. 782 17.3.2 pin connections .................................................................................................... 783 17.3.3 data format .......................................................................................................... 784 17.3.4 register se ttings ................................................................................................... 785 17.3.5 clock..................................................................................................................... 787 17.3.6 data transmit/receive operations ....................................................................... 790 17.4 usage notes .................................................................................................................... ... 797 section 18 i/o ports........................................................................................... 803 18.1 overview....................................................................................................................... ..... 803 18.1.1 features................................................................................................................. 803 18.1.2 block diag rams .................................................................................................... 804 18.1.3 pin configuration.................................................................................................. 811 18.1.4 register config uration.......................................................................................... 813 18.2 register desc riptions......................................................................................................... 8 14 18.2.1 port control regist er a (pctra)........................................................................ 814 18.2.2 port data register a (pdtra) ............................................................................ 815 18.2.3 port control regist er b (pct rb) ........................................................................ 816 18.2.4 port data regist er b (pdt rb)............................................................................. 817 18.2.5 gpio interrupt control register (g pioic).......................................................... 818 18.2.6 serial port regist er (scsptr1) ........................................................................... 819 18.2.7 serial port regist er (scsptr2) ........................................................................... 821 section 19 interrupt controller (intc)............................................................. 825 19.1 overview....................................................................................................................... ..... 825 19.1.1 features................................................................................................................. 825 19.1.2 block diag ram...................................................................................................... 825 19.1.3 pin configuration.................................................................................................. 827 19.1.4 register config uration.......................................................................................... 827 19.2 interrupt sources.............................................................................................................. .. 828 19.2.1 nmi interrupt........................................................................................................ 828 19.2.2 irl interr upts ....................................................................................................... 829 19.2.3 on-chip peripheral mo dule interr upts ................................................................. 831 19.2.4 interrupt exception hand ling and prio rity............................................................ 832
r01uh0456ej0702 rev. 7.02 page xxv of lii sep 24, 2013 19.3 register desc riptions ......................................................................................................... 8 35 19.3.1 interrupt priority register s a to d (ipr a?iprd) ................................................ 835 19.3.2 interrupt control re gister (i cr)........................................................................... 837 19.3.3 interrupt-priority-level setting register 00 (intpri00) (sh 7750r only)......... 839 19.3.4 interrupt source register 00 (i ntreq00) (SH7750r only)............................... 840 19.3.5 interrupt mask register 00 (in tmsk00) (SH7750r only) ................................ 841 19.3.6 interrupt mask clear register 00 (intmskclr00) (sh 7750r only) ............... 842 19.3.7 bit assignments of intreq00, intmsk00, and intmskclr00 (SH7750r only) ................................................................................................... 842 19.4 intc oper ation ................................................................................................................. 843 19.4.1 interrupt operati on sequence ............................................................................... 843 19.4.2 multiple inte rrupts ................................................................................................ 845 19.4.3 interrupt masking w ith mai bit........................................................................... 845 19.5 interrupt respon se time.................................................................................................... 846 19.6 usage notes .................................................................................................................... ... 847 19.6.1 nmi interrupts (SH7750 and SH7750s only)...................................................... 847 section 20 user break controller (ubc) ..........................................................851 20.1 overview....................................................................................................................... ..... 851 20.1.1 features................................................................................................................. 851 20.1.2 block diag ram...................................................................................................... 852 20.2 register desc riptions ......................................................................................................... 8 54 20.2.1 access to ubc contro l register s......................................................................... 854 20.2.2 break address regist er a (bara) ...................................................................... 855 20.2.3 break asid register a (basra)........................................................................ 856 20.2.4 break address mask regi ster a (bamra)......................................................... 856 20.2.5 break bus cycle regi ster a ( bbra)................................................................... 857 20.2.6 break address regist er b (ba rb) ...................................................................... 859 20.2.7 break asid regist er b (bas rb) ........................................................................ 859 20.2.8 break address mask re gister b (b amrb) ......................................................... 859 20.2.9 break data regist er b (bdrb) ............................................................................ 859 20.2.10 break data mask regi ster b (b dmrb)............................................................... 860 20.2.11 break bus cycle regi ster b ( bbrb) ................................................................... 861 20.2.12 break control regi ster (brc r) ........................................................................... 861 20.3 operation ...................................................................................................................... ..... 864 20.3.1 explanation of terms re lating to a ccesses.......................................................... 864 20.3.2 explanation of terms relating to instruction in tervals ........................................ 864 20.3.3 user break opera tion sequenc e ........................................................................... 865 20.3.4 instruction access cycle break ............................................................................ 866 20.3.5 operand access cy cle break................................................................................ 867
page xxvi of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 20.3.6 condition match fl ag settin g............................................................................... 868 20.3.7 program counter (pc) value saved ..................................................................... 868 20.3.8 contiguous a and b settings fo r sequential co nditions ...................................... 869 20.3.9 usage notes .......................................................................................................... 870 20.4 user break debug s upport func tion ................................................................................. 872 20.5 examples of use ................................................................................................................ 874 20.6 user break controller stop function................................................................................. 876 20.6.1 transition to user break co ntroller stoppe d state............................................... 876 20.6.2 cancelling the user break co ntroller stopped state............................................ 876 20.6.3 examples of stopping and restarti ng the user break controller......................... 877 section 21 high-performance u ser debug interface (h-udi) ......................... 879 21.1 overview....................................................................................................................... ..... 879 21.1.1 features................................................................................................................. 879 21.1.2 block diag ram...................................................................................................... 879 21.1.3 pin configuration.................................................................................................. 881 21.1.4 register config uration.......................................................................................... 882 21.2 register desc riptions......................................................................................................... 8 83 21.2.1 instruction regist er (sdir) .................................................................................. 883 21.2.2 data register (sddr) .......................................................................................... 885 21.2.3 bypass register (sdbpr) .................................................................................... 886 21.2.4 interrupt source register (s dint) (SH7750r only) .......................................... 886 21.2.5 boundary scan register (sdb sr) (SH7750r only) ........................................... 887 21.3 operation ...................................................................................................................... ..... 891 21.3.1 tap control ......................................................................................................... 891 21.3.2 h-udi reset ......................................................................................................... 892 21.3.3 h-udi interrupt .................................................................................................... 892 21.3.4 boundary scan (extest, sample/preload, bypass) (SH7750r only)................................................................................................... 893 21.4 usage notes .................................................................................................................... ... 893 section 22 electrical characteristics ................................................................. 895 22.1 absolute maximum ratings .............................................................................................. 895 22.2 dc charact eristics ............................................................................................................. 896 22.3 ac charact eristics ............................................................................................................. 920 22.3.1 clock and control signal timing ......................................................................... 922 22.3.2 control signal timing .......................................................................................... 946 22.3.3 bus timing ........................................................................................................... 950 22.3.4 peripheral module si gnal timi ng....................................................................... 1003 22.3.5 ac characteristic te st condit ions ..................................................................... 1015
r01uh0456ej0702 rev. 7.02 page xxvii of lii sep 24, 2013 22.3.6 delay time variation due to load capaci tance ................................................ 1016 appendix a address list ................................................................................1017 appendix b package dimensions....................................................................1023 appendix c mode pin settings .......................................................................1029 appendix d ckio2enb pin configuration ...................................................1033 appendix e pin functions ...............................................................................1035 e.1 pin states..................................................................................................................... ..... 1035 e.2 handling of unus ed pins ................................................................................................. 1038 appendix f synchronous dram address multiplexing tables ...................1039 appendix g prefetching of instru ctions and its side effects ..........................1061 appendix h power-on and power-off procedures.........................................1063 h.1 power-on stip ulations ..................................................................................................... 1063 h.2 power-off stip ulations .................................................................................................... 1063 h.3 common stipulations for po wer-on and po wer-off ....................................................... 1064 appendix i product lineup..............................................................................1067 appendix j version registers..........................................................................1069 index .......................................................................................................1071
page xxviii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013
r01uh0456ej0702 rev. 7.02 page xxix of lii sep 24, 2013 figures section 1 overview figure 1.1 block diagram of sh7 750/SH7750s/SH7750r group functions ............................... 9 figure 1.2 pin arrangement (256-pin bga) ................................................................................ 10 figure 1.3 pin arrangement (208-pin qfp) ................................................................................. 11 figure 1.4 pin arrangement (264-pin csp) ................................................................................. 12 figure 1.5 pin arrangement (292-pin bga) ................................................................................ 13 section 2 programming model figure 2.1 data formats ...................................................................................................... ......... 53 figure 2.2 cpu register config uration in each processor mode................................................ 56 figure 2.3 ge neral regi sters ................................................................................................. ....... 58 figure 2.4 floati ng-point registers .......................................................................................... .... 61 figure 2.5 data formats in memory ............................................................................................ 67 figure 2.6 proces sor state tr ansitions....................................................................................... ... 68 section 3 memory management unit (mmu) figure 3.1 role of the mmu ................................................................................................... ..... 73 figure 3.2 mmu- related registers............................................................................................. .75 figure 3.3 physical ad dress space (mmucr.at = 0) ............................................................... 79 figure 3.4 p4 area........................................................................................................... ............. 81 figure 3.5 external memory space ............................................................................................. .82 figure 3.6 vi rtual address space (mmucr.at = 1).................................................................. 83 figure 3.7 utlb configuration ................................................................................................ ... 86 figure 3.8 relationship between page size and ad dress format................................................. 87 figure 3.9 itlb configur ation................................................................................................ ..... 90 figure 3.10 flowchart of memory access using utlb.............................................................. 91 figure 3.11 flowchart of memory access using itlb ............................................................... 92 figure 3.12 operation of ldtlb instruction............................................................................... 94 figure 3.13 memory-mappe d itlb addre ss array................................................................... 103 figure 3.14 memory-mappe d itlb data array 1 ..................................................................... 104 figure 3.15 memory-mappe d itlb data array 2 ..................................................................... 105 figure 3.16 memory-mappe d utlb address array ................................................................. 107 figure 3.17 memory-mappe d utlb data array 1.................................................................... 108 figure 3.18 memory-mappe d utlb data array 2.................................................................... 109
page xxx of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 section 4 caches figure 4.1 cache and store queue control registers ................................................................ 114 figure 4.2 configuration of op erand cache (SH7750 , SH7750s)............................................. 117 figure 4.3 configuration of operand cache (SH7750r) ........................................................... 118 figure 4.4 configuratio n of write-bac k buffer ......................................................................... 122 figure 4.5 configuration of write-throu gh buffer .................................................................... 122 figure 4.6 configuration of inst ruction cache (sh775 0, SH7750s) ......................................... 128 figure 4.7 configuration of instruction cache (SH7750r)........................................................ 129 figure 4.8 me mory-mapped ic ad dress array ......................................................................... 132 figure 4.9 memory-map ped ic data array ............................................................................... 133 figure 4.10 memory-ma pped oc address array ...................................................................... 134 figure 4.11 memory-ma pped oc data array ........................................................................... 135 figure 4.12 memory-ma pped ic addres s array ....................................................................... 138 figure 4.13 memory-ma pped ic data array ............................................................................. 139 figure 4.14 memory-ma pped oc address array ...................................................................... 140 figure 4.15 memory-ma pped oc data array ........................................................................... 141 figure 4.16 store queue configuration...................................................................................... 14 3 section 5 exceptions figure 5.1 register bit config urations....................................................................................... 150 figure 5.2 instruction execu tion and exception handling......................................................... 155 figure 5.3 example of general exception acceptance or der.................................................... 157 section 6 floating -point unit (fpu) figure 6.1 format of single-pr ecision floating-p oint number.................................................. 185 figure 6.2 format of double-p recision floating- point number ................................................ 186 figure 6.3 single-preci sion nan bit pattern.............................................................................. 188 figure 6.4 floatin g-point registers .......................................................................................... .. 190 section 8 pipelining figure 8.1 basic pi pelines ................................................................................................... ....... 232 figure 8.2 instruct ion execution patterns................................................................................... 2 33 figure 8.3 examples of pipelined ex ecution.............................................................................. 245 section 9 power-down modes figure 9.1 status output in power-on reset ........................................................................ 276 figure 9.2 status outp ut in manual reset............................................................................. 276 figure 9.3 status output in standby interrupt sequence.................................................. 277 figure 9.4 status output in standby power-on rese t sequence ..................................... 277
r01uh0456ej0702 rev. 7.02 page xxxi of lii sep 24, 2013 figure 9.5 status output in standby manual reset sequence.......................................... 278 figure 9.6 status output in sleep interrupt sequence...................................................... 279 figure 9.7 status output in sleep power-on rese t sequence.......................................... 279 figure 9.8 status output in sleep manual reset sequence.............................................. 280 figure 9.9 status output in deep sleep interrupt sequence ............................................ 281 figure 9.10 status output in deep sleep power-on reset sequence .............................. 281 figure 9.11 status output in deep sleep manual reset sequence .................................. 282 figure 9.12 hardware sta ndby mode timing (when ca = lo w in normal operation) ........... 283 figure 9.13 hardware st andby mode timing (when ca = low in wdt operation) .............. 284 figure 9.14 timing when power other than vdd-rtc is off................................................. 285 figure 9.15 timing when vdd-rtc power is off on........................................................ 285 section 10 clock oscillation circuits figure 10.1 (1) block diagra m of cpg (SH7750 , SH7750s) .................................................... 289 figure 10.1 (2) block di agram of cpg (SH7750r) .................................................................. 290 figure 10.2 block diagram of wdt .......................................................................................... 300 figure 10.3 writing to wtcnt and wtcsr............................................................................ 305 figure 10.4 points for attenti on when using crysta l resonato r................................................ 307 figure 10.5 points for attention wh en using pll oscill ator circuit ........................................ 308 section 11 realtime clock (rtc) figure 11.1 bloc k diagram of rtc ........................................................................................... 31 2 figure 11.2 examples of time setting pr ocedures..................................................................... 329 figure 11.3 examples of time reading pr ocedures ................................................................... 331 figure 11.4 example of use of alarm function......................................................................... 332 figure 11.5 example of crystal oscillator circui t connection .................................................. 334 section 12 timer unit (tmu) figure 12.1 block diagram of tmu .......................................................................................... 338 figure 12.2 example of coun t operation setting procedure ..................................................... 351 figure 12.3 tcnt au to-reload oper ation ................................................................................ 352 figure 12.4 count timing when operating on inte rnal cloc k ................................................... 352 figure 12.5 count timing when operating on exte rnal clock .................................................. 353 figure 12.6 count timing when oper ating on on-chip rtc output cl ock............................. 353 figure 12.7 operation timing wh en using input capt ure function .......................................... 354 section 13 bus state controller (bsc) figure 13.1 bloc k diagram of bsc............................................................................................ 3 59 figure 13.2 correspondence between virtua l address space and external memory space...... 365 figure 13.3 external memory space a llocation ........................................................................ 367
page xxxii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 13.4 example of rdy sampling timing at which bcr4 is set (two wait cycles are in serted by wcr2) ............................................................ 385 figure 13.5 writing to rtcsr, rtcnt, rtcor, and rfcr.................................................. 421 figure 13.6 basic timing of sram in terface............................................................................ 439 figure 13.7 example of 64-bit data width sram connection ................................................ 440 figure 13.8 example of 32-bit data width sram connection ................................................ 441 figure 13.9 example of 16-bit data width sram connection ................................................ 442 figure 13.10 example of 8-bit data width sram connection ................................................ 443 figure 13.11 sram interface wa it timing (softwar e wait only ) ........................................... 444 figure 13.12 sram interface wait state timing (wait state insertion by rdy signal) ......... 445 figure 13.13 sram interface read-strobe nega te timing (ans = 1, anw = 4, anh = 2) ..... 446 figure 13.14 example of dram conn ection (64-bit data width, area 3) .............................. 448 figure 13.15 example of dram conn ection (32-bit data width, area 3) .............................. 449 figure 13.16 example of dram connectio n (16-bit data width, areas 2 and 3) ................... 450 figure 13.17 basic dram access timing ................................................................................ 452 figure 13.18 dram wait state timing .................................................................................... 453 figure 13.19 dram burst access timing ................................................................................ 454 figure 13.20 dram bus cycle (edo mode, rcd = 0, anw = 0, tpc = 1)........................... 455 figure 13.21 burst access timing in dram edo mode......................................................... 456 figure 13.22 (1) dram burst bus cycle, ras down mode start (fast page mode, rcd = 0, anw = 0)............................................................ 457 figure 13.22 (2) dram burst bus cycle, ras down mode continuation (fast page mode, rcd = 0, anw = 0)............................................................ 458 figure 13.22 (3) dram burst bus cycle, ras down mode start (edo mode, rcd = 0, anw = 0)................................................................... 459 figure 13.22 (4) dram burst bus cycle, ras down mode continuation (edo mode, rcd = 0, anw = 0)................................................................... 460 figure 13.23 cas-before-r as refresh op eration.................................................................... 461 figure 13.24 dram cas-before-ras refre sh cycle timing (tras = 0, trc = 1)............. 462 figure 13.25 dram sel f-refresh cycle timing....................................................................... 464 figure 13.26 example of 64-bit data widt h synchronous dram connection (area 3).......... 466 figure 13.27 example of 32-bit data widt h synchronous dram connection (area 3).......... 467 figure 13.28 basic timing for synchronous dram burst read .............................................. 469 figure 13.29 basic timing for synchronous dram single read............................................. 471 figure 13.30 basic timing for synchronous dram burst write ............................................. 473 figure 13.31 basic timing for synchronous dram single write............................................ 474 figure 13.32 bu rst read timing ............................................................................................... .476 figure 13.33 burst read timing (ras down, same row addres s)......................................... 477 figure 13.34 burst read timing (r as down, different row addresses)................................ 478 figure 13.35 bu rst write timing .............................................................................................. .479
r01uh0456ej0702 rev. 7.02 page xxxiii of lii sep 24, 2013 figure 13.36 burst write ti ming (same row address)............................................................. 480 figure 13.37 burst write timing (different row addresses) ................................................... 481 figure 13.38 burst read cycle for di fferent bank and row address following preceding burst r ead cycle .................................................................................. 483 figure 13.39 auto-r efresh operation ........................................................................................ 48 5 figure 13.40 synchronous dr am auto-refresh timing.......................................................... 485 figure 13.41 synchronous dr am self-refresh timing ........................................................... 487 figure 13.42 (1) synchronous dr am mode write ti ming (pall) ......................................... 490 figure 13.42 (2) synchronous dram mode write timing (mode register set) ..................... 491 figure 13.43 basic timing of synchronous dram burst read (b urst length = 4) ................. 492 figure 13.44 basic timing of a burst write to sync hronous dram........................................ 494 figure 13.45 example of the connection of synchronous dram with 64-bit bus width (256 mbits ) ............................................................................................................ 495 figure 13.46 synchronous dram auto-refresh timing with 64-bit bus width (tras[2:0] = 001 , trc[2:0] = 001)..................................................................... 496 figure 13.47 burst ro m basic access timing ......................................................................... 498 figure 13.48 burst ro m wait access timing........................................................................... 499 figure 13.49 burst ro m wait access timing........................................................................... 500 figure 13.50 example of pcmcia interface ............................................................................. 504 figure 13.51 basic timing for pcmcia memory ca rd interface ............................................. 505 figure 13.52 wait timing for pc mcia memory card interface .............................................. 506 figure 13.53 pcmcia space allo cation ................................................................................... 507 figure 13.54 basic timing fo r pcmcia i/o card interface ..................................................... 508 figure 13.55 wait timing for pcmcia i/o card interface ...................................................... 509 figure 13.56 dynamic bus sizing timi ng for pcmcia i/o card interface ............................. 510 figure 13.57 example of 64-b it data width mpx connection ................................................. 512 figure 13.58 mpx interface timing 1 (singl e read cycle, anw = 0, no external wait, bus width: 64 bits) ............................................................................................... 513 figure 13.59 mpx interface timing 2 (singl e read, anw = 0, one exte rnal wait inserted, bus width: 64 bits) ............................................................................................... 514 figure 13.60 mpx interface timing 3 (single write cycle, anw = 0, no wait, bus width: 64 bits) ............................................................................................... 515 figure 13.61 mpx interface timing 4 (singl e write, anw = 1, one external wait inserted, bus width: 64 bits) ............................................................................................... 516 figure 13.62 mpx interface timing 5 (burst read cycle, anw = 0, no external wait, bus width: 64 bits, transfer data size: 32 bytes) .............................................. 517 figure 13.63 mpx interface timing 6 (burst read cycle, anw = 0, ex ternal wait control, bus width: 64 bits, transfer data size: 32 bytes) .............................................. 518 figure 13.64 mpx interface timing 7 (burst write cycle, anw = 0, no external wait, bus width: 64 bits, transfer data size: 32 bytes) .............................................. 519
page xxxiv of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 13.65 mpx interface timing 8 (burst write cycle, anw = 1, external wait control, bus width: 64 bits, transfer data size: 32 bytes) .............................................. 520 figure 13.66 mpx interface timing 9 (burst read cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 64 bits)................................................. 521 figure 13.67 mpx interface timing 10 (burst read cycle, anw = 0, one external wait inserted, bus width: 32 bits, transfer data size: 64 bits) ... 522 figure 13.68 mpx interface timing 11 (burst write cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 64 bits)................................................. 523 figure 13.69 mpx interface timing 12 (burst write cycle, anw = 1, one external wait inserted, bus width: 32 bits, transfer data size: 64 bits) ... 524 figure 13.70 mpx interface timing 13 (burst read cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 32 bytes) ............................................... 525 figure 13.71 mpx interface timing 14 (burst read cycle, anw = 0, external wait control, bus width: 32 bits, transfer data size: 32 bytes) .............................................. 526 figure 13.72 mpx interface timing 15 (bur st write cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 32 bytes) .............................................. 527 figure 13.73 mpx interface timing 16 (burst write cycle, anw = 1, external wait control, bus width: 32 bits, transfer data size: 32 bytes) .............................................. 528 figure 13.74 example of 64-bit data width byte control sram............................................ 530 figure 13.75 byte control sram basic read cycl e (no wa it) ............................................... 531 figure 13.76 byte control sram basic re ad cycle (one internal wait cycle) ...................... 532 figure 13.77 byte control sram basic read cycle (one internal wait + on e external wait).............................................................. 533 figure 13.78 waits be tween access cycles ............................................................................... 535 figure 13.79 ar bitration sequence............................................................................................ .538 section 14 direct memory access controller (dmac) figure 14.1 block diagram of dmac ....................................................................................... 548 figure 14.2 dmac tr ansfer flowchart ..................................................................................... 568 figure 14.3 round robin mode ................................................................................................. 574 figure 14.4 example of changes in priority order in r ound robin mode................................ 575 figure 14.5 data flow in single addr ess mode......................................................................... 577 figure 14.6 dma transfer ti ming in single ad dress m ode..................................................... 578 figure 14.7 operation in dual addr ess mode............................................................................ 579 figure 14.8 example of transfer timing in dual address mode .............................................. 580 figure 14.9 example of dma tr ansfer in cycle steal mode .................................................... 581 figure 14.10 example of dm a transfer in burst mode............................................................ 581 figure 14.11 bus handling with two dmac channels operating........................................... 585 figure 14.12 dual address mode/cycle steal mode external bus external bus/ dreq (level detection), da ck (read cycle)................................................................ 588
r01uh0456ej0702 rev. 7.02 page xxxv of lii sep 24, 2013 figure 14.13 dual address mode/cycle steal mode external bus external bus/ dreq (edge detection), dac k (read cycle)................................................................. 589 figure 14.14 dual address mode/burst mode external bus external bus/ dreq (level detection), da ck (read cycle)................................................................ 590 figure 14.15 dual address mode/burst mode external bus external bus/ dreq (edge detection), dac k (read cycle)................................................................. 591 figure 14.16 dual address mode/cycle steal mode on-chip sci (level detection) external bus .......................................................................................................... 592 figure 14.17 dual address mode/cycle steal mode external bus on-chip sci (level det ection)................................................................................................... 593 figure 14.18 single address mode/cycle steal mode external bus external bus/ dreq (level det ection)................................................................................................... 594 figure 14.19 single address mode/cycle steal mode external bus external bus/ dreq (edge detect ion).................................................................................................... 595 figure 14.20 single address mode/burst mode external bus external bus/ dreq (level det ection)................................................................................................... 596 figure 14.21 single address mode/burst mode external bus external bus/ dreq (edge detect ion).................................................................................................... 597 figure 14.22 single address mode/burst mode external bus external bus/ dreq (level detection)/32-byte block transfer (bus width: 64 bits, sd ram: row hit write) .................................................... 598 figure 14.23 on-demand tran sfer mode block diagram ......................................................... 603 figure 14.24 system configuration in on-demand data transfer mode .................................. 605 figure 14.25 data tran sfer request format............................................................................... 606 figure 14.26 single address mode: synchronous dram external device longword transfer sdram auto-precharge r ead bus cycle, burst (rcd[1:0] = 01, cas latency = 3, tpc[2:0] = 001).................................................. 609 figure 14.27 single address mode: external device synchronous dram longword transfer sdram auto-precharge write bus cycle, burst (rcd[1:0] = 01, trwl[2:0] = 101, tpc[2:0] = 001)............................................... 610 figure 14.28 dual address mode/synchronous dram sram longword transfer ........... 611 figure 14.29 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on -demand data transfer .......................................... 612 figure 14.30 single address mode/burst mode/external device external bus 32-byte block transfer/channel 0 on -demand data transfer .......................................... 613 figure 14.31 single address mode/burst mode/external bus external device 32-bit transfer/channel 0 on-dem and data tr ansfer..................................................... 614 figure 14.32 single address mode/burst mode/external device external bus 32-bit transfer/channel 0 on-dem and data tr ansfer..................................................... 615 figure 14.33 handshake protocol using data bus (channel 0 on-demand data transfer) .... 616
page xxxvi of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 14.34 handshake protocol without use of data bus (channel 0 on-demand da ta transfer)................................................................. 617 figure 14.35 read from synchr onous dram precharge bank ................................................. 618 figure 14.36 read from synchronous dr am non-precharge ba nk (row miss) ..................... 618 figure 14.37 read from sync hronous dram (r ow hit) .......................................................... 619 figure 14.38 write to synchr onous dram prec harge ba nk..................................................... 619 figure 14.39 write to synchronous dr am non-precharge bank (row miss)......................... 620 figure 14.40 write to sync hronous dram (row hit).............................................................. 620 figure 14.41 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on -demand data transfer .......................................... 621 figure 14.42 ddt mode setting ................................................................................................ 622 figure 14.43 single address mode/burst mode/edge detection/ external device external bus data transfer ................................................................................... 622 figure 14.44 single address mode/burst mode/level detection/ external bus external device da ta transfer .............................................................................. 623 figure 14.45 single address mode/burst mode/edge detection/byte, word, longword, quadword/external bus external device data transfer ............... 624 figure 14.46 single address mode/burst mode/edge detection/byte, word, longword, quadword/external device external bus data transfer ............... 625 figure 14.47 single address mode/burst mode/32-byte block transfer/dma transfer request to channels 1?3 using data bus ............................................................. 626 figure 14.48 single address mode/burst mode/32-byte block transfer/ external bus external device data transfer/ direct data transfer request to channel 2 without using da ta bus......................................................................................... 627 figure 14.49 single address mode/burst mode/external bus external device data transfer/direct data transfer request to ch annel 2 ............................................ 628 figure 14.50 single address mode/burst mode/external device external bus data transfer/direct data transfer request to ch annel 2 ............................................ 629 figure 14.51 single address mode/burst mode/external bus external device data transfer (active bank address)/direct da ta transfer request to channel 2....... 630 figure 14.52 single address mode/burst mode/external device external bus data transfer (active bank address)/direct da ta transfer request to channel 2....... 631 figure 14.53 block di agram of the dmac ............................................................................... 635 figure 14.54 dtr format (trans fer request format ) (SH7750r)............................................ 646 figure 14.55 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on -demand data transfer ......................................... 650 figure 14.56 single address mode/burst mode/external bus external device/32-byte block transfer/on-demand data transfer on channel 4 ..................................... 651
r01uh0456ej0702 rev. 7.02 page xxxvii of lii sep 24, 2013 section 15 serial commu nication interface (sci) figure 15.1 bloc k diagram of sci............................................................................................. 657 figure 15.2 md0/sck pin ...................................................................................................... ... 674 figure 15.3 md7/tx d pin...................................................................................................... .... 675 figure 15.4 rxd pin .......................................................................................................... ......... 675 figure 15.5 data format in asynchronous communication (example with 8-bit data, pa rity, two stop bits).................................................. 687 figure 15.6 relation between output clock and transfer data phase (asynchronous mode)............................................................................................. 689 figure 15.7 sample sci initialization fl owchart ....................................................................... 690 figure 15.8 sample serial transmission flowchart ................................................................... 691 figure 15.9 example of transmit operation in asynchronous mode (example with 8-bit data, parity, one st op bit) .................................................... 693 figure 15.10 sample serial reception flowch art (1)................................................................. 694 figure 15.10 sample serial reception flowch art (2)................................................................. 695 figure 15.11 example of sci receive oper ation (example with 8-bit data, parity, one stop bit) ......................................................................................................... 697 figure 15.12 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving st ation a)........................................... 699 figure 15.13 sample multiprocessor serial transmission flowchart ........................................ 700 figure 15.14 example of sci transmit operation (example with 8-bit data, multiprocessor bit, on e stop bi t) ......................................................................... 702 figure 15.15 sample multiprocessor serial reception fl owchart (1)........................................ 704 figure 15.15 sample multiprocessor serial reception fl owchart (2)........................................ 705 figure 15.16 example of sci receive operation (example with 8-bit data, multiprocessor bit, on e stop bi t) ......................................................................... 706 figure 15.17 data format in synchronous comm unication ...................................................... 707 figure 15.18 sample sci initialization fl owchart ..................................................................... 709 figure 15.19 sample serial transmission flowchart ................................................................. 710 figure 15.20 example of sci transmit op eration ..................................................................... 712 figure 15.21 sample serial reception flowch art (1)................................................................. 713 figure 15.21 sample serial reception flowch art (2)................................................................. 714 figure 15.22 example of sci receive op eration....................................................................... 715 figure 15.23 sample flowchart for seri al data transmission and reception ........................... 716 figure 15.24 receive data samplin g timing in asyn chronous mode ...................................... 720 figure 15.25 example of synchr onous transmission by dmac .............................................. 721 figure 15.26 example c ountermeasure on SH7750 ................................................................... 723 figure 15.27 clock inpu t timing of sck pin ............................................................................ 723
page xxxviii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 section 16 serial communicati on interface with fifo (scif) figure 16.1 bloc k diagram of scif........................................................................................... 7 27 figure 16.2 md8/ rts2 pin........................................................................................................ 753 figure 16.3 cts2 pin ................................................................................................................. 754 figure 16.4 md1/txd2 pin..................................................................................................... ... 755 figure 16.5 md2/rxd2 pin ..................................................................................................... .. 755 figure 16.6 sample scif initialization fl owchart ..................................................................... 761 figure 16.7 sample serial transmission flowchart ................................................................... 762 figure 16.8 example of transmit operation (example with 8-bit data, parity, one st op bit) .................................................... 764 figure 16.9 example of operation using modem control ( cts2 )............................................ 764 figure 16.10 sample serial reception flowch art (1)................................................................. 765 figure 16.10 sample serial reception flowch art (2)................................................................. 766 figure 16.11 example of scif receive operation (example with 8-bit data, parity, one st op bit) .................................................. 768 figure 16.12 example of operation using modem control ( rts2 ).......................................... 769 figure 16.13 receive data samplin g timing in asyn chronous mode ...................................... 772 figure 16.14 overrun error flag .............................................................................................. .. 774 section 17 smart card interface figure 17.1 block diagram of smart card interface.................................................................. 776 figure 17.2 schematic diagram of sm art card interface pin connections................................ 783 figure 17.3 smart card interface data format .......................................................................... 784 figure 17.4 tend generation ti ming....................................................................................... 786 figure 17.5 sample star t character wa veforms ........................................................................ 787 figure 17.6 difference in clock outp ut according to gm bit sett ing...................................... 790 figure 17.7 sample in itialization flow chart .............................................................................. 791 figure 17.8 sample transmi ssion processing flowchart ........................................................... 793 figure 17.9 sample recep tion processing flowchart ................................................................ 795 figure 17.10 receive data samplin g timing in smar t card mo de ........................................... 797 figure 17.11 retr ansfer operation in sci receive mode .......................................................... 799 figure 17.12 retransfer oper ation in sci tr ansmit mode ........................................................ 799 figure 17.13 procedure for stop ping and restarti ng the clock ................................................. 800 section 18 i/o ports figure 18.1 16-bit port...................................................................................................... ......... 804 figure 18.2 4-bit port....................................................................................................... .......... 805 figure 18.3 md0/sck pin ...................................................................................................... ... 806 figure 18.4 md7/tx d pin...................................................................................................... .... 807 figure 18.5 rxd pin.......................................................................................................... ......... 807
r01uh0456ej0702 rev. 7.02 page xxxix of lii sep 24, 2013 figure 18.6 md1/txd2 pin..................................................................................................... ... 808 figure 18.7 md2/rxd2 pin..................................................................................................... ... 808 figure 18.8 cts2 pin ................................................................................................................. 809 figure 18.9 md8/ rts2 pin........................................................................................................ 810 section 19 interrupt controller (intc) figure 19.1 bloc k diagram of intc.......................................................................................... 82 6 figure 19.2 example of irl interrupt co nnection ..................................................................... 829 figure 19.3 interrupt operation flowchart................................................................................. 844 section 20 user break controller (ubc) figure 20.1 block diagram of user break controller................................................................ 852 figure 20.2 user break debug support function flowchart ..................................................... 873 section 21 high-performan ce user debug interface (h-udi) figure 21.1 block diag ram of h-udi circuit............................................................................ 880 figure 21.2 tap control state transition diagram ................................................................... 891 figure 21.3 h-udi reset...................................................................................................... ...... 892 section 22 electrical characteristics figure 22.1 extal clock input timing ................................................................................... 940 figure 22.2 (1) ckio clock output timing .............................................................................. 940 figure 22.2 (2) ckio clock output timing .............................................................................. 940 figure 22.3 power-on oscillation settli ng time ....................................................................... 941 figure 22.4 standby return oscillation settling time (return by reset ) .............................. 941 figure 22.5 power-on oscillation settli ng time ....................................................................... 942 figure 22.6 standby return oscillation settling time (return by reset ) .............................. 942 figure 22.7 standby re turn oscillation settling ti me (return by nmi)................................... 943 figure 22.8 standby return oscillation settling time (return by irl3 to irl0 )..................... 943 figure 22.9 pll synchronization settling time in case of reset or nmi interrupt.............. 944 figure 22.10 pll synchronization settling time in case of irl interrupt............................... 944 figure 22.11 manual reset input timing................................................................................... 945 figure 22.12 m ode input timing ............................................................................................... 945 figure 22.13 c ontrol signal timing........................................................................................... 948 figure 22.14 (1) pin drive timi ng for reset or sleep mo de ..................................................... 948 figure 22.14 (2) pin drive timi ng for software standby m ode................................................ 949 figure 22.15 sram bus cycle: basic bus cycle (no wait)..................................................... 956 figure 22.16 sram bus cycle: basi c bus cycle (one in ternal wait)...................................... 957 figure 22.17 sram bus cycle: basic bus cycle (one internal wait + one external wait).... 958
page xl of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 22.18 sram bus cycle: basi c bus cycle (no wait, address setup/ hold time insertion, ans = 1, anh = 1) .............................................................. 959 figure 22.19 burst ro m bus cycle (n o wait) ......................................................................... 960 figure 22.20 burst rom bus cycle (1st data: one internal wait + one external wait; 2nd/3rd/4th data: one internal wait).................................................................... 961 figure 22.21 burst rom bus cycle (no wait, address setup/hold time insertion, ans = 1, an h = 1) ................................................................................................ 962 figure 22.22 burst rom bus cycle (one internal wait + one ex ternal wait) ........................ 963 figure 22.23 synchronous dram auto-precharge read bus cycle: single (rcd[1:0] = 01, cas latency = 3, tpc[2:0] = 011) ........................................... 964 figure 22.24 synchronous dram auto-precharge read bus cycle: burst (rcd[1:0] = 01, cas latency = 3, tp c[2:0] = 011)....................................................................... 965 figure 22.25 synchronous dram normal read bus cycle: act + read commands, burst (rasd = 1, rcd[1:0] = 01, cas latenc y = 3) .......................................... 966 figure 22.26 synchronous dram normal read bus cycle: pre + act + read commands, burst ((rasd = 1, rcd[1:0] = 01, tpc[2:0] = 001, cas latency = 3).............. 967 figure 22.27 synchronous dram normal read bus cycle: read command, burst ((rasd = 1, cas latency = 3) ............................................................................ 968 figure 22.28 synchronous dram auto-precharge write bus cycle: single (rcd[1:0] = 01, tpc[2:0] = 001, trwl[2:0] = 010).......................................... 969 figure 22.29 synchronous dram auto-precharge write bus cycle: burst (rcd[1:0] = 01, tpc[2:0] = 001, trwl[2:0] = 010).......................................... 970 figure 22.30 synchronous dram normal write bus cycle: act + write commands, burst (rasd = 1, rcd[1:0] = 01, trwl[2:0] = 010)......................................... 971 figure 22.31 synchronous dram normal write bus cycle: pre + act + write commands, burst (rasd = 1, rcd[1:0] = 01, tpc[2:0] = 001, trwl[2:0] = 010).............. 972 figure 22.32 synchronous dram normal write bus cycle: write command, burst (rasd = 1, tr wl[2:0] = 010)................................................................... 973 figure 22.33 synchronous dram bus cycle: synchronous dram precharge command (rasd = 1, tpc[2:0] = 001) ................................................................................ 974 figure 22.34 synchronous dram bus cycle: synchronous dram auto-refresh (tras = 1, trc[2: 0] = 00 1) ................................................................................ 975 figure 22.35 synchronous dram bus cycle: synchronous dram self-refresh (trc[2:0] = 001)................................................................................................... 976 figure 22.36 (a) synchronous dram bus cycle: synchronous dram mode register setting (pall)............................................................................................................. 977 figure 22.36 (b) synchronous dram bus cycle: synchronous dram mode register setting (set)................................................................................................................ 978 figure 22.37 dram bus cycles (1) rcd[1:0] = 00, anw[2:0] = 000, tpc[2:0] = 001 (2) rcd[1:0] = 01, anw[2:0] = 001, tpc[2: 0] = 010.......................................... 979
r01uh0456ej0702 rev. 7.02 page xli of lii sep 24, 2013 figure 22.38 dram bus cycle (edo mode, rcd[1:0] = 00, anw[2:0] = 000, tpc[2:0] = 001) .................................................................................................... 980 figure 22.39 dram burst bus cycle (edo mode, rcd[1:0] = 00, anw[2:0] = 000, tpc[2:0] = 001) .................................................................................................... 981 figure 22.40 dram burst bus cycle (edo mode, rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 001) ........................ 982 figure 22.41 dram burst bus cycle (edo mode, rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 001, 2-cycle ca s negate pulse width)............................................. 983 figure 22.42 dram burst bus cycle: ras down mode state (edo mode, rcd[1:0] = 00 , anw[2:0] = 000) ................................................... 984 figure 22.43 dram burst bus cycle: ras down mode continuation (edo mode, rcd[1:0] = 00 , anw[2:0] = 000) ................................................... 985 figure 22.44 dram burst bus cycle (fast page mode, rcd[1:0] = 00, anw[2:0] = 000, tpc[2:0] = 001) .................................................................................................... 986 figure 22.45 dram burst bus cycle (fast page mode, rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 001) .................................................................................................... 987 figure 22.46 dram burst bus cycle (fast page mode, rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 001, 2-cycle ca s negate pulse width)............................................. 988 figure 22.47 dram burst bus cycle: ras down mode state (fast page mode, rcd[1:0] = 00, anw[2:0] = 000) ............................................ 989 figure 22.48 dram burst bus cycle: ras down mode continuation (fast page mode, rcd[1:0] = 00, anw[2:0] = 000) ............................................ 990 figure 22.49 dram bus cycle: dram cas-before-ras refresh (tras[2:0] = 000, t rc[2:0] = 001)..................................................................... 991 figure 22.50 dram bus cycle: dram cas-before-ras refresh (tras[2:0] = 001, t rc[2:0] = 001)..................................................................... 992 figure 22.51 dram bus cycle: dram self-refresh (trc[ 2:0] = 001) ................................. 993 figure 22.52 pcmcia memory bus cycle (1) ted[2:0] = 000, teh[2:0] = 000, no wait (2) ted[2:0] = 001, teh[2:0] = 001, one internal wait + on e external wait ................................................................ 994 figure 22.53 pcmcia i/o bus cycle (1) ted[2:0] = 000, teh[2:0] = 000, no wait (2) ted[2:0] = 001, teh[2:0] = 001, one internal wait + on e external wait ................................................................ 995 figure 22.54 pcmcia i/o bus cycle (ted[2:0] = 001, teh[2:0] = 001, one internal wait, bus sizing).............................................................................. 996 figure 22.55 mpx basic bus cycle: r ead (1) 1st data (one internal wait) (2) 1st data (one internal wa it + one external wait) .......................................... 997 figure 22.56 mpx basic bus cycl e: write (1) 1st data (no wait) (2) 1st data (one internal wait) (3) 1st data (one internal wa it + one external wait) .......................................... 998
page xlii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 22.57 mpx bus cycle: burst read (1) 1st data (one internal wait), 2nd to 8th data (one internal wait) (2) 1st data (one internal wait), 2nd to 4th data (one internal wait + one extern al wait) .................................... 999 figure 22.58 mpx bus cycle: burst write (1) no internal wait (2) 1st data (one internal wait), 2nd to 4th data (no internal wa it + external wait control) .............................. 1000 figure 22.59 memory byte control sram bus cycles (1) basic read cycle (no wait) (2) basic read cycle (one intern al wait) (3) basic read cycle (one internal wait + on e external wait)............................................................ 1001 figure 22.60 memory byte control sram bus cycle: basic read cycle (no wait, address setup/hold time insert ion, ans[0] = 1, anh[1:0] =0 1)..... 1002 figure 22.61 tclk input timing ............................................................................................ 101 1 figure 22.62 rtc oscillation settling time at power-on....................................................... 1011 figure 22.63 sck i nput clock ti ming .................................................................................... 1011 figure 22.64 sci i/o synchr onous mode cloc k timing ......................................................... 1012 figure 22.65 i/o port input/output timing .............................................................................. 1012 figure 22.66 (a) dreq /drak timi ng ................................................................................... 1012 figure 22.66 (b) dbreq / tr input timing and bavl output ti ming .................................. 1013 figure 22.67 tc k input timing............................................................................................... 1 013 figure 22.68 reset hold timing........................................................................................... 1014 figure 22.69 h-udi da ta transfer timing .............................................................................. 1014 figure 22.70 pin break timing ................................................................................................ 1014 figure 22.71 nm i input timing............................................................................................... 1 014 figure 22.72 out put load circuit ............................................................................................ 1 015 figure 22.73 load cap acitance vs. de lay time ....................................................................... 1016 appendix b package dimensions figure b.1 package dimensions (256-pin bga: devices other than hd6417750rba240hv and hd6417750sb a200v) ................................................................................... 1023 figure b.2 package dime nsions (208-p in qfp) ...................................................................... 1024 figure b.3 package dime nsions (264-pin csp)....................................................................... 1025 figure b.4 package dime nsions (292-p in bga) ..................................................................... 1026 figure b.5 package dimensions (256-pin bga: hd6417750rba240hv and hd6417750sba 200v) .......................................................................................... 1027 appendix d ckio2enb pin configuration figure d.1 ckio2enb pin configur ation ............................................................................... 1033 appendix g prefetching of instructions and its side effects figure g.1 inst ruction prefetch .............................................................................................. .. 1061
r01uh0456ej0702 rev. 7.02 page xliii of lii sep 24, 2013 appendix h power-on and power-off procedures figure h.1 power-on procedure 1 ........................................................................................... 106 4 figure h.2 power-on procedure 2 ........................................................................................... 106 5
page xliv of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013
r01uh0456ej0702 rev. 7.02 page xlv of lii sep 24, 2013 tables section 1 overview table 1.1 lsi features ................................................................................................................ 1 table 1.2 pin functions............................................................................................................. 14 table 1.3 pin functions............................................................................................................. 24 table 1.4 pin functions............................................................................................................. 32 table 1.5 pin functions............................................................................................................. 42 section 2 programming model table 2.1 initial regist er values............................................................................................... 55 section 3 memory ma nagement unit (mmu) table 3.1 mmu regist ers......................................................................................................... 74 section 4 caches table 4.1 cache features (sh7 750, SH7750 s) ...................................................................... 111 table 4.2 cache features (SH7750r) ..................................................................................... 112 table 4.3 features of st ore queues......................................................................................... 112 table 4.4 cache control re gisters.......................................................................................... 113 section 5 exceptions table 5.1 exception-related registers ................................................................................... 149 table 5.2 exceptions ............................................................................................................... 152 table 5.3 types of re set......................................................................................................... 161 section 6 floating-point unit (fpu) table 6.1 floating-point number fo rmats and parameters .................................................... 186 table 6.2 floating-point ranges ............................................................................................. 187 table 6.3 incorrect opera tion result ...................................................................................... 203 table 6.4 fdiv drm, drn (drn/drm drn) ................................................................. 204 table 6.5 fadd drm, drn (drn + drm drn) fsub drm, drn (drn ? drm drn) ............................................................................................ 205 table 6.6 fmul drm, drn (drn*drm drn) .............................................................. 205 table 6.7 trap routine processing....................................................................................... 207 section 7 instruction set table 7.1 addressing modes and ef fective addr esses ........................................................... 211 table 7.2 notation used in in struction list ............................................................................ 215
page xlvi of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 7.3 fixed-point transfer instruct ions............................................................................ 216 table 7.4 arithmetic operation instructions........................................................................... 218 table 7.5 logic operation in structions................................................................................... 220 table 7.6 shift instru ctions ..................................................................................................... 221 table 7.7 branch instructions ................................................................................................. 222 table 7.8 system control in structions .................................................................................... 223 table 7.9 floating-point single-preci sion instructions........................................................... 225 table 7.10 floating-point double-preci sion instru ctions ......................................................... 226 table 7.11 floating-point contro l instructions......................................................................... 226 table 7.12 floating-point graphics acce leration instru ctions ................................................. 227 section 8 pipelining table 8.1 instruction groups................................................................................................... 238 table 8.2 parallel-exec utability .............................................................................................. 242 table 8.3 execution cy cles..................................................................................................... 249 section 9 power-down modes table 9.1 status of cpu and peripheral mo dules in power-do wn modes............................. 260 table 9.2 power-down mode registers ................................................................................. 261 table 9.3 power-down m ode pins ......................................................................................... 261 table 9.4 state of registers in standby mode ........................................................................ 270 section 10 clock oscillation circuits table 10.1 cpg pins ................................................................................................................. 292 table 10.2 cpg regist er........................................................................................................... 292 table 10.3 (1) clock operating modes (s h7750, sh775 0s) .................................................. 293 table 10.3 (2) clock operating mode s (SH7750r)................................................................. 293 table 10.4 frqcr settings and internal clock freque ncies ................................................... 294 table 10.5 wdt regist ers........................................................................................................ 301 section 11 realtime clock (rtc) table 11.1 rtc pins ................................................................................................................. 313 table 11.2 rtc regist ers ......................................................................................................... 313 table 11.3 crystal oscillator circuit consta nts (recommended values) ................................ 333 section 12 timer unit (tmu) table 12.1 tmu pins................................................................................................................ 338 table 12.2 tmu regist ers ........................................................................................................ 339 table 12.3 tmu interrupt sources ........................................................................................... 355
r01uh0456ej0702 rev. 7.02 page xlvii of lii sep 24, 2013 section 13 bus state controller (bsc) table 13.1 bsc pins ................................................................................................................. 360 table 13.2 bsc regist ers ......................................................................................................... 364 table 13.3 external memory space map.................................................................................. 366 table 13.4 pcmcia interface features.................................................................................... 368 table 13.5 pcmcia support interfaces ................................................................................... 369 table 13.6 mpx interface is selected (areas 0 to 6)................................................................ 398 table 13.7 (1) 64-bit external device/big-endian access and data alignment ...................... 423 table 13.7 (2) 64-bit external device/big-endian access and data alignment ...................... 424 table 13.8 32-bit external device/big-endian access and data alignment ........................... 425 table 13.9 16-bit external device/big-endian access and data alignment ........................... 426 table 13.10 8-bit external device/big-endian access and data alignment............................. 427 table 13.11 (1) 64-bit external device/little-endian access and data alignment.................. 428 table 13.11 (2) 64-bit external device/little-endian access and data alignment.................. 429 table 13.12 32-bit external device/little-endian access and data alignment ........................ 430 table 13.13 16-bit external device/little-endian access and data alignment ........................ 431 table 13.14 8-bit external device/little-endian access and data alignment .......................... 432 table 13.15 relationship between amxext and amx2?0 bits and address multiplexing.... 451 table 13.16 example of correspondence between this lsi and synchronous dram address pins (64-bit bus width, amx2?a mx0 = 011, amxext = 0) ............................ 468 table 13.17 cycles for which pipeline access is possible ......................................................... 484 table 13.18 relationship between address and ce when using pcmcia interface ................ 502 section 14 direct memory access controller (dmac) table 14.1 dmac pins............................................................................................................. 549 table 14.2 dmac pins in ddt mode ..................................................................................... 550 table 14.3 dmac regist ers..................................................................................................... 550 table 14.4 selecting external request mode with rs bits ...................................................... 570 table 14.5 selecting on-chip peripheral module request mode wi th rs b its ....................... 572 table 14.6 supported dma transfers ...................................................................................... 576 table 14.7 relationship between dma transfer t ype, request mode, and bus mode .......... 582 table 14.8 external request transfer sources and destinations in normal dma mode ........ 583 table 14.9 external request transfer sources and destinations in ddt mode ...................... 584 table 14.10 conditions for transfer between external memory and an external device with dack, and corresponding register se ttings ......................................................... 602 table 14.11 dmac pins............................................................................................................. 636 table 14.12 dmac pins in ddt mode ..................................................................................... 637 table 14.13 register config uration ............................................................................................ 638 table 14.14 channel selection by dtr fo rmat (dmaor.dbl = 1)........................................ 646 table 14.15 notification of transfer channel in eight-channe l ddt mode............................. 648
page xlviii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 14.16 function of bavl .................................................................................................. 648 table 14.17 dtr format for clearin g request queues ............................................................. 649 table 14.18 dmac interrupt-re quest codes............................................................................. 650 section 15 serial commu nication interface (sci) table 15.1 sci pins .................................................................................................................. 658 table 15.2 sci registers........................................................................................................... 659 table 15.3 examples of bit rates and scbrr1 se ttings in asynchronous mode .................. 677 table 15.4 examples of bit rates and scbrr1 settings in synchr onous mode..................... 681 table 15.5 maximum bit rate for various frequencies with baud rate generator (asynchronous mode)............................................................................................. 682 table 15.6 maximum bit rate with external cl ock input (asynchronous mode)................... 683 table 15.7 maximum bit rate with external cl ock input (synchronous mode)..................... 683 table 15.8 scsmr1 settings for serial tran sfer format se lection ......................................... 685 table 15.9 scsmr1 and scscr1 settings for sci clock source selection .......................... 686 table 15.10 serial transfer formats (asynchronous mode) ...................................................... 688 table 15.11 receive error conditions........................................................................................ 696 table 15.12 sci interrupt sources.............................................................................................. 718 table 15.13 scssr1 status flags and tran sfer of recei ve data............................................... 719 table 15.14 peripheral module si gnal timing ........................................................................... 724 section 16 serial communicati on interface with fifo (scif) table 16.1 scif pins ................................................................................................................ 728 table 16.2 scif regist ers ........................................................................................................ 729 table 16.3 scsmr2 settings for serial tran sfer format se lection ......................................... 758 table 16.4 scscr2 settings for scif cl ock source sel ection ............................................... 758 table 16.5 serial transmit/recei ve formats ............................................................................ 759 table 16.6 scif interrup t sources............................................................................................ 770 section 17 smart card interface table 17.1 smart card inte rface pins ....................................................................................... 777 table 17.2 smart card interf ace register s ............................................................................... 777 table 17.3 smart card interface re gister se ttings ................................................................... 785 table 17.4 values of n and corresponding cks1 and cks0 settings ..................................... 788 table 17.5 examples of bit rate b (bits/s) for va rious scbrr1 settings (when n = 0)........ 788 table 17.6 examples of scbrr1 settings for bit rate b (bits/s) (when n = 0) ..................... 788 table 17.7 maximum bit rate at various frequenc ies (smart card interface mode) ............. 789 table 17.8 register settings and sck pin state....................................................................... 789 table 17.9 smart card mode operating stat es and interrupt sources...................................... 796
r01uh0456ej0702 rev. 7.02 page xlix of lii sep 24, 2013 section 18 i/o ports table 18.1 20-bit general-purpose i/o port pins ..................................................................... 811 table 18.2 sci i/o port pins..................................................................................................... 812 table 18.3 scif i/o port pins .................................................................................................. 812 table 18.4 i/o port regi sters .................................................................................................... 813 section 19 interrupt controller (intc) table 19.1 intc pins ............................................................................................................... 827 table 19.2 intc regist ers........................................................................................................ 827 table 19.3 irl3 ? irl0 pins and interr upt leve ls..................................................................... 830 table 19.4 SH7750 irl3 ? irl0 pins and interrupt leve ls (when irlm = 1)......................... 831 table 19.5 interrupt exception handling sour ces and priority order ...................................... 833 table 19.6 interrupt request sources an d ipra?iprd re gisters............................................ 836 table 19.7 interrupt request sources and the b its of the intpri 00 register ......................... 839 table 19.8 bit assignme nts ...................................................................................................... 842 table 19.9 interrupt respon se time ......................................................................................... 846 section 20 user break controller (ubc) table 20.1 ubc regist ers......................................................................................................... 853 section 21 high-performan ce user debug interface (h-udi) table 21.1 h-udi pins.............................................................................................................. 881 table 21.2 h-udi regist ers...................................................................................................... 882 table 21.3 configuration of the bound ary scan re gister......................................................... 888 section 22 electrical characteristics table 22.1 absolute maximum ratings.................................................................................... 895 table 22.2 dc characteristics (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba 240hv)........................................................................................ 896 table 22.3 dc characteristics (hd6 417750rf240 (v)) .......................................................... 898 table 22.4 dc characteristics (hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba240hv* 3 )..................................................................................... 900 table 22.5 dc characteristics (hd6 417750rf200 (v)) .......................................................... 902 table 22.6 dc characteristics (hd6 417750sbp200 (v), hd 6417750sba200v).................. 904 table 22.7 dc characteristics (hd6 417750sf200 (v)) .......................................................... 906 table 22.8 dc characteristics (hd6 417750bp200m (v)) ...................................................... 908 table 22.9 dc characteristics (hd6 417750sf167 (v)) .......................................................... 910 table 22.10 dc characteristics (hd6 417750f167 (v))............................................................. 912 table 22.11 dc characteristics (hd6 417750svf133 (v))........................................................ 914 table 22.12 dc characteristics (hd6 417750svbt133 (v))..................................................... 916
page l of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.13 dc characteristics (hd6 417750vf128 (v)).......................................................... 918 table 22.14 permissible output currents ................................................................................... 919 table 22.15 clock timing (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba 240hv)........................................................................................ 920 table 22.16 clock timing (hd6417 750rf240 (v)).................................................................. 920 table 22.17 clock timing (hd6417750bp200m (v), hd6417750sbp200 (v), hd6417750sba200v*, hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba 240hv*)...................................................................................... 920 table 22.18 clock timing (hd6417 750rf200 (v)).................................................................. 920 table 22.19 clock timing (hd6417 750sf200 (v)) .................................................................. 921 table 22.20 clock timing (hd6417750f167 (v ), hd6417750sf167 (v)) .............................. 921 table 22.21 clock timing (hd6417750svf133 (v ), hd6417750svbt133 (v)) ................... 921 table 22.22 clock timing (hd6417 750vf128 (v )).................................................................. 921 table 22.23 clock and control signal timing (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba 240hv).............................................. 922 table 22.24 clock and control signal timi ng (hd6417750rf240 (v))................................... 924 table 22.25 clock and control signal timing (hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba240hv* 2 )........................................... 926 table 22.26 clock and control signal timi ng (hd6417750rf200 (v))................................... 928 table 22.27 clock and control signal timing (hd6417750bp200m (v), hd6417750sbp200 (v), hd6417750sba 200v).................................................. 930 table 22.28 clock and control signal timi ng (hd6417750sf2 00 (v)) ................................... 932 table 22.29 clock and control signal timing (hd6417750f167 (v), hd6417750sf167 (v))........................................................................................... 934 table 22.30 clock and control signal timing (hd6417750svf133 (v), hd6417750svbt133 (v)) ..................................................................................... 936 table 22.31 clock and control signal timi ng (hd6417750vf1 28 (v))................................... 938 table 22.32 control signal timing............................................................................................. 946 table 22.33 control signal timing............................................................................................. 947 table 22.34 bus timing (1) ........................................................................................................ 950 table 22.35 bus timing (2) ........................................................................................................ 952 table 22.36 bus timing (3) ........................................................................................................ 954 table 22.37 peripheral module sign al timing (1) ................................................................... 1003 table 22.38 peripheral module sign al timing (2) ................................................................... 1005 table 22.39 peripheral module sign al timing (3) ................................................................... 1007 table 22.40 peripheral module sign al timing (4) ................................................................... 1008 table 22.41 peripheral module sign al timing (5) ................................................................... 1010 appendix a address list table a.1 address li st .......................................................................................................... 1017
r01uh0456ej0702 rev. 7.02 page li of lii sep 24, 2013 appendix e pin functions table e.1 pin states in reset, power-down st ate, and bus-rel eased state ......................... 1035 appendix i product lineup table i.1 SH7750/SH7750s/SH7750r product li neup ....................................................... 1067 appendix j version registers table j.1 register config uration .......................................................................................... 1069
page lii of lii r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 1 of 1076 sep 24, 2013 section 1 overview 1.1 SH7750, SH7750s, SH7750r groups features this lsi (SH7750, SH7750s, and SH7750r groups) is a 32-bit risc (reduced instruction set computer) microprocessor with a sh-4 cpu core and features up ward compatibility with sh-1, sh-2, and sh-3 microcomputers at the instruction set level. it in cludes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an mmu (memory management unit) with a 64-entry fully-associative unified tlb (translation lookaside buffer). the SH7750 and SH7750s have an 8-kbyte instruction cache and a 16-kbyte data cache. the SH7750r has a 16-kbyte instruction cache and a 32-kbyte data cache. this lsi has an on-chip bus state controller (bsc) that allows connection to dram and synchronous dram. its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50 % compared with 32-bit instructions. the features of this lsi are summarized in table 1.1. table 1.1 lsi features item features lsi ? superscalar architecture: parallel execution of two instructions ? external buses ? separate 26-bit address and 64-bit data buses ? external bus frequency of 1/2, 1/3, 1/ 4, 1/6, or 1/8 times internal bus frequency
section 1 overview SH7750, SH7750s, SH7750r group page 2 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 item features cpu ? renesas original superh architecture ? 32-bit internal data bus ? general register file: ? sixteen 32-bit general registers (and eight 32-bit shadow registers) ? seven 32-bit control registers ? four 32-bit system registers ? risc-type instruction set (upward-compatible with sh-1, sh-2, and sh-3) ? fixed 16-bit instruction length for improved code efficiency ? load-store architecture ? delayed branch instructions ? conditional execution ? c-based instruction set ? superscalar architecture (providing simultaneous execution of two instructions) including fpu ? instruction execution time: maximum 2 instructions/cycle ? virtual address space: 4 gbytes ( 448-mbyte external memory space) ? space identifier asids: 8 bits , 256 virtual address spaces ? on-chip multiplier ? five-stage pipeline
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 3 of 1076 sep 24, 2013 item features fpu ? on-chip floating-point coprocessor ? supports single-precision (32 bits) and double-precision (64 bits) ? supports ieee754-compliant data types and exceptions ? two rounding modes: round to nearest and round to zero ? handling of denormalized numbers: truncation to zero or interrupt generation for compliance with ieee754 ? floating-point registers: 32 bits 16 2 banks (single-precision 32 bits 16 or double-precision 64 bits 8) 2 banks ? 32-bit cpu-fpu floating-point communication register (fpul) ? supports fmac (multiply- and-accumulate) instruction ? supports fdiv (divide) and fsqrt (square root) instructions ? supports fldi0/fldi1 (load c onstant 0/1) instructions ? instruction execution times ? latency (fmac/fadd/fsub/fmul): 3 cycles (single-precision), 8 cycles (double-precision) ? pitch (fmac/fadd/fsub/fmul): 1 cycl e (single-precision), 6 cycles (double-precision) note: fmac is supported for single-precision only. ? 3-d graphics instructions (single-precision only): ? 4-dimensional vector conversion and matrix operations (ftrv): 4 cycles (pitch), 7 cycles (latency) ? 4-dimensional vector inner product (fipr): 1 cycle (pitch), 4 cycles (latency)
section 1 overview SH7750, SH7750s, SH7750r group page 4 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 item features clock pulse generator (cpg) ? choice of main clock: ? SH7750, SH7750s: 1/2, 1, 3, or 6 times extal ? SH7750r: 1, 6, or 12 times extal ? clock modes: ? cpu frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ? bus frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ? peripheral frequency: 1/2, 1/3, 1/ 4, 1/6, or 1/8 times main clock note: maximum frequency varies with models. ? power-down modes ? sleep mode ? standby mode ? module standby function ? single-channel watchdog timer memory management unit (mmu) ? 4-gbyte address space, 256 address s pace identifiers (8-bit asids) ? single virtual mode and multiple virtual memory mode ? supports multiple page sizes: 1 kb yte, 4 kbytes, 64 kbytes, 1 mbyte ? 4-entry fully-associative tlb for instructions ? 64-entry fully-associative tlb for instructions and operands ? supports software-controlled replacement and random-counter replacement algorithm ? tlb contents can be accessed directly by address mapping
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 5 of 1076 sep 24, 2013 item features cache memory [SH7750, SH7750s] ? instruction cache (ic) ? 8 kbytes, direct mapping ? 256 entries, 32-byte block length ? normal mode (8-kbyte cache) ? index mode ? operand cache (oc) ? 16 kbytes, direct mapping ? 512 entries, 32-byte block length ? normal mode (16-kbyte cache) ? index mode ? ram mode (8-kbyte cache + 8-kbyte ram) ? choice of write method (copy -back or write-through) ? single-stage copy-back buffer, single-stage write-through buffer ? cache memory contents can be accessed directly by address mapping (usable as on-chip memory) ? store queue (32 bytes 2 entries) cache memory [SH7750r] ? instruction cache (ic) ? 16 kbytes, 2-way set associative ? 256 entries/way, 32-byte block length ? cache-double-mode (16-kbyte cache) ? index mode ? SH7750/SH7750s-compatible mode (8 kbytes, direct mapping) ? operand cache (oc) ? 32 kbytes, 2-way set associative ? 512 entries/way, 32-byte block length ? cache-double-mode (32-kbyte cache) ? index mode ? ram mode (16-kbyte cache + 16-kbyte ram) ? SH7750/SH7750s-compatible mode (16 kbytes, direct mapping) ? single-stage copy-back buffer, single-stage write-through buffer ? cache memory contents can be accessed directly by address mapping (usable as on-chip memory) ? store queue (32 bytes 2 entries)
section 1 overview SH7750, SH7750s, SH7750r group page 6 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 item features interrupt controller (intc) ? five independent external interrupts: nmi, irl3 to irl0 ? 15-level encoded external interrupts: irl3 to irl0 ? on-chip peripheral module interrupts: priority level can be set for each module user break controller (ubc) ? supports debugging by means of user break interrupts ? two break channels ? address, data value, access type, and data size can all be set as break conditions ? supports sequential break function bus state controller (bsc) ? supports external memory access ? 64/32/16/8-bit external data bus ? external memory space divided into seven areas, each of up to 64 mbytes, with the following parameters settable for each area: ? bus size (8, 16, 32, or 64 bits) ? number of wait cycles (hardware wait function also supported) ? connection of dram, synchronous dram, and burst rom possible by setting space type ? supports fast page mode and dram edo ? supports pcmcia interface ? chip select signals ( cs0 to cs6 ) output for relevant areas ? dram/synchronous dram refresh functions ? programmable refresh interval ? supports cas-before-ras refresh mode and self-refresh mode ? dram/synchronous dram burst access function ? big endian or little endian mode can be set
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 7 of 1076 sep 24, 2013 item features direct memory access controller (dmac) ? physical address dma controller: ? SH7750, SH7750s: 4-channel ? SH7750r: 8-channel ? transfer data size: 8, 16, 32, or 64 bits, or 32 bytes ? address modes: ? single address mode ? dual address mode ? transfer requests: external, on-chip module, or auto-requests ? bus modes: cycle-steal or burst mode ? supports on-demand data transfer timer unit (tmu) ? auto-reload 32-bit timer: ? SH7750, SH7750s: 3-channel ? SH7750r: 5-channel ? input capture function ? choice of seven counter input clocks realtime clock (rtc) ? on-chip clock and calendar functions ? built-in 32 khz crystal oscillator with maximum 1/256 second resolution (cycle interrupts) serial communication interface (sci, scif) ? two full-duplex communication channels (sci, scif) ? channel 1 (sci): ? choice of asynchronous mode or synchronous mode ? supports smart card interface ? channel 2 (scif): ? supports asynchronous mode ? separate 16-byte fifos provided for transmitter and receiver
section 1 overview SH7750, SH7750s, SH7750r group page 8 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 item features product lineup abbre- viation voltage (internal) operating frequency model no. package SH7750 1.95 v 200 mhz hd6417750bp200m 256-pin bga 1.8 v 167 mhz hd6417750f167 1.5 v 128 mhz hd6417750vf128 208-pin qfp SH7750s 1.95 v 200 mhz hd6417750sbp200 256-pin bga hd6417750sba200 hd6417750sf200 1.8 v 167 mhz hd6417750sf167 1.5 v 133 mhz hd6417750svf133 208-pin qfp hd6417750svbt133 264-pin csp SH7750r 1.5 v 240 mhz hd6417750rbg240 292-pin bga hd6417750rbp240 256-pin bga hd6417750rba240h hd6417750rf240 208-pin qfp 200 mhz hd6417750rbg200 292-pin bga hd6417750rbp200 256-pin bga hd6417750rf200 208-pin qfp
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 9 of 1076 sep 24, 2013 1.2 block diagram figure 1.1 shows an internal block diagram of this lsi. cpg intc sci (scif) rtc tmu external bus interface bsc dmac address 29-bit address 64-bit data 64-bit data 32-bit data 32-bit data upper 32-bit data 32-bit address (instructions) 32-bit data (instructions) 32-bit address (data) peripheral address bus 26-bit address 64-bit data 16-bit peripheral data bus ubc lower 32-bit data lower 32-bit data 32-bit data (load) 32-bit data (store) cpu i cache o cache itlb utlb cache and tlb controller fpu sh-4 core 64-bit data (store) legend: bsc: bus state controller cpg: clock pulse generator dmac: direct memory access controller fpu: floating-point unit intc: interrupt controller itlb: instruction tlb (translation lookaside buffer) utlb: unified tlb (translation lookaside buffer) rtc: realtime clock sci: serial communication interface scif: serial communication interface with fifo tmu: timer unit ubc: user break controller figure 1.1 block diagram of SH7750/SH7750s/SH7750r group functions
section 1 overview SH7750, SH7750s, SH7750r group page 10 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1.3 pin arrangement nmi irl3 irl2 irl1 irl0 md1/txd2 md0/sck d50 d51 d52 d53 d63 d62 d61 d57 d56 d31 d30 d29 d28 d27 d26 d25 d54 d55 d16 d17 d18 d19 d20 d21 d48 d49 d60 d59 d58 rdy reset cs0 cs1 cs6 bs extal ckio2enb xtal vss-cpg vdd-cpg(3.3v) vdd-pll1(3.3v) vdd-pll2(3.3v) tdi tck tms tdo asebrk /brkack md6/ iois16 status1 status0 dack1 dack0 md5/ ras2 md4/ ce2b md3/ ce2a a25 a24 a23 a22 a21 a20 a19 a18 md7/txd sck2/ mreset md8/ rts2 tclk vdd-rtc(3.3v) vss-rtc extal2 xtal2 d8 d7 cke we5 / cas5 /dqm5 we4 / cas4 /dqm4 we1 / cas1 /dqm1 we0 / cas0 /dqm0 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 ckio ckio2 a6 a5 a4 a3 a2 cs3 cs2 ras rd / cass / frame rd/ wr we2 / cas2 /dqm2/ iciord we3 / cas3 /dqm3/ iciowr we6 / cas6 /dqm6 we7 / cas7 /dqm7/ reg d23 d24 d22 a b c d e f g h 1234567891011121314151617 1920 18 j k l m n p r t u v w y d47 d46 d45 d44 d43 d42 d32 d33 d34 d35 d36 d37 cs4 trst cts2 drak0 drak1 vss-pll1 vss-pll2 a1 a0 cs5 rd2 rd/ wr2 bga256 (top view) md2/rxd2 dreq1 dreq0 rxd back / bsreq d41 d40 d15 d14 d13 d12 d11 d10 d9 d38 d39 d0 d1 d2 d3 d4 d5 d6 breq / bsack vddq (io) vssq (io) vdd (internal) vss (internal) nc ca * notes: power must be supplied to the on-chip pll power supply pins (vdd-pll1, vdd-pll2, vss-pll1, vss-pll2, vdd-cpg, vss-cpg, vdd-rtc, and vss-rtc) regardless of whether or not the pll circuits, crystal oscillation circuit, and rtc are used. * hardware standby request (SH7750s and SH7750r). in the SH7750, pull up to 3.3 v. figure 1.2 pin arrangement (256-pin bga)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 11 of 1076 sep 24, 2013 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 rdy reset cs0 cs1 cs4 cs5 cs6 bs d47 d32 d46 d33 d45 d34 d44 d35 d43 d36 d42 d37 d41 d38 d40 d39 d15 d0 d14 d1 d13 d2 d12 d3 d11 d4 d10 d5 d9 d6 back / bsreq breq / bsack 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 nmi irl3 irl2 irl1 irl0 md2/rxd2 md1/txd2 md0/sck d63 d48 d62 d49 d61 d50 d60 d51 d59 d52 d58 d53 d57 d54 d56 d55 d31 d16 d30 d17 d29 d18 d28 d19 d27 d20 d26 d21 d25 dreq1 dreq0 rxd 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 d8 d7 cke we5 / cas5 /dqm5 we4 / cas4 /dqm4 we1 / cas1 /dqm1 we0 / cas0 /dqm0 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 ckio a6 a5 a4 a3 a2 drak1 drak0 cs3 cs2 ras rd / cass / frame rd/ wr we2 / cas2 /dqm2/ ioicrd we3 / cas3 /dqm3/ ioicwr we6 / cas6 /dqm6 we7 / cas7 /dqm7/ reg d23 d24 d22 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 extal xtal vss-cpg vdd-cpg(3.3v) vss-pll1 vdd-pll1(3.3v) vss-pll2 vdd-pll2(3.3v) trst tdi tck tms tdo asebrk /brkack md6/ iois16 status1 status0 a1 a0 dack1 dack0 md5/ ras2 md4/ ce2b md3/ ce2a a25 a24 a23 a22 a21 a20 a19 a18 sck2/ mreset md7/txd md8/ rts2 tclk cts2 ca * vdd-rtc(3.3v) vss-rtc extal2 xtal2 qfp208 top view vdd (internal) vss (internal) vddq (io) vssq (io) notes: power must be supplied to the on-chip pll power supply pins (vdd-pll1, vdd-pll2, vss-pll1, vss-pll2, vdd-cpg, vss-cpg, vdd-rtc, and vss-rtc) regardless of whether or not the pll circuits, crystal oscillation circuit, and rtc are used. * hardware standby request (SH7750s and SH7750r). in the SH7750, pull up to 3.3 v. figure 1.3 pin arrangement (208-pin qfp)
section 1 overview SH7750, SH7750s, SH7750r group page 12 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 vddq (io) vssq (io) vdd (internal) vss (internal) nc a b c d e f g h 1 vss-cpg xtal extal vdd-cpg trst tdo md6/ iois16 a0 vddq vddq a20 vdd tclk vss-rtc xtal2 extal2 irl2 reset cs4 vdd-pll2 vss status0 dack0 a24 vddq md7/txd ca irl3 rdy vss-pll2 vss-pll1 vdd-pll1 tck vssq vssq md3/ ce2a a22 a18 vddq vddq vdd-rtc md1/txd2 nmi cs0 vssq ckio2enb tdi vdd a1 md5/ ras2 a23 vss md8/ rts2 cts2 vssq irl0 irl1 bs cs1 cs5 cs6 tms asebrk / brkack vddq vddq md4/ ce2b vssq vssq sck2/ mreset d48 rd/ wr2 md2/rxd2 vssq vdd d47 vddq rd2 d32 d33 status1 dack1 vssq a25 a21 a19 d49 vddq d63 md0/sck d62 d45 vddq d46 vss vssq d34 d50 vddq vdd vssq vss d61 vddq d43 d44 d35 vssq d36 d52 vddq d51 vssq d60 d59 vddq d38 d42 d41 d37 vssq vssq d57 d53 d54 d58 vddq d39 d0 vssq d15 vddq d40 d56 vssq d31 d16 d55 vddq d1 vss vssq vdd vddq d14 d30 vssq vss d18 vddq d17 d2 d4 d3 vddq d13 a14 a9 vddq a6 a2 d29 d28 d27 vddq d19 vdd vssq d5 d11 d12 a16 vddq vddq a7 a4 drak0 vssq vss d26 d21 vddq d20 vssq vddq vddq we4 / cas4 / dqm4 we0 / cas0 / dqm0 vdd a11 vssq vssq cs2 rd / cass / frame vssq vssq d25 dreq1 d6 breq / bsack d10 cke we5 / cas5 / dqm5 a17 vss a12 a8 vddq vddq ras we3 / cas3 / dqm3/ iciowr we6 / cas6 / dqm6 we2 / cas2 / dqm2/ iciord rxd back / bsreq vssq d8 vddq vssq a13 vssq ckio2 a3 vdd rd/ wr d24 d22 vssq dreq0 d9 d7 we1 / cas1 / dqm1 a15 vssq a10 ckio a5 drak1 cs3 vddq vddq we7 / cas7 / dqm7/ reg d23 vssq 234567891011121314151617 j k l m n p r t u csp264 (top view) note: power must be supplied to the on-chip pll power supply pins (vdd-pll1, vdd-pll2, vss-pll1, vss-pll2, vdd-cpg, vss-cpg, vdd-rtc, and vss-rtc) regardless of whether or not the pll circuits, crystal oscillation circuit, and rtc are used. figure 1.4 pin arrangement (264-pin csp)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 13 of 1076 sep 24, 2013 xtal2 vss-rtc nmi irl1 irl2 md2/rxd2 irl0 d49 d50 d51 d52 rd/ wr2 d62 d61 d57 d56 d31 d30 d29 d28 d27 d21 dreq1 d54 d55 d16 d17 d18 d19 d20 d25 md0/sck d48 d60 d59 d58 rdy reset cs0 cs1 cs5 cs6 extal vss-pll1 xtal vdd-cpg(3.3v) vss-cpg vss-pll2 vdd-pll1(3.3v) trst vdd-pll2(3.3v) tms tck md6/ iois16 asebrk /brkack status0 status1 a0 a1 dack0 dack1 md5/ ras2 md4/ ce2b md3/ ce2a a25 a24 a23 a22 a21 a20 a19 a18 sck2/ mreset md7/txd tclk cts2 vdd-rtc(3.3v) vss-rtc extal2 irl3 d6 d8 cke we5 / cas5 /dqm5 we1 / cas1 /dqm1 we0 / cas0 /dqm0 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 ckio a5 a6 a3 a4 drak1 a2 cs3 drak0 ras cs2 rd/ wr rd / cass / frame we6 / cas6 /dqm6 we3 / cas3 /dqm3/ iciowr d24 d23 d22 dreq0 rxd a b c d e f g h 1234567891011121314151617 1920 18 j k l m n p r t u v w y rd2 d32 d33 d34 d35 d36 d47 d46 d45 d44 d43 d42 ckio2enb md8/ rts2 ckio2 tdi tdo cs4 bs d37 d53 d63 bga292 (top view) md1/txd2 d26 we2 / cas2 / dqm2/ iciord d11 d41 d40 d15 d14 d13 d12 d4 d5 back / bsreq breq / bsack d38 d39 d0 d1 d2 d3 d10 d9 d7 we4 / cas4 /dqm4 vddq (io) vdd (internal) vss ca we7 / cas7 /dqm7 / reg note: power must be supplied to the on-chip pll power supply pins (vdd-pll1, vdd-pll2, vss-pll1, vss-pll2, vdd-cpg, vss-cpg, vdd-rtc, and vss-rtc) regardless of whether or not the pll circuits, crystal oscillation circuit, and rtc are used. figure 1.5 pin arrangement (292-pin bga)
section 1 overview SH7750, SH7750s, SH7750r group page 14 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1.4 pin functions 1.4.1 pin functions (256-pin bga) table 1.2 pin functions memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 1 b2 rdy i bus ready rdy rdy rdy 2 b1 reset i reset reset 3 c2 cs0 o chip select 0 cs0 cs0 4 c1 cs1 o chip select 1 cs1 cs1 5 d4 cs4 o chip select 4 cs4 cs4 6 d3 cs5 o chip select 5 cs5 ce1a cs5 7 d2 cs6 o chip select 6 cs6 ce1b cs6 8 d1 bs o bust start ( bs ) ( bs ) ( bs ) ( bs ) ( bs ) 9 e4 vssq power io gnd (0 v) 10 e3 rd2 o rd / cass / frame oe cas oe frame 11 f3 vddq power io vdd (3.3 v) 12 f4 vssq power io gnd (0 v) 13 e2 d47 i/o data/port (port) (port) (port) (port) (port) 14 e1 d32 i/o data/port (port) (port) (port) (port) (port) 15 g3 vdd power internal vdd (1.8 v) 16 g4 vss power internal gnd (0 v) 17 f2 d46 i/o data/port (port) (port) (port) (port) (port) 18 f1 d33 i/o data/port (port) (port) (port) (port) (port) 19 h3 vddq power io vdd (3.3 v) 20 h4 vssq power io gnd (0 v) 21 g2 d45 i/o data/port (port) (port) (port) (port) (port) 22 g1 d34 i/o data/port (port) (port) (port) (port) (port) 23 h2 d44 i/o data/port (port) (port) (port) (port) (port) 24 h1 d35 i/o data/port (port) (port) (port) (port) (port) 25 j3 vddq power io vdd (3.3 v) 26 j4 vssq power io gnd (0 v)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 15 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 27 j2 d43 i/o data/port (port) (port) (port) (port) (port) 28 j1 d36 i/o data/port (port) (port) (port) (port) (port) 29 k2 d42 i/o data/port (port) (port) (port) (port) (port) 30 k1 d37 i/o data/port (port) (port) (port) (port) (port) 31 k3 vddq power io vdd (3.3 v) 32 k4 vssq power io gnd (0 v) 33 l1 d41 i/o data/port (port) (port) (port) (port) (port) 34 l2 d38 i/o data/port (port) (port) (port) (port) (port) 35 m1 d40 i/o data/port (port) (port) (port) (port) (port) 36 m2 d39 i/o data/port (port) (port) (port) (port) (port) 37 l3 vddq power io vdd (3.3 v) 38 l4 vssq power io gnd (0 v) 39 n1 d15 i/o data a15 40 n2 d0 i/o data a0 41 p1 d14 i/o data a14 42 p2 d1 i/o data a1 43 m3 vddq power io vdd (3.3 v) 44 m4 vssq power io gnd (0 v) 45 r1 d13 i/o data a13 46 r2 d2 i/o data a2 47 p3 vdd power internal vdd 48 p4 vss power internal gnd (0 v) 49 t1 d12 i/o data a12 50 t2 d3 i/o data a3 51 r3 vddq power io vdd (3.3 v) 52 r4 vssq power io gnd (0 v) 53 u1 d11 i/o data a11 54 u2 d4 i/o data a4 55 v1 d10 i/o data a10 56 v2 d5 i/o data a5 57 t3 vddq power io vdd (3.3 v) 58 t4 vssq power io gnd (0 v) 59 w1 d9 i/o data a9
section 1 overview SH7750, SH7750s, SH7750r group page 16 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 60 y1 d6 i/o data a6 61 u3 back / bsreq o bus acknowledge/ bus request 62 v3 breq / bsack i bus request/bus acknowledge 63 w2 d8 i/o data a8 64 y2 d7 i/o data a7 65 w3 cke o clock output enable cke 66 v5 vddq power io vdd (3.3 v) 67 u5 vssq power io gnd (0 v) 68 y3 we5 / cas5 / dqm5 o d47?d40 select signal we5 cas5 dqm5 69 w4 we4 / cas4 / dqm4 o d39?d32 select signal we4 cas4 dqm4 70 y4 we1 / cas1 / dqm1 o d15?d8 select signal we1 cas1 dqm1 we1 71 w5 we0 / cas0 / dqm0 o d7?d0 select signal we0 cas0 dqm0 72 y5 a17 o address 73 v6 vddq power io vdd (3.3 v) 74 u6 vssq power io gnd (0 v) 75 w6 a16 o address 76 y6 a15 o address 77 v7 vdd power internal vdd 78 u7 vss power internal gnd (0 v) 79 w7 a14 o address 80 y7 a13 o address 81 v8 vddq power io vdd (3.3 v) 82 u8 vssq power io gnd (0 v) 83 v4 nc 84 w8 a12 o address 85 y8 a11 o address
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 17 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 86 w9 a10 o address 87 v9 vddq power io vdd (3.3 v) 88 u9 vssq power io gnd (0 v) 89 y9 a9 o address 90 w10 a8 o address 91 y10 a7 o address 92 y11 ckio o clock output ckio ckio ckio 93 v10 vddq power io vdd (3.3 v) 94 u10 vssq power io gnd (0 v) 95 w11 ckio2 o ckio * 1 ckio ckio ckio 96 y12 a6 o address 97 w12 a5 o address 98 y13 a4 o address 99 v11 vddq power io vdd (3.3 v) 100 u11 vssq power io gnd (0 v) 101 w13 a3 o address 102 y14 a2 o address 103 v12 drak1 o dmac1 request acknowledge 104 u13 drak0 o dmac0 request acknowledge 105 v13 vddq power io vdd (3.3 v) 106 u12 vssq power io gnd (0 v) 107 w14 cs3 o chip select 3 cs3 ( cs3 ) cs3 cs3 108 y15 cs2 o chip select 2 cs2 ( cs2 ) cs2 cs2 109 v14 vdd power internal vdd 110 u14 vss power internal gnd (0 v) 111 w15 ras o ras ras ras 112 y16 rd / cass / frame o read/ cas / frame oe cas oe frame 113 v15 vddq power io vdd (3.3 v) 114 u15 vssq power io gnd (0 v) 115 w16 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr
section 1 overview SH7750, SH7750s, SH7750r group page 18 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 116 y17 we2 / cas2 / dqm2/ iciord o d23?d16 select signal we2 cas2 dqm2 iciord 117 w17 we3 / cas3 / dqm3/ iciowr o d31?d24 select signal we3 cas3 dqm3 iciowr 118 y18 we6 / cas6 / dqm6 o d55?d48 select signal we6 cas6 dqm6 119 v16 vddq power io vdd (3.3 v) 120 u16 vssq power io gnd (0 v) 121 w18 we7 / cas7 / dqm7/ reg o d63?d56 select signal we7 cas7 dqm7 reg 122 y19 d23 i/o data a23 123 w19 d24 i/o data a24 124 y20 d22 i/o data a22 125 v17 rxd i sci data input 126 u17 dreq0 i request from dmac0 127 u18 dreq1 i request from dmac1 128 w20 d25 i/o data a25 129 t18 vddq power io vdd (3.3 v) 130 t17 vssq power io gnd (0 v) 131 v19 d21 i/o data a21 132 v20 d26 i/o data 133 u19 d20 i/o data a20 134 u20 d27 i/o data 135 r18 vddq power io vdd (3.3 v) 136 r17 vssq power io gnd (0 v) 137 t19 d19 i/o data a19 138 t20 d28 i/o data 139 p18 vdd power internal vdd 140 p17 vss power internal gnd (0 v) 141 r19 d18 i/o data a18 142 r20 d29 i/o data
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 19 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 143 n18 vddq power io vdd (3.3 v) 144 n17 vssq power io gnd (0 v) 145 p19 d17 i/o data a17 146 p20 d30 i/o data 147 n19 d16 i/o data a16 148 n20 d31 i/o data 149 m18 vddq power io vdd (3.3 v) 150 m17 vssq power io gnd (0 v) 151 m19 d55 i/o data 152 m20 d56 i/o data 153 l19 d54 i/o data 154 l20 d57 i/o data 155 l18 vddq power io vdd (3.3 v) 156 l17 vssq power io gnd (0 v) 157 k20 d53 i/o data 158 k19 d58 i/o data 159 j20 d52 i/o data 160 j19 d59 i/o data 161 k18 vddq power io vdd (3.3 v) 162 k17 vssq power io gnd (0 v) 163 h20 d51 i/o data/port (port) (port) (port) (port) (port) 164 h19 d60 i/o data 165 g20 d50 i/o data/port (port) (port) (port) (port) (port) 166 g19 d61 i/o data accsize0 167 j18 vddq power io vdd (3.3 v) 168 j17 vssq power io gnd (0 v) 169 f20 d49 i/o data/port (port) (port) (port) (port) (port) 170 f19 d62 i/o data accsize1 171 g18 vdd power internal vdd 172 g17 vss power internal gnd (0 v) 173 e20 d48 i/o data/port (port) (port) (port) (port) (port) 174 e19 d63 i/o data accsize2 175 f18 vddq power io vdd (3.3 v)
section 1 overview SH7750, SH7750s, SH7750r group page 20 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 176 f17 vssq power io gnd (0 v) 177 e17 vssq power io gnd (0 v) 178 e18 rd/ wr2 o rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 179 d20 md0/sck i/o mode/sci clock md0 sck sck sck sck sck 180 d19 md1/txd2 i/o mode scif data output md1 txd2 txd2 txd2 txd2 txd2 181 d18 md2/rxd2 i mode/scif data input md2 rxd2 rxd2 rxd2 rxd2 rxd2 182 c20 irl0 i interrupt 0 183 c19 irl1 i interrupt 1 184 b20 irl2 i interrupt 2 185 c18 irl3 i interrupt 3 186 a20 nmi i nonmaskable interrupt 187 b19 xtal2 o rtc crystal resonator pin 188 a19 extal2 i rtc crystal resonator pin 189 b18 vss-rtc power rtc gnd (0 v) 190 a18 vdd-rtc power rtc vdd (3.3 v) 191 d17 ca i * 2 192 c17 vss power internal gnd (0 v) 193 b17 vddq power io vdd (3.3 v) 194 c16 cts2 i/o scif data control ( cts ) 195 a17 tclk i/o rtc/tmu clock 196 b16 md8/ rts2 i/o mode/scif data control ( rts ) md8 rts2 rts2 rts2 rts2 rts2 197 c15 vddq power io vdd (3.3 v) 198 d15 vssq power io gnd (0 v) 199 b15 md7/txd i/o mode/sci data output md7 txd txd txd txd txd
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 21 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 200 a16 sck2/ mreset i scif clock/ manual reset mreset sck2 sck2 sck2 sck2 sck2 201 c14 vdd power internal vdd 202 d14 vss power internal gnd (0 v) 203 a15 a18 o address 204 b14 a19 o address 205 c13 vddq power io vdd (3.3 v) 206 d13 vssq power io gnd (0 v) 207 a14 a20 o address 208 b13 a21 o address 209 a13 a22 o address 210 b12 a23 o address 211 c12 vddq power io vdd (3.3 v) 212 d12 vssq power io gnd (0 v) 213 a12 a24 o address 214 b11 a25 o address 215 a11 md3/ ce2a i/o mode/ pcmcia-ce md3 ce2a 216 a10 md4/ ce2b i/o mode/ pcmcia-ce md4 ce2b 217 c11 vddq power io vdd (3.3 v) 218 d11 vssq power io gnd (0 v) 219 b10 md5/ ras2 i/o mode/ ras (dram) md5 ras2 220 a9 dack0 o dmac0 bus acknowledge 221 b9 dack1 o dmac1 bus acknowledge 222 c8 a0 o address 223 c10 vddq power io vdd (3.3 v) 224 d10 vssq power io gnd (0 v) 225 d8 a1 o address 226 a8 status0 o status 227 b8 status1 o status
section 1 overview SH7750, SH7750s, SH7750r group page 22 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 228 a7 md6/ iois16 i mode/ iois16 (pcmcia) md6 iois16 229 c9 vddq power io vdd (3.3 v) 230 d9 vssq power io gnd (0 v) 231 b7 asebrk / brkack i/o pin break/ acknowledge (h-udi) 232 a6 tdo o data out (h-udi) 233 c7 vdd power internal vdd 234 d7 vss power internal gnd (0 v) 235 b6 tms i mode (h-udi) 236 a5 tck i clock (h-udi) 237 b5 tdi i data in (h-udi) 238 c4 trst i reset (h-udi) 239 c3 ckio2enb i ckio2, rd2 , rd/ wr2 enable 240 c6 nc 241 a4 vdd-pll2 power pll2 vdd (3.3v) 242 d6 vss-pll2 power pll2 gnd (0v) 243 b4 vdd-pll1 power pll1 vdd (3.3v) 244 d5 vss-pll1 power pll1 gnd (0v) 245 a3 vdd-cpg power cpg vdd (3.3v) 246 b3 vss-cpg power cpg gnd (0v) 247 a2 xtal o crystal resonator 248 a1 extal i external input clock/crystal resonator 249 c5 nc
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 23 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 250 d16 nc 251 h17 nc 252 h18 nc 253 n3 nc 254 n4 nc 255 u4 nc 256 v18 nc legend: i: input o: output i/o: input/output power: power supply notes: supply power to all power pins. for t he SH7750s, supply power to rtc at a minimum in hardware standby mode. power must be supplied to vdd-pll1/2 and vss-pll1/2 regardless of whether or not the on-chip pll circuits are used. power must be supplied to vdd-cpg and vs s-cpg regardless of whether or not the on- chip crystal oscillation circuit is used. power must be supplied to vdd-rtc and vs s-rtc regardless of w hether or not the on- chip rtc is used. vssq, vss, vss-rtc, vss-pll1/2, and vss- cpg are connected inside the package. nc pins must be left completely open, and not connected to a power supply, gnd, etc. 1. ckio2 is not connected to pll2. 2. hardware standby request (SH7750s and SH7750r). in the SH7750, pull up to 3.3 v.
section 1 overview SH7750, SH7750s, SH7750r group page 24 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1.4.2 pin functions (208-pin qfp) table 1.3 pin functions memory interface pin no. pin name i/o function reset sram dram sdram pcmcia mpx 1 rdy i bus ready rdy rdy rdy 2 reset i reset reset 3 cs0 o chip select 0 cs0 cs0 4 cs1 o chip select 1 cs1 cs1 5 cs4 o chip select 4 cs4 cs4 6 cs5 o chip select 5 cs5 ce1a cs5 7 cs6 o chip select 6 cs6 ce1b cs6 8 bs o bust start ( bs ) ( bs ) ( bs ) ( bs ) ( bs ) 9 vddq power io vdd (3.3 v) 10 vssq power io gnd (0 v) 11 d47 i/o data/port (port) (p ort) (port) (port) (port) 12 d32 i/o data/port (port) (p ort) (port) (port) (port) 13 vdd power internal vdd 14 vss power internal gnd (0 v) 15 d46 i/o data/port (port) (p ort) (port) (port) (port) 16 d33 i/o data/port (port) (p ort) (port) (port) (port) 17 d45 i/o data/port (port) (p ort) (port) (port) (port) 18 d34 i/o data/port (port) (p ort) (port) (port) (port) 19 d44 i/o data/port (port) (p ort) (port) (port) (port) 20 d35 i/o data/port (port) (p ort) (port) (port) (port) 21 vddq power io vdd (3.3 v) 22 vssq power io gnd (0 v) 23 d43 i/o data/port (port) (p ort) (port) (port) (port) 24 d36 i/o data/port (port) (p ort) (port) (port) (port) 25 d42 i/o data/port (port) (p ort) (port) (port) (port) 26 d37 i/o data/port (port) (p ort) (port) (port) (port) 27 d41 i/o data/port (port) (p ort) (port) (port) (port) 28 d38 i/o data/port (port) (p ort) (port) (port) (port) 29 d40 i/o data/port (port) (p ort) (port) (port) (port)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 25 of 1076 sep 24, 2013 memory interface pin no. pin name i/o function reset sram dram sdram pcmcia mpx 30 d39 i/o data/port (port) (p ort) (port) (port) (port) 31 vddq power io vdd (3.3 v) 32 vssq power io gnd (0 v) 33 d15 i/o data a15 34 d0 i/o data a0 35 d14 i/o data a14 36 d1 i/o data a1 37 d13 i/o data a13 38 d2 i/o data a2 39 vdd power internal vdd (1.8 v) 40 vss power internal gnd (0 v) 41 d12 i/o data a12 42 d3 i/o data a3 43 vddq power io vdd (3.3 v) 44 vssq power io gnd (0 v) 45 d11 i/o data a11 46 d4 i/o data a4 47 d10 i/o data a10 48 d5 i/o data a5 49 d9 i/o data a9 50 d6 i/o data a6 51 back / bsreq o bus acknowledge/ bus request 52 breq / bsack i bus request/bus acknowledge 53 d8 i/o data a8 54 d7 i/o data a7 55 cke o clock output enable cke 56 vddq power io vdd (3.3 v) 57 vssq power io gnd (0 v)
section 1 overview SH7750, SH7750s, SH7750r group page 26 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface pin no. pin name i/o function reset sram dram sdram pcmcia mpx 58 we5 / cas5 / dqm5 o d47?d40 select signal we5 cas5 dqm5 59 we4 / cas4 / dqm4 o d39?d32 select signal we4 cas4 dqm4 60 we1 / cas1 / dqm1 o d15?d8 select signal we1 cas1 dqm1 we1 61 we0 / cas0 / dqm0 o d7?d0 select signal we0 cas0 dqm0 62 a17 o address 63 a16 o address 64 a15 o address 65 vdd power internal vdd 66 vss power internal gnd (0 v) 67 a14 o address 68 a13 o address 69 vddq power io vdd (3.3 v) 70 vssq power io gnd (0 v) 71 a12 o address 72 a11 o address 73 a10 o address 74 a9 o address 75 a8 o address 76 a7 o address 77 ckio o clock output ckio ckio ckio 78 vddq power io vdd (3.3 v) 79 vssq power io gnd (0 v) 80 a6 o address 81 a5 o address 82 a4 o address 83 a3 o address 84 a2 o address 85 drak1 o dmac1 request acknowledge
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 27 of 1076 sep 24, 2013 memory interface pin no. pin name i/o function reset sram dram sdram pcmcia mpx 86 drak0 o dmac0 request acknowledge 87 vddq power io vdd (3.3 v) 88 vssq power io gnd (0 v) 89 cs3 o chip select 3 cs3 ( cs3 ) cs3 cs3 90 cs2 o chip select 2 cs2 ( cs2 ) cs2 cs2 91 vdd power internal vdd 92 vss power internal gnd (0 v) 93 ras o ras ras ras 94 rd / cass / frame o read/ cas / frame oe cas oe frame 95 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 96 we2 / cas2 / dqm2/ iciord o d23?d16 select signal we2 cas2 dqm2 iciord 97 we3 / cas3 / dqm3/ iciowr o d31?d24 select signal we3 cas3 dqm3 iciowr 98 we6 / cas6 / dqm6 o d55?d48 select signal we6 cas6 dqm6 99 vddq power io vdd (3.3 v) 100 vssq power io gnd (0 v) 101 we7 / cas7 / dqm7/ reg o d63?d56 select signal we7 cas7 dqm7 reg 102 d23 i/o data a23 103 d24 i/o data a24 104 d22 i/o data a22 105 rxd i sci data input 106 dreq0 i request from dmac0 107 dreq1 i request from dmac1 108 d25 i/o data a25 109 d21 i/o data a21 110 d26 i/o data 111 d20 i/o data a20
section 1 overview SH7750, SH7750s, SH7750r group page 28 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface pin no. pin name i/o function reset sram dram sdram pcmcia mpx 112 d27 i/o data 113 vddq power io vdd (3.3 v) 114 vssq power io gnd (0 v) 115 d19 i/o data a19 116 d28 i/o data 117 vdd power internal vdd 118 vss power internal gnd (0 v) 119 d18 i/o data a18 120 d29 i/o data 121 d17 i/o data a17 122 d30 i/o data 123 d16 i/o data a16 124 d31 i/o data 125 vddq power io vdd (3.3 v) 126 vssq power io gnd (0 v) 127 d55 i/o data 128 d56 i/o data 129 d54 i/o data 130 d57 i/o data 131 d53 i/o data 132 d58 i/o data 133 d52 i/o data 134 d59 i/o data 135 vddq power io vdd (3.3 v) 136 vssq power io gnd (0 v) 137 d51 i/o data/port (port) (p ort) (port) (port) (port) 138 d60 i/o data 139 d50 i/o data/port (port) (p ort) (port) (port) (port) 140 d61 i/o data accsize0 141 d49 i/o data/port (port) (p ort) (port) (port) (port) 142 d62 i/o data accsize1 143 vdd power internal vdd
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 29 of 1076 sep 24, 2013 memory interface pin no. pin name i/o function reset sram dram sdram pcmcia mpx 144 vss power internal gnd (0 v) 145 d48 i/o data/port (port) (p ort) (port) (port) (port) 146 d63 i/o data accsize2 147 vddq power io vdd (3.3 v) 148 vssq power io gnd (0 v) 149 md0/sck i/o mode/sci clock md0 sck sck sck sck sck 150 md1/txd2 i/o mode scif data output md1 txd2 txd2 txd2 txd2 txd2 151 md2/rxd2 i mode/scif data input md2 rxd2 rxd2 rxd2 rxd2 rxd2 152 irl0 i interrupt 0 153 irl1 i interrupt 1 154 irl2 i interrupt 2 155 irl3 i interrupt 3 156 nmi i nonmaskable interrupt 157 xtal2 o rtc crystal resonator pin 158 extal2 i rtc crystal resonator pin 159 vss-rtc power rtc gnd (0 v) 160 vdd-rtc power rtc vdd (3.3 v) 161 ca i * 162 vss power internal gnd (0 v) 163 vddq power io vdd (3.3 v) 164 cts2 i/o scif data control ( cts ) 165 tclk i/o rtc/tmu clock 166 md8/ rts2 i/o mode/scif data control ( rts ) md8 rts2 rts2 rts2 rts2 rts2 167 md7/txd i/o mode/sci data output md7 txd txd txd txd txd
section 1 overview SH7750, SH7750s, SH7750r group page 30 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface pin no. pin name i/o function reset sram dram sdram pcmcia mpx 168 sck2/ mreset i scif clock/ manual reset mreset sck2 sck2 sck2 sck2 sck2 169 vdd power internal vdd 170 vss power internal gnd (0 v) 171 a18 o address 172 a19 o address 173 a20 o address 174 a21 o address 175 a22 o address 176 a23 o address 177 vddq power io vdd (3.3 v) 178 vssq power io gnd (0 v) 179 a24 o address 180 a25 o address 181 md3/ ce2a i/o mode/ pcmcia-ce md3 ce2a 182 md4/ ce2b i/o mode/ pcmcia-ce md4 ce2b 183 md5/ ras2 i/o mode/ ras (dram) md5 ras2 184 dack0 o dmac0 bus acknowledge 185 dack1 o dmac1 bus acknowledge 186 a0 o address 187 vddq power io vdd (3.3 v) 188 vssq power io gnd (0 v) 189 a1 o address 190 status0 o status 191 status1 o status 192 md6/ iois16 i mode/ iois16 (pcmcia) md6 iois16 193 asebrk / brkack i/o pin break/ acknowledge (h-udi )
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 31 of 1076 sep 24, 2013 memory interface pin no. pin name i/o function reset sram dram sdram pcmcia mpx 194 tdo o data out (h-udi) 195 vdd power internal vdd 196 vss power internal gnd (0 v) 197 tms i mode (h-udi) 198 tck i clock (h-udi) 199 tdi i data in (h-udi) 200 trst i reset (h-udi) 201 vdd-pll2 power pll2 vdd (3.3v) 202 vss-pll2 power pll2 gnd (0v) 203 vdd-pll1 power pll1 vdd (3.3v) 204 vss-pll1 power pll1 gnd (0v) 205 vdd-cpg power cpg vdd (3.3v) 206 vss-cpg power cpg gnd (0v) 207 xtal o crystal resonator 208 extal i external input clock/crystal resonator legend: i: input o: output i/o: input/output power: power supply notes: supply power to all power pins. for t he SH7750s, supply power to rtc at a minimum in hardware standby mode. power must be supplied to vdd-pll1/2 and vss-pll1/2 regardless of whether or not the on-chip pll circuits are used. power must be supplied to vdd-cpg and vs s-cpg regardless of whether or not the on- chip crystal oscillation circuit is used. power must be supplied to vdd-rtc and vs s-rtc regardless of w hether or not the on- chip rtc is used. vssq, vss, vss-rtc, vss-pll1/2, and vss- cpg are connected inside the package. the rd2 , rd/ wr2 , ckio2, and ckio2enb pins are not provided on the qfp package. for a qfp package, the maximum operating frequency of the external bus is 84 mhz. * hardware standby request (SH7750s and sh 7750r). in the SH7750, pull up to 3.3 v.
section 1 overview SH7750, SH7750s, SH7750r group page 32 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1.4.3 pin functions (264-pin csp) table 1.4 pin functions memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 1 c2 rdy i bus ready rdy rdy rdy 2 b1 reset i reset reset 3 d3 cs0 o chip select 0 cs0 cs0 4 e2 cs1 o chip select 1 cs1 cs1 5 b2 cs4 o chip select 4 cs4 cs4 6 e3 cs5 o chip select 5 cs5 ce1a cs5 7 e4 cs6 o chip select 6 cs6 ce1b cs6 8 e1 bs o bus start ( bs ) ( bs ) ( bs ) ( bs ) ( bs ) 9 f4 rd2 o rd / cass / frame oe cas oe frame 10 f3 vddq power io vdd (3.3 v) 11 d4 vssq power io gnd (0 v) 12 f2 d47 i/o data/port (port) (port) (port) (port) (port) 13 f5 d32 i/o data/port (port) (port) (port) (port) (port) 14 f1 vdd power internal vdd (1.5 v) 15 g4 vss power internal gnd (0 v) 16 g3 d46 i/o data/port (port) (port) (port) (port) (port) 17 f6 d33 i/o data/port (port) (port) (port) (port) (port) 18 g2 vddq power io vdd (3.3 v) 19 g5 vssq power io gnd (0 v) 20 g1 d45 i/o data/port (port) (port) (port) (port) (port) 21 g6 d34 i/o data/port (port) (port) (port) (port) (port) 22 h3 d44 i/o data/port (port) (port) (port) (port) (port) 23 h4 d35 i/o data/port (port) (port) (port) (port) (port) 24 h1 vddq power io vdd (3.3 v) 25 h5 vssq power io gnd (0 v) 26 h2 d43 i/o data/port (port) (port) (port) (port) (port) 27 h6 d36 i/o data/port (port) (port) (port) (port) (port) 28 j3 d42 i/o data/port (port) (port) (port) (port) (port)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 33 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 29 j5 d37 i/o data/port (port) (port) (port) (port) (port) 30 j1 vddq power io vdd (3.3 v) 31 j6 vssq power io gnd (0 v) 32 j4 d41 i/o data/port (port) (port) (port) (port) (port) 33 j2 d38 i/o data/port (port) (port) (port) (port) (port) 34 k6 d40 i/o data/port (port) (port) (port) (port) (port) 35 k1 d39 i/o data/port (port) (port) (port) (port) (port) 36 k5 vddq power io vdd (3.3 v) 37 k3 vssq power io gnd (0 v) 38 k4 d15 i/o data a15 39 k2 d0 i/o data a0 40 l6 d14 i/o data a14 41 l1 d1 i/o data a1 42 l5 vddq power io vdd (3.3 v) 43 l3 vssq power io gnd (0 v) 44 m5 d13 i/o data a13 45 m1 d2 i/o data a2 46 l4 vdd power internal vdd (1.5 v) 47 l2 vss power internal gnd (0 v) 48 n5 d12 i/o data a12 49 m3 d3 i/o data a3 50 m4 vddq power io vdd (3.3 v) 51 n1 vssq power io gnd (0 v) 52 n4 d11 i/o data a11 53 m2 d4 i/o data a4 54 r3 d10 i/o data a10 55 n3 d5 i/o data a5 56 p3 vddq power io vdd (3.3 v) 57 p1 vssq power io gnd (0 v) 58 u1 d9 i/o data a9 59 r1 d6 i/o data a6
section 1 overview SH7750, SH7750s, SH7750r group page 34 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 60 t1 back / bsreq o bus acknowledge/ bus request 61 r2 breq / bsack i bus request/bus acknowledge 62 t3 d8 i/o data a8 63 u2 d7 i/o data a7 64 r4 cke o clock output enable cke 65 t5 vddq power io vdd (3.3 v) 66 t2 vssq power io gnd (0 v) 67 r5 we5 / cas5 / dqm5 o d47?d40 select signal we5 cas5 dqm5 68 p5 we4 / cas4 / dqm4 o d39?d32 select signal we4 cas4 dqm4 69 u5 we1 / cas1 / dqm1 o d15?d8 select signal we1 cas1 dqm1 we1 70 p6 we0 / cas0 / dqm0 o d7?d0 select signal we0 cas0 dqm0 71 r6 a17 o address 72 p4 vddq power io vdd (3.3 v) 73 t6 vssq power io gnd (0 v) 74 n6 a16 o address 75 u6 a15 o address 76 p7 vdd power internal vdd (1.5 v) 77 r7 vss power internal gnd (0 v) 78 m6 a14 o address 79 t7 a13 o address 80 n7 vddq power io vdd (3.3 v) 81 u7 vssq power io gnd (0 v) 82 r8 a12 o address 83 p8 a11 o address 84 u8 a10 o address 85 n8 vddq power io vdd (3.3 v)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 35 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 86 t8 vssq power io gnd (0 v) 87 m8 a9 o address 88 r9 a8 o address 89 n9 a7 o address 90 u9 ckio o clock output ckio ckio ckio 91 m9 vddq power io vdd (3.3 v) 92 p9 vssq power io gnd (0 v) 93 t9 ckio2 o ckio * ckio ckio ckio 94 m10 a6 o address 95 u10 a5 o address 96 n10 a4 o address 97 r10 vddq power io vdd (3.3 v) 98 p10 vssq power io gnd (0 v) 99 t10 a3 o address 100 m11 a2 o address 101 u11 drak1 o dmac1 request acknowledge 102 n11 drak0 o dmac0 request acknowledge 103 r11 vddq power io vdd (3.3 v) 104 n12 vssq power io gnd (0 v) 105 u12 cs3 o chip select 3 cs3 ( cs3 ) cs3 cs3 106 p11 cs2 o chip select 2 cs2 ( cs2 ) cs2 cs2 107 t11 vdd power internal vdd (1.5 v) 108 n13 vss power internal gnd (0 v) 109 r12 ras o ras ras ras 110 p12 rd / cass / frame o read/ cas / frame oe cas oe frame 111 u13 vddq power io vdd (3.3 v) 112 p13 vssq power io gnd (0 v) 113 t12 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 114 r15 we2 / cas2 / dqm2/ iciord o d23?d16 select signal we2 cas2 dqm2 iciord
section 1 overview SH7750, SH7750s, SH7750r group page 36 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 115 r13 we3 / cas3 / dqm3/ iciowr o d31?d24 select signal we3 cas3 dqm3 iciowr 116 r14 we6 / cas6 / dqm6 o d55?d48 select signal we6 cas6 dqm6 117 u14 vddq power io vdd (3.3 v) 118 u17 vssq power io gnd (0 v) 119 u15 we7 / cas7 / dqm7/ reg o d63?d56 select signal we7 cas7 dqm7 reg 120 u16 d23 i/o data a23 121 t13 d24 i/o data a24 122 t15 d22 i/o data a22 123 r16 rxd i sci1 data input 124 t17 dreq0 i request from dmac0 125 p17 dreq1 i request from dmac1 126 p15 d25 i/o data a25 127 n16 vddq power io vdd (3.3 v) 128 t16 vssq power io gnd (0 v) 129 n15 d21 i/o data a21 130 n14 d26 i/o data 131 n17 d20 i/o data a20 132 m14 d27 i/o data 133 m15 vddq power io vdd (3.3 v) 134 p14 vssq power io gnd (0 v) 135 m16 d19 i/o data a19 136 m13 d28 i/o data 137 m17 vdd power internal vdd (1.5 v) 138 l14 vss power internal gnd (0 v) 139 l15 d18 i/o data a18 140 m12 d29 i/o data 141 l16 vddq power io vdd (3.3 v) 142 l13 vssq power io gnd (0 v)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 37 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 143 l17 d17 i/o data a17 144 l12 d30 i/o data 145 k15 d16 i/o data a16 146 k14 d31 i/o data 147 k17 vddq power io vdd (3.3 v) 148 k13 vssq power io gnd (0 v) 149 k16 d55 i/o data 150 k12 d56 i/o data 151 j15 d54 i/o data 152 j13 d57 i/o data 153 j17 vddq power io vdd (3.3 v) 154 j12 vssq power io gnd (0 v) 155 j14 d53 i/o data 156 j16 d58 i/o data 157 h12 d52 i/o data 158 h17 d59 i/o data 159 h13 vddq power io vdd (3.3 v) 160 h15 vssq power io gnd (0 v) 161 h14 d51 i/o data/port (port) (port) (port) (port) (port) 162 h16 d60 i/o data 163 g12 d50 i/o data/port (port) (port) (port) (port) (port) 164 g17 d61 i/o data accsize0 165 g13 vddq power io vdd (3.3 v) 166 g15 vssq power io gnd (0 v) 167 f13 d49 i/o data/port (port) (port) (port) (port) (port) 168 f17 d62 i/o data accsize1 169 g14 vdd power internal vdd (1.5 v) 170 g16 vss power internal gnd (0 v) 171 e13 d48 i/o data/port (port) (port) (port) (port) (port) 172 f15 d63 i/o data accsize2 173 f14 vddq power io vdd (3.3 v) 174 e17 vssq power io gnd (0 v)
section 1 overview SH7750, SH7750s, SH7750r group page 38 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 175 e14 rd/ wr2 o rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 176 f16 md0/sck i/o mode/sci1 clock md0 sck sck sck sck sck 177 c15 md1/txd2 i/o mode/scif data output md1 txd2 txd2 txd2 txd2 txd2 178 e15 md2/rxd2 i mode/scif data input md2 rxd2 rxd2 rxd2 rxd2 rxd2 179 d15 irl0 i interrupt 0 180 d17 irl1 i interrupt 1 181 a17 irl2 i interrupt 2 182 b17 irl3 i interrupt 3 183 c16 nmi i nonmaskable interrupt 184 a15 xtal2 o rtc crystal resonator pin 185 a16 extal2 i rtc crystal resonator pin 186 a14 vss-rtc power rtc gnd (0 v) 187 c14 vdd-rtc power rtc vdd (3.3 v) 188 b13 ca i hardware standby request 189 c13 vddq power io vdd (3.3 v) 190 d13 cts2 i/o scif data control ( cts ) 191 a13 tclk i/o rtc/tmu clock 192 d12 md8/ rts2 i/o mode/scif data control ( rts ) md8 rts2 rts2 rts2 rts2 rts2 193 c12 vddq power io vdd (3.3 v) 194 d14 vssq power io gnd (0 v) 195 b12 md7/txd i/o mode/sci1 data output md7 txd txd txd txd txd 196 e12 sck2/ mreset i scif clock/ manual reset mreset sck2 sck2 sck2 sck2 sck2 197 a12 vdd power internal vdd (1.5 v)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 39 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 198 d11 vss power internal gnd (0 v) 199 c11 a18 o address 200 f12 a19 o address 201 b11 vddq power io vdd (3.3 v) 202 e11 vssq power io gnd (0 v) 203 a11 a20 o address 204 f11 a21 o address 205 c10 a22 o address 206 d10 a23 o address 207 a10 vddq power io vdd (3.3 v) 208 e10 vssq power io gnd (0 v) 209 b10 a24 o address 210 f10 a25 o address 211 c9 md3/ ce2a i/o mode/ pcmcia-ce md3 ce2a 212 e9 md4/ ce2b i/o mode/ pcmcia-ce md4 ce2b 213 a9 vddq power io vdd (3.3 v) 214 f9 vssq power io gnd (0 v) 215 d9 md5/ ras2 i/o mode/ ras (dram) md5 ras2 216 b9 dack0 o dmac0 bus acknowledge 217 f8 dack1 o dmac1 bus acknowledge 218 a8 a0 o address 219 e8 vddq power io vdd (3.3 v) 220 c8 vssq power io gnd (0 v) 221 d8 a1 o address 222 b8 status0 o status 223 f7 status1 o status 224 a7 md6/ iois16 i mode/ iois16 (pcmcia) md6 iois16 225 e7 vddq power io vdd (3.3 v) 226 c7 vssq power io gnd (0 v)
section 1 overview SH7750, SH7750s, SH7750r group page 40 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 227 e6 asebrk / brkack i/o pin break/ acknowledge (h-udi ) 228 a6 tdo o data out (h-udi) 229 d7 vdd power internal vdd (1.5 v) 230 b7 vss power internal gnd (0 v) 231 e5 tms i mode (h-udi) 232 c6 tck i clock (h-udi) 233 d6 tdi i data in (h-udi) 234 a5 trst i reset (h-udi) 235 d5 ckio2enb i ckio2, rd2 , rd/ wr2 enable 236 b6 vdd-pll2 power pll2 vdd (3.3v) 237 c3 vss-pll2 power pll2 gnd (0v) 238 c5 vdd-pll1 power pll1 vdd (3.3v) 239 c4 vss-pll1 power pll1 gnd (0v) 240 a4 vdd-cpg power cpg vdd (3.3v) 241 a1 vss-cpg power cpg gnd (0v) 242 a2 xtal o crystal resonator 243 a3 extal i external clock/ crystal resonator 244 b3 nc-1 245 b4 nc-2 246 b5 nc-3 247 b14 nc-4 248 b15 nc-5 249 b16 nc-6 250 c1 nc-7 251 c17 nc-8 252 d1 nc-9 253 d2 nc-10 254 d16 nc-11 255 e16 nc-12
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 41 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 256 m7 nc-13 257 n2 nc-14 258 p2 nc-15 259 p16 nc-16 260 r17 nc-17 261 t4 nc-18 262 t14 nc-19 263 u3 nc-20 264 u4 nc-21 legend: i: input o: output i/o: input/output power: power supply notes: supply power to all power pins. for t he SH7750s, supply power to rtc at a minimum in hardware standby mode. power must be supplied to vdd-pll1/2 and vss-pll1/2 regardless of whether or not the on-chip pll circuits are used. power must be supplied to vdd-cpg and vs s-cpg regardless of whether or not the on- chip crystal oscillation circuit is used. power must be supplied to vdd-rtc and vs s-rtc regardless of w hether or not the on- chip rtc is used. nc pins must be left completely open, and not connected to a power supply, gnd, etc. * ckio2 is not connected to pll2.
section 1 overview SH7750, SH7750s, SH7750r group page 42 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1.4.4 pin functions (292-pin bga) table 1.5 pin functions memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 1 b2 rdy i bus ready rdy rdy rdy 2 b1 reset i reset reset 3 c2 cs0 o chip select 0 cs0 cs0 4 c1 cs1 o chip select 1 cs1 cs1 5 d3 cs4 o chip select 4 cs4 cs4 6 d2 cs5 o chip select 5 cs5 ce1a cs5 7 d1 cs6 o chip select 6 cs6 ce1b cs6 8 e3 bs o bus start ( bs ) ( bs ) ( bs ) ( bs ) ( bs ) 9 e4 vss power gnd (0 v) 10 e2 rd2 o rd / cass / frame oe cas oe frame 11 f3 vddq power io vdd (3.3 v) 12 f4 vss power gnd (0 v) 13 e1 d47 i/o data/port (port) (port) (port) (port) (port) 14 f2 d32 i/o data/port (port) (port) (port) (port) (port) 15 g3 vdd power internal vdd 16 g4 vss power gnd (0 v) 17 f1 d46 i/o data/port (port) (port) (port) (port) (port) 18 g2 d33 i/o data/port (port) (port) (port) (port) (port) 19 h3 vddq power io vdd (3.3 v) 20 h4 vss power gnd (0 v) 21 g1 d45 i/o data/port (port) (port) (port) (port) (port) 22 h2 d34 i/o data/port (port) (port) (port) (port) (port) 23 h1 d44 i/o data/port (port) (port) (port) (port) (port) 24 j2 d35 i/o data/port (port) (port) (port) (port) (port) 25 j3 vddq power io vdd (3.3 v) 26 j4 vss power gnd (0 v) 27 j1 d43 i/o data/port (port) (port) (port) (port) (port) 28 k2 d36 i/o data/port (port) (port) (port) (port) (port) 29 k1 d42 i/o data/port (port) (port) (port) (port) (port)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 43 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 30 l3 d37 i/o data/port (port) (port) (port) (port) (port) 31 k3 vddq power io vdd (3.3 v) 32 k4 vss power gnd (0 v) 33 l2 d41 i/o data/port (port) (port) (port) (port) (port) 34 l1 d38 i/o data/port (port) (port) (port) (port) (port) 35 m2 d40 i/o data/port (port) (port) (port) (port) (port) 36 m1 d39 i/o data/port (port) (port) (port) (port) (port) 37 m3 vddq power io vdd (3.3 v) 38 l4 vss power gnd (0 v) 39 n2 d15 i/o data a15 40 n1 d0 i/o data a0 41 p2 d14 i/o data a14 42 p1 d1 i/o data a1 43 n3 vddq power io vdd (3.3 v) 44 m4 vss power gnd (0 v) 45 r2 d13 i/o data a13 46 r1 d2 i/o data a2 47 p3 vdd power internal vdd 48 p4 vss power gnd (0 v) 49 t2 d12 i/o data a12 50 t1 d3 i/o data a3 51 r3 vddq power io vdd (3.3 v) 52 r4 vss power gnd (0 v) 53 u3 d11 i/o data a11 54 u2 d4 i/o data a4 55 u1 d10 i/o data a10 56 v2 d5 i/o data a5 57 t3 vddq power io vdd (3.3 v) 58 t4 vss power gnd (0 v) 59 v1 d9 i/o data a9 60 w2 d6 i/o data a6 61 w1 back / bsreq o bus acknowledge/ bus request
section 1 overview SH7750, SH7750s, SH7750r group page 44 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 62 y1 breq / bsack i bus request/ bus acknowledge 63 y2 d8 i/o data a8 64 v3 d7 i/o data a7 65 w3 cke o clock output enable cke 66 v5 vddq power io vdd (3.3 v) 67 u5 vss power gnd (0 v) 68 y3 we5 / cas5 / dqm5 o d47?d40 select signal we5 cas5 dqm5 69 v4 we4 / cas4 / dqm4 o d39?d32 select signal we4 cas4 dqm4 70 w4 we1 / cas1 / dqm1 o d15?d8 select signal we1 cas1 dqm1 we1 71 y4 we0 / cas0 / dqm0 o d7?d0 select signal we0 cas0 dqm0 72 w5 a17 o address 73 v6 vddq power io vdd (3.3 v) 74 u6 vss power gnd (0 v) 75 y5 a16 o address 76 w6 a15 o address 77 v7 vdd power internal vdd 78 u7 vss power gnd (0 v) 79 y6 a14 o address 80 w7 a13 o address 81 v8 vddq power io vdd (3.3 v) 82 u8 vss power gnd (0 v) 83 u4 vss power gnd (0 v) 84 y7 a12 o address 85 w8 a11 o address 86 y8 a10 o address 87 v9 vddq power io vdd (3.3 v) 88 u9 vss power gnd (0 v) 89 w9 a9 o address 90 y9 a8 o address
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 45 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 91 w10 a7 o address 92 y10 ckio o clock output ckio ckio ckio 93 v10 vddq power io vdd (3.3 v) 94 u10 vss power gnd (0 v) 95 v11 ckio2 o ckio * ckio ckio ckio 96 w11 a6 o address 97 y11 a5 o address 98 w12 a4 o address 99 v12 vddq power io vdd (3.3 v) 100 u12 vss power gnd (0 v) 101 y12 a3 o address 102 w13 a2 o address 103 y13 drak1 o dmac1 request acknowledge 104 w14 drak0 o dmac0 request acknowledge 105 v13 vddq power io vdd (3.3 v) 106 u13 vss power gnd (0 v) 107 y14 cs3 o chip select 3 cs3 ( cs3 ) cs3 cs3 108 w15 cs2 o chip select 2 cs2 ( cs2 ) cs2 cs2 109 v14 vdd power internal vdd 110 u14 vss power gnd (0 v) 111 y15 ras o ras ras ras 112 w16 rd / cass / frame o read/ cas / frame oe cas oe frame 113 v15 vddq power io vdd (3.3 v) 114 u15 vss power gnd (0 v) 115 y16 rd/ wr o read/write rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 116 v17 we2 / cas2 / dqm2/ iciord o d23?d16 select signal we2 cas2 dqm2 iciord 117 w17 we3 / cas3 / dqm3/ iciowr o d31?d24 select signal we3 cas3 dqm3 iciowr 118 y17 we6 / cas6 / dqm6 o d55?d48 select signal we6 cas6 dqm6
section 1 overview SH7750, SH7750s, SH7750r group page 46 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 119 v16 vddq power io vdd (3.3 v) 120 u16 vss power gnd (0 v) 121 v18 we7 / cas7 / dqm7/ reg o d63?d56 select signal we7 cas7 dqm7 reg 122 w18 d23 i/o data a23 123 y18 d24 i/o data a24 124 y19 d22 i/o data a22 125 y20 rxd i sci data input 126 w19 dreq0 i request from dmac0 127 w20 dreq1 i request from dmac1 128 v19 d25 i/o data a25 129 t18 vddq power io vdd (3.3 v) 130 t17 vss power gnd (0 v) 131 v20 d21 i/o data a21 132 u18 d26 i/o data 133 u19 d20 i/o data a20 134 u20 d27 i/o data 135 r18 vddq power io vdd (3.3 v) 136 r17 vss power gnd (0 v) 137 t19 d19 i/o data a19 138 t20 d28 i/o data 139 p18 vdd power internal vdd 140 p17 vss power gnd (0 v) 141 r19 d18 i/o data a18 142 r20 d29 i/o data 143 n18 vddq power io vdd (3.3 v) 144 n17 vss power gnd (0 v) 145 p19 d17 i/o data a17 146 p20 d30 i/o data 147 n19 d16 i/o data a16 148 n20 d31 i/o data 149 m18 vddq power io vdd (3.3 v)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 47 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 150 m17 vss power gnd (0 v) 151 m19 d55 i/o data 152 m20 d56 i/o data 153 l19 d54 i/o data 154 l20 d57 i/o data 155 l18 vddq power io vdd (3.3 v) 156 l17 vss power gnd (0 v) 157 k18 d53 i/o data 158 k19 d58 i/o data 159 k20 d52 i/o data 160 j19 d59 i/o data 161 j18 vddq power io vdd (3.3 v) 162 k17 vss power gnd (0 v) 163 j20 d51 i/o data/port (port) (port) (port) (port) (port) 164 h19 d60 i/o data 165 h20 d50 i/o data/port (port) (port) (port) (port) (port) 166 g19 d61 i/o data accsize0 167 h18 vddq power io vdd (3.3 v) 168 j17 vss power gnd (0 v) 169 g20 d49 i/o data/port (port) (port) (port) (port) (port) 170 f19 d62 i/o data accsize1 171 g18 vdd power internal vdd 172 g17 vss power gnd (0 v) 173 f20 d48 i/o data/port (port) (port) (port) (port) (port) 174 e18 d63 i/o data accsize2 175 f18 vddq power io vdd (3.3 v) 176 f17 vss power gnd (0 v) 177 e17 vss power gnd (0 v) 178 e19 rd/ wr2 o rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr rd/ wr 179 e20 md0/sck i/o mode/sci clock md0 sck sck sck sck sck 180 d18 md1/txd2 i/o mode/scif data output md1 txd2 txd2 txd2 txd2 txd2 181 d19 md2/rxd2 i mode/scif data input md2 rxd2 rxd2 rxd2 rxd2 rxd2
section 1 overview SH7750, SH7750s, SH7750r group page 48 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 182 d20 irl0 i interrupt 0 183 c19 irl1 i interrupt 1 184 c20 irl2 i interrupt 2 185 b19 irl3 i interrupt 3 186 b20 nmi i nonmaskable interrupt 187 a20 xtal2 o rtc crystal resonator pin 188 a19 extal2 i rtc crystal resonator pin 189 b18 vss-rtc power rtc gnd (0 v) 190 a18 vdd-rtc power rtc vdd (3.3 v) 191 d17 ca i hardware standby 192 c17 vddq power io vdd (3.3 v) 193 c18 vss-rtc power rtc gnd (0 v) 194 b17 cts2 i/o scif data control ( cts ) 195 a17 tclk i/o rtc/tmu clock 196 c16 md8/ rts2 i/o mode/scif data control ( rts ) md8 rts2 rts2 rts2 rts2 rts2 197 c15 vddq power io vdd (3.3 v) 198 d15 vss power gnd (0 v) 199 b16 md7/txd i/o mode/sci1 data output md7 txd txd txd txd txd 200 a16 sck2/ mreset i scif clock/ manual reset mreset sck2 sck2 sck2 sck2 sck2 201 c14 vdd power internal vdd 202 d14 vss power gnd (0 v) 203 b15 a18 o address 204 a15 a19 o address 205 c13 vddq power io vdd (3.3 v) 206 d13 vss power gnd (0 v) 207 b14 a20 o address 208 a14 a21 o address 209 b13 a22 o address
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 49 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 210 a13 a23 o address 211 c12 vddq power io vdd (3.3 v) 212 d12 vss power gnd (0 v) 213 b12 a24 o address 214 a12 a25 o address 215 b11 md3/ ce2a i/o mode/ pcmcia-ce md3 ce2a 216 a11 md4/ ce2b i/o mode/ pcmcia-ce md4 ce2b 217 c11 vddq power io vdd (3.3 v) 218 d11 vss power gnd (0 v) 219 c10 md5/ ras2 i/o mode/ ras (dram) md5 ras2 220 b10 dack0 o dmac0 bus acknowledge 221 a10 dack1 o dmac1 acknowledge 222 b9 a0 o address 223 c8 vddq power io vdd (3.3 v) 224 d8 vss power gnd (0 v) 225 a9 a1 o address 226 b8 status0 o status 227 a8 status1 o status 228 b7 md6/ iois16 i mode/ iois16 (pcmcia) md6 iois16 229 c9 vddq power io vdd (3.3 v) 230 d9 vss power gnd (0 v) 231 a7 asebrk / brkack i/o pin break/ acknowledge (h-udi) 232 c6 tdo o data out (h-udi) 233 c7 vdd power internal vdd 234 d7 vss power gnd (0 v) 235 b6 tms i mode (h-udi) 236 a6 tck i clock (h-udi) 237 c5 tdi i data in (h-udi)
section 1 overview SH7750, SH7750s, SH7750r group page 50 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 238 b5 trst i reset (h-udi) 239 c4 ckio2enb i ckio2, rd2 , rd/ wr2 enable 240 d6 vss power gnd (0 v) 241 a5 vdd-pll2 power pll2 vdd (3.3 v) 242 b4 vss-pll2 power pll2 gnd (0 v) 243 a4 vdd-pll1 power pll1 vdd (3.3 v) 244 c3 vss-pll1 power pll1 gnd (0 v) 245 b3 vdd-cpg power cpg vdd (3.3 v) 246 a3 vss-cpg power cpg gnd (0 v) 247 a2 xtal o crystal resonator 248 a1 extal i external clock/ crystal resonator 249 n4 vss power gnd (0 v) 250 u11 vss power gnd (0 v) 251 u17 vss power gnd (0 v) 252 h17 vss power gnd (0 v) 253 d16 vss power gnd (0 v) 254 d10 vss power gnd (0 v) 255 d5 vss power gnd (0 v) 256 d4 vss power gnd (0 v) 257 h8 vss power gnd (0 v) 258 j8 vss power gnd (0 v) 259 k8 vss power gnd (0 v) 260 l8 vss power gnd (0 v) 261 m8 vss power gnd (0 v) 262 n8 vss power gnd (0 v) 263 n9 vss power gnd (0 v) 264 n10 vss power gnd (0 v) 265 n11 vss power gnd (0 v) 266 n12 vss power gnd (0 v) 267 n13 vss power gnd (0 v) 268 m13 vss power gnd (0 v)
SH7750, SH7750s, SH7750r group section 1 overview r01uh0456ej0702 rev. 7.02 page 51 of 1076 sep 24, 2013 memory interface no. pin no. pin name i/o function reset sram dram sdram pcmcia mpx 269 l13 vss power gnd (0 v) 270 k13 vss power gnd (0 v) 271 j13 vss power gnd (0 v) 272 h13 vss power gnd (0 v) 273 h12 vss power gnd (0 v) 274 h11 vss power gnd (0 v) 275 h10 vss power gnd (0 v) 276 h9 vss power gnd (0 v) 277 j9 vss power gnd (0 v) 278 k9 vss power gnd (0 v) 279 l9 vss power gnd (0 v) 280 m9 vss power gnd (0 v) 281 m10 vss power gnd (0 v) 282 m11 vss power gnd (0 v) 283 m12 vss power gnd (0 v) 284 l12 vss power gnd (0 v) 285 k12 vss power gnd (0 v) 286 j12 vss power gnd (0 v) 287 j11 vss power gnd (0 v) 288 j10 vss power gnd (0 v) 289 k10 vss power gnd (0 v) 290 l10 vss power gnd (0 v) 291 l11 vss power gnd (0 v) 292 k11 vss power gnd (0 v) legend: i: input o: output i/o: input/output power: power supply notes: supply power to all power pins. power must be supplied to vdd-pll1/2 and vss-pll1/2 regardless of whether or not the on-chip pll circuits are used. power must be supplied to vdd-cpg and vs s-cpg regardless of whether or not the on- chip crystal oscillation circuit is used.
section 1 overview SH7750, SH7750s, SH7750r group page 52 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 power must be supplied to vdd-rtc and vs s-rtc regardless of w hether or not the on- chip rtc is used. nc pins must be left completely open, and not connected to a power supply, gnd, etc. * ckio2 is not connected to pll2.
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 53 of 1076 sep 24, 2013 section 2 programming model 2.1 data formats the data formats handled by the sh-4 are shown in figure 2.1. byte (8 bits) word (16 bits) lon g word (32 bits) sin g le-precision floatin g -point (32 bits) double-precision floatin g -point (64 bits) 0 7 0 15 0 31 0 31 30 22 fraction exp s 0 63 62 51 exp s fraction figure 2.1 data formats
section 2 programming model SH7750, SH7750s, SH7750r group page 54 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 2.2 register configuration 2.2.1 privileged mode and banks processor modes: the sh-4 has two processor modes, user mode and privileged mode. the sh-4 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. there are fo ur kinds of registers?general registers, system registers, control registers, and floating- point registers?and the registers th at can be accessed differ in the two processor modes. general registers: there are 16 general registers, designated r0 to r15. general registers r0 to r7 are banked registers which are switched by a processor mode change. in privileged mode, the register bank bit (rb) in the status register (sr) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (ldc) and store control register (stc) instructions. when the rb bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers r0_bank1 to r7_bank1 and non-banked general registers r8 to r15 can be accessed as general registers r0 to r15. in this case, the eight registers comprising bank 0 general registers r0_bank0 to r7_bank0 are accessed by the ldc/ stc instructions. when the rb bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers r0_bank0 to r7_bank0 and non-banked general registers r8 to r15 can be accessed as general registers r0 to r15. in this case, the eight registers comprising bank 1 general registers r0_bank1 to r7_bank1 are accessed by the ldc/stc instructions. in user mode, the 16 registers comprising bank 0 general registers r0_bank0 to r7_bank0 and non-banked general registers r8 to r15 can be accessed as general registers r0 to r15. the eight registers comprising bank 1 general registers r0_bank1 to r7_bank1 cannot be accessed. control registers: control registers comprise the global ba se register (gbr) an d status register (sr), which can be accessed in both processor modes, and the saved status register (ssr), saved program counter (spc), vector base register (vbr), saved general register 15 (sgr), and debug base register (dbr), which can only be accessed in privileged mode. some bits of the status register (such as the rb bit) can only be accessed in privileged mode. system registers: system registers comprise the multiply-and-accumulate registers (mach/macl), the procedure register (pr), the program counter (pc), the floating-point status/control register (fpscr), and the floating- point communication regist er (fpul). access to these registers does not depend on the processor mode.
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 55 of 1076 sep 24, 2013 floating-point registers: there are thirty-two floating-point registers, fr0?fr15 and xf0? xf15. fr0?fr15 and xf0?xf15 can be assigned to either of two banks (fpr0_bank0? fpr15_bank0 or fpr0_bank1?fpr15_bank1). fr0?fr15 can be used as the eight registers dr0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers fv0/4/8/12 (register vectors), while xf0? xf15 can be used as the eight registers xd0/2/4/6/8/10/12/14 (register pairs) or register matrix xmtrx. register values after a reset are shown in table 2.1. table 2.1 initial register values type registers initial value * general registers r0_bank0?r7_bank0, r0_bank1?r7_bank1, r8?r15 undefined sr md bit = 1, rb bit = 1, bl bit = 1, fd bit = 0, imask = 1111 (h'f), reserved bits = 0, others undefined gbr, ssr, spc, sgr, dbr undefined control registers vbr h'00000000 mach, macl, pr, fpul undefined pc h'a0000000 system registers fpscr h'00040001 floating-point registers fr0?fr15, xf0?xf15 undefined note: * initialized by a power-on reset and manual reset. the register configuration in each pr ocessor is shown in figure 2.2. switching between user mode and privileged mode is controlled by the processor mode bit (md) in the status register.
section 2 programming model SH7750, SH7750s, SH7750r group page 56 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 31 0 r0 _ bank0 * 1 * 2 r1 _ bank0 * 2 r2 _ bank0 * 2 r3 _ bank0 * 2 r4 _ bank0 * 2 r5 _ bank0 * 2 r6 _ bank0 * 2 r7 _ bank0 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr gbr mach macl pr pc (a) re g ister confi g uration in user mode 31 0 r0 _ bank1 * 1 * 3 r1 _ bank1 * 3 r2 _ bank1 * 3 r3 _ bank1 * 3 r4 _ bank1 * 3 r5 _ bank1 * 3 r6 _ bank1 * 3 r7 _ bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 r0 _ bank0 * 1 * 4 r1 _ bank0 * 4 r2 _ bank0 * 4 r3 _ bank0 * 4 r4 _ bank0 * 4 r5 _ bank0 * 4 r6 _ bank0 * 4 r7 _ bank0 * 4 (b) re g ister confi g uration in privile g ed mode (rb = 1) gbr mach macl vbr pr sr ssr pc spc 31 0 r0 _ bank1 * 1 * 3 r1 _ bank1 * 3 r2 _ bank1 * 3 r3 _ bank1 * 3 r4 _ bank1 * 3 r5 _ bank1 * 3 r6 _ bank1 * 3 r7 _ bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 r0 _ bank0 * 1 * 4 r1 _ bank0 * 4 r2 _ bank0 * 4 r3 _ bank0 * 4 r4 _ bank0 * 4 r5 _ bank0 * 4 r6 _ bank0 * 4 r7 _ bank0 * 4 (c) re g ister confi g uration in privile g ed mode (rb = 0) gbr mach macl vbr pr sr ssr pc spc sgr dbr sgr dbr notes: 1. the r0 re g ister is used as the index re g ister in indexed re g ister-indirect addressin g mode and indexed gbr indirect addressin g mode. 2. banked re g isters 3. banked re g isters accessed as g eneral re g isters when the rb bit is set to 1 in the sr re g ister. accessed only by ldc/stc instructions when the rb bit is cleared to 0. 4. banked re g isters accessed as g eneral re g isters when the rb bit is cleared to 0 in the sr re g ister. accessed only by ldc/stc instructions when the rb bit is set to 1. figure 2.2 cpu register configuration in each processor mode
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 57 of 1076 sep 24, 2013 2.2.2 general registers figure 2.3 shows the relationship between the processor modes and general registers. the sh-4 has twenty-four 32-bit general registers (r0_bank0?r7_bank0, r0_bank1?r7_bank1, and r8?r15). however, only 16 of these can be accessed as general registers r0?r15 in one processor mode. the sh-4 has two processor modes, user mode and privileged mode, in which r0?r7 are assigned as shown below. ? r0_bank0?r7_bank0 in user mode (sr.md = 0), r0?r7 are always assigned to r0_bank0?r7_bank0. in privileged mode (sr.md = 1), r0?r7 are assigned to r0_bank0?r7_bank0 only when sr.rb = 0. ? r0_bank1?r7_bank1 in user mode, r0_bank1?r7_bank1 cannot be accessed. in privileged mode, r0?r7 are assigned to r0_bank1?r7_bank1 only when sr.rb = 1.
section 2 programming model SH7750, SH7750s, SH7750r group page 58 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 sr.md = 0 or (sr.md = 1, sr.rb = 0) r0_bank0 r1_bank0 r2_bank0 r3_bank0 r4_bank0 r5_bank0 r6_bank0 r7_bank0 r0_bank0 r1_bank0 r2_bank0 r3_bank0 r4_bank0 r5_bank0 r6_bank0 r7_bank0 r0_bank1 r1_bank1 r2_bank1 r3_bank1 r4_bank1 r5_bank1 r6_bank1 r7_bank1 r0_bank1 r1_bank1 r2_bank1 r3_bank1 r4_bank1 r5_bank1 r6_bank1 r7_bank1 r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r8 r9 r10 r11 r12 r13 r14 r15 r8 r9 r10 r11 r12 r13 r14 r15 (sr.md = 1, sr.rb = 1) figure 2.3 general registers programming note: as the user's r0?r7 are assigned to r0_bank0?r7_bank0, and after an exception or interrupt r0?r7 are assigned to r0_bank1?r7_bank1, it is not necessary for the interrupt handler to save and restore the user's r0?r7 (r0_bank0?r7_bank0). after a reset, the values of r0_bank0?r7_bank0, r0_bank1?r7_bank1, and r8?r15 are undefined.
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 59 of 1076 sep 24, 2013 2.2.3 floating-point registers figure 2.4 shows the floating-point registers. there are thirty-two 32-bit floating-point registers, divided into two banks (fpr0_bank0?fpr15_bank0 and fpr0_bank1?fpr15_bank1). these 32 registers are referenced as fr0?fr15, dr0/2/4/6/8/10/12/14, fv0/4/8/12, xf0?xf15, xd0/2/4/6/8/10/12/14, or xmtrx. the correspondence between fprn_banki and the reference name is determined by the fr bit in fpscr (see figure 2.4). ? floating-point registers, fprn_banki (32 registers) fpr0_bank0, fpr1_bank0, fpr2_b ank0, fpr3_bank0, fpr4_bank0, fpr5_bank0, fpr6_bank0, fpr7_b ank0, fpr8_bank0, fpr9_bank0, fpr10_bank0, fpr11_bank0, fpr12_ba nk0, fpr13_bank0, fpr14_bank0, fpr15_bank0 fpr0_bank1, fpr1_bank1, fpr2_b ank1, fpr3_bank1, fpr4_bank1, fpr5_bank1, fpr6_bank1, fpr7_b ank1, fpr8_bank1, fpr9_bank1, fpr10_bank1, fpr11_bank1, fpr12_ba nk1, fpr13_bank1, fpr14_bank1, fpr15_bank1 ? single-precision floating-point registers, fri (16 registers) when fpscr.fr = 0, fr0?fr15 are assigned to fpr0_bank0?fpr15_bank0. when fpscr.fr = 1, fr0?fr15 are assigned to fpr0_bank1?fpr15_bank1. ? double-precision floating-point registers or single-precision floating-point register pairs, dri (8 registers): a dr register comprises two fr registers. dr0 = {fr0, fr1}, dr2 = {fr2, fr3}, dr4 = {fr4, fr5}, dr6 = {fr6, fr7}, dr8 = {fr8, fr9}, dr10 = {fr10, fr11}, dr12 = {fr12, fr13}, dr14 = {fr14, fr15} ? single-precision floating-point vector registers, fvi (4 registers): an fv register comprises four fr registers fv0 = {fr0, fr1, fr2, fr3}, fv4 = {fr4, fr5, fr6, fr7}, fv8 = {fr8, fr9, fr10, fr11}, fv 12 = {fr12, fr13, fr14, fr15} ? single-precision floating-point extended registers, xfi (16 registers) when fpscr.fr = 0, xf0?xf15 are a ssigned to fpr0_bank1?fpr15_bank1. when fpscr.fr = 1, xf0?xf15 are a ssigned to fpr0_bank0?fpr15_bank0.
section 2 programming model SH7750, SH7750s, SH7750r group page 60 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? single-precision floating-point extended register pairs, xdi (8 registers): an xd register comprises two xf registers xd0 = {xf0, xf1}, xd2 = {xf2, xf3}, xd4 = {xf4, xf5}, xd6 = {xf6, xf7}, xd8 = {xf8, xf9}, xd10 = {xf10, xf11}, xd12 = {xf12, xf13}, xd14 = {xf14, xf15} ? single-precision floating-point extended register matrix, xmtrx: xmtrx comprises all 16 xf registers xmtrx = xf0 xf4 xf8 xf12 xf1 xf5 xf9 xf13 xf2 xf6 xf10 xf14 xf3 xf7 xf11 xf15
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 61 of 1076 sep 24, 2013 fpr0_bank0 fpr1_bank0 fpr2_bank0 fpr3_bank0 fpr4_bank0 fpr5_bank0 fpr6_bank0 fpr7_bank0 fpr8_bank0 fpr9_bank0 fpr10_bank0 fpr11_bank0 fpr12_bank0 fpr13_bank0 fpr14_bank0 fpr15_bank0 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpr0_bank1 fpr1_bank1 fpr2_bank1 fpr3_bank1 fpr4_bank1 fpr5_bank1 fpr6_bank1 fpr7_bank1 fpr8_bank1 fpr9_bank1 fpr10_bank1 fpr11_bank1 fpr12_bank1 fpr13_bank1 fpr14_bank1 fpr15_bank1 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpscr.fr = 0 fpscr.fr = 1 figure 2.4 floating-point registers programming note: after a reset, the values of fpr0_bank0?fpr15_bank0 and fpr0_bank1?fpr15_bank1 are undefined.
section 2 programming model SH7750, SH7750s, SH7750r group page 62 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 2.2.4 control registers status register, sr (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00xx 1111 00xx (x: undefined)) 31 30 29 28 27 16 15 14 10 9 8 7 4 3 2 1 0 ? md rb bl ? fd ? m q imask ? s t note: ?: reserved. these bits are always read as 0, and should only be written with 0. ? md: processor mode md = 0: user mode (some instructions canno t be executed, and some resources cannot be accessed) md = 1: privileged mode ? rb: general register bank specifier in privileg ed mode (set to 1 by a reset, exception, or interrupt) rb = 0: r0_bank0?r7_bank0 are accessed as general registers r0?r7. (r0_bank1? r7_bank1 can be accessed using ldc/st c r0_bank?r7_bank instructions.) rb = 1: r0_bank1?r7_bank1 are accessed as general registers r0?r7. (r0_bank0? r7_bank0 can be accessed using ldc/st c r0_bank?r7_bank instructions.) ? bl: exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) bl = 1: interrupt requests are masked. if a general exception other than a user break occurs while bl = 1, the processor switches to the reset state. ? fd: fpu disable bit (cleared to 0 by a reset) fd = 1: an fpu instruction causes a general fpu disable exception, and if the fpu instruction is in a delay slot, a slot fpu disable exception is generated. (fpu instructions: h'f*** instructions, ldc(.l)/sts(.l) instructions for fpul/fpscr) ? m, q: used by the div0s, div0u, and div1 instructions. ? imask: interrupt mask level external interrupts of a same level or a lower level than imask are masked. ? s: specifies a saturation opera tion for a mac instruction. ? t: true/false condition or carry/borrow bit
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 63 of 1076 sep 24, 2013 saved status register, ssr (32 bits, privil ege protection, initia l value undefined): the current contents of sr are saved to ssr in the event of an exception or interrupt. saved program counter, spc (32 bits, privilege protection, initial value undefined): the address of an instruction at which an interrupt or exception occurs is saved to spc. global base register, gbr (32 bits, initial value undefined): gbr is referenced as the base address in a gbr-referencing mov instruction. vector base register, vbr (32 bits, privilege protection, initial value = h'0000 0000): vbr is referenced as the branch destination base address in the event of an exception or interrupt. for details, see section 5, exceptions. saved general register 15, sgr (32 bits, priv ilege protection, initial value undefined): the contents of r15 are saved to sgr in the event of an exception or interrupt. debug base register, dbr (32 bits, privile ge protection, initial value undefined): when the user break debug function is enabled (brcr.ubde = 1), dbr is referenced as the user break handler branch destination address instead of vbr. 2.2.5 system registers multiply-and-accumulate register high, ma ch (32 bits, initial value undefined) multiply-and-accumulate re gister low, macl (32 bits, initial value undefined) mach/macl is used for the added value in a ma c instruction, and to store a mac instruction or mul operation result. procedure register, pr (32 bits, initial value undefined): the return address is stored in pr in a subroutine call using a bsr, bsrf, or jsr instruction, and pr is referenced by the subroutine return instruction (rts). program counter, pc (32 bits, initial value = h'a000 0000): pc indicates the instruction fetch address.
section 2 programming model SH7750, SH7750s, SH7750r group page 64 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 floating-point status/control register, fpscr (32 bits, initial value = h'0004 0001) 31 22 21 20 19 18 17 12 11 7 6 2 1 0 ? fr sz pr dn cause enable flag rm note: ?: reserved. these bits are always read as 0, and should only be written with 0. ? fr: floating-point register bank fr = 0: fpr0_bank0?fpr15_bank0 are assigned to fr0?fr15; fpr0_bank1? fpr15_bank1 are assigned to xf0?xf15. fr = 1: fpr0_bank0?fpr15_bank0 are assigned to xf0?xf15; fpr0_bank1? fpr15_bank1 are assigned to fr0?fr15. ? sz: transfer size mode sz = 0: the data size of the fmov instruction is 32 bits. sz = 1: the data size of the fmov instruc tion is a 32-bit register pair (64 bits). ? pr: precision mode pr = 0: floating-point instructions are executed as single-precision operations. pr = 1: floating-point instructions are executed as double-precision operations (the result of instructions for which double-precision is not supported is undefined). do not set sz and pr to 1 simultaneously; this setting is reserved. [sz, pr = 11]: reserved (fpu operation instruction is undefined.) ? dn: denormalization mode dn = 0: a denormalized number is treated as such. dn = 1: a denormalized nu mber is treated as zero. ? cause: fpu exception cause field ? enable: fpu exception enable field ? flag: fpu exception flag field fpu error (e) invalid operation (v) division by zero (z) overflow (o) underflow (u) inexact (i) cause fpu exception cause field bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 enable fpu exception enable field none bit 11 bit 10 bit 9 bit 8 bit 7 flag fpu exception flag field none bit 6 bit 5 bit 4 bit 3 bit 2
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 65 of 1076 sep 24, 2013 when an fpu operation instruction is executed, the fpu exception cause field is cleared to zero first. when the next fpu exception is occured, the corresponding bits in the fpu exception cause field and fpu excep tion flag field are set to 1. the fpu exception flag field holds the status of the exception gene rated after the field was last cleared. ? rm: rounding mode rm = 00: round to nearest rm = 01: round to zero rm = 10: reserved rm = 11: reserved ? bits 22 to 31: reserved floating-point communication register, fp ul (32 bits, initial value undefined): data transfer between fpu registers and cpu registers is carried out via the fpul register. programming note: when sz = 1 and big endian mode is selected, fmov can be used for double-precision floating-point load or store operations. in little endian mode, two 32-bit data size moves must be executed, with sz = 0, to load or store a double-precision floating-point number. 2.3 memory-mapped registers appendix a, address list shows the control registers mapped to memory. the control registers are double-mapped to the following two memory areas. all registers have two addresses. h'1c00 0000?h'1fff ffff h'fc00 0000?h'ffff ffff these two areas are used as follows. ? h'1c00 0000?h'1fff ffff this area must be accessed using the address tr anslation function of the mmu. setting the page number of this area to the corresponding filed of the tlb enables access to a memory- mapped register. accessing this area without using the address translation function of the mmu is not guaranteed. ? h'fc00 0000?h'ffff ffff access to area h'ff00 0000?h'ffff ffff in user mode will cause an address error. memory- mapped registers can be referenced in user mode by means of access that involves address translation.
section 2 programming model SH7750, SH7750s, SH7750r group page 66 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 note: do not access undefined locations in e ither area the operation of an access to an undefined location is undefined. also, memo ry-mapped registers must be accessed using a fixed data size. the operatio n of an access using an invali d data size is undefined. 2.4 data format in registers register operands are always longwords (32 bits). when a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 lon g word 2.5 data formats in memory memory data formats are classifi ed into bytes, words, and longwords. memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. a memory operand less than 32 bits in length is sign-extended before being loaded into a register. a word operand must be accessed starting from a word boundary (eve n address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). an address error will result if this rule is not observed. a byte operand can be accessed from any address. big endian or little endian byte order can be selected for the data format. the endian should be set with the md5 external pin in a power-on reset. big endian is selected when the md5 pin is low, and little endian when high. the endian cannot be changed dynamically. bit positions are numbered left to right from most-significant to least-significant. thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit an d the rightmost bit, bit 0, is the least significant bit. the data format in memory is shown in figure 2.5.
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 67 of 1076 sep 24, 2013 address a a 70707070 31 15 0 15 0 31 0 15 0 31 0 23 15 7 0 a + 1 a + 2 a + 3 byte 0 word 0 lon g word word 1 byte 1 byte 2 byte 3 a + 11 70707070 31 15 0 23 15 7 0 a + 10 a + 9 a + 8 byte 3 word 1 lon g word word 0 byte 2 byte 1 byte 0 address a + 4 address a + 8 address a + 8 address a + 4 address a bi g endian little endian figure 2.5 data formats in memory note: the sh-4 does not support endian conversion for the 64-bit data format. therefore, if double-precision floatin g-point format (64-bit) access is pe rformed in little endian mode, the upper and lower 32 bits will be reversed. 2.6 processor states the sh-4 has five processor states: the reset stat e, exception-handling stat e, bus-released state, program execution state, and power-down state. reset state: in this state the cpu is reset. th e reset state is entered when the reset pin goes low. the cpu enters the po wer-on reset state if the mreset pin is high, and the manual reset state if the mreset pin is low. for more information on resets, see section 5, exceptions. in the power-on reset state, th e internal state of the cpu and the on-chip peripheral module registers are initialized. in the manual reset state, the internal state of the cpu and registers of on- chip peripheral modules other than the bus state controller (bsc) are initialized. since the bus state controller (bsc) is not initialized in the manual reset state, refreshing operations continue. refer to the register configurations in the relevant sections for further details. exception-handling state: this is a transient state during wh ich the cpu's processor state flow is altered by a reset, general exception, or interrupt exception handling source. in the case of a reset, the cpu branches to addr ess h'a000 0000 and star ts executing the user- coded exception handling program. in the case of a general exception or interrupt, the program counter (pc) contents are saved in the saved program counter (spc), the status register (sr) contents are saved in the saved status register (ssr), and the r15 contents are saved in saved general register 15 (sgr). the cpu branches to the start address of the user-coded exception service routine found from the sum of the
section 2 programming model SH7750, SH7750s, SH7750r group page 68 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 contents of the vector base address and the vect or offset. see section 5, exceptions, for more information on resets, general exceptions, and interrupts. program execution state: in this state the cpu executes pr ogram instructions in sequence. power-down state: in the power-down state, cpu operation halts and power consumption is reduced. the power-down state is entered by ex ecuting a sleep instructio n. there are two modes in the power-down state: sleep mode and standby mode. for details, see section 9, power-down modes. bus-released state: in this state the cpu has released th e bus to a device that requested it. transitions between the states are shown in figure 2.6. reset = 0, mreset = 1 reset = 1, mreset = 0 reset = 1, mreset = 1 power-on reset state manual reset state program execution state bus-released state exception-handling state interrupt interrupt end of exception transition processing bus request clearance exception interrupt bus request clearance bus request bus request clearance sleep instruction with stby bit cleared sleep instruction with stby bit set from any state when reset = 0 and mreset = 1 reset = 0 and mreset = 0 reset state power-down state bus request bus request standby mode sleep mode figure 2.6 processor state transitions
SH7750, SH7750s, SH7750r group section 2 programming model r01uh0456ej0702 rev. 7.02 page 69 of 1076 sep 24, 2013 2.7 processor modes there are two processor modes: user mode and privileged mode. the processor mode is determined by the processor mode bit (md) in th e status register (sr). user mode is selected when the md bit is cleared to 0, and privileged mode when the md bit is set to 1. when the reset state or exception state is entered, the md bit is set to 1. there ar e certain registers and bits which can only be accessed in privileged mode.
section 2 programming model SH7750, SH7750s, SH7750r group page 70 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 71 of 1076 sep 24, 2013 section 3 memory management unit (mmu) 3.1 overview 3.1.1 features the sh-4 can handle 29-bit exte rnal memory space from an 8-bi t address space identifier and 32- bit logical (virtual) address space. address translation from virtua l address to physical address is performed using the memory management unit (mmu) built into the sh-4. the mmu performs high-speed address translation by caching user-cr eated address translation table information in an address translation buffer (translation lookaside buffer: tlb). the sh-4 has four instruction tlb (itlb) entries and 64 unified tlb (utlb) entries. utlb copies are stored in the itlb by hardware. a paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 mbyte). it is possible to set the virtual address space access right and implement storage protection independently for privileged mode and user mode. 3.1.2 role of the mmu the mmu was conceived as a means of making ef ficient use of physical memory. as shown in figure 3.1, when a process is smaller in size than the physical memory, th e entire process can be mapped onto physical memory, but if the process in creases in size to the po int where it does not fit into physical memory, it becomes necessary to divi de the process into smaller parts, and map the parts requiring execution onto physical memory on an ad hoc basis ((1)). having this mapping onto physical memory executed consciously by th e process itself imposes a heavy burden on the process. the virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2)). with a vi rtual memory system, th e size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the mmu. the mmu is normally managed by the os, and physical memory switching is carried out so as to enable the virtual memory required by a task to be mapped smoothly onto physical memory. physical memory switching is performed via secondary storage, etc. the virtual memory system that cam e into being in this way works to best effect in a time sharing system (tss) that allows a number of processes to run simultaneously ((3)). running a number of processes in a tss did not increase efficiency sin ce each process had to take account of physical memory mapping. efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4)). in this system, virtual memory is allocated to each process. the task of the mmu is to map a number of virtual memo ry areas onto physical me mory in an efficient
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 72 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 manner. it is also provided with memory protection functions to prevent a process from inadvertently accessing anothe r process's physical memory. when address translation from virtual memory to physical memory is performed using the mmu, it may happen that the translation information has not been recorded in the mmu, or the virtual memory of a different process is accessed by mist ake. in such cases, the mmu will generate an exception, change the physical memory mappi ng, and record the new address translation information. although the functions of the mmu could be implemented by software alone, having address translation performed by software each time a pr ocess accessed physical memory would be very inefficient. for this reason, a buffer for address translation (the translation lookaside buffer: tlb) is provided in hardware, and frequently used address translation information is placed here. the tlb can be described as a cache for address transl ation information. howeve r, unlike a cache, if address translation fails?that is, if an exception occurs?switching of the address translation information is normally performed by software. thus memory management can be performed in a flexible manner by software. there are two methods by which the mmu can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. with the paging method, the unit of translation is a fixed-size address space called a page (usu ally from 1 to 64 kbytes in size). in the following descriptions, the address space in virtual memory in the sh-4 is referred to as virtual address space, and the ad dress space in physical memory as physical address space.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 73 of 1076 sep 24, 2013 (2) process 1 process 1 physical memory process 1 process 2 process 3 virtual memory process 1 process 1 process 2 process 3 mmu mmu (4) (3) (1) physical memory physical memory physical memory physical memory virtual memory figure 3.1 role of the mmu
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 74 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3.1.3 register configuration the mmu registers are shown in table 3.1. table 3.1 mmu registers name abbrevia- tion r/w initial value * 1 p4 address * 2 area 7 address * 2 acces s size page table entry high register pteh r/w undefined h'ff00 0000 h'1f00 0000 32 page table entry low register ptel r/w undefined h'ff00 0004 h'1f00 0004 32 page table entry assistance register ptea r/w undefined h 'ff00 0034 h'1f00 0034 32 translation table base register ttb r/w undefined h 'ff00 0008 h'1f00 0008 32 tlb exception address register tea r/w undefined h 'ff00 000c h'1f00 000c 32 mmu control register mmucr r/w h'0000 0000 h'ff00 0010 h'1f00 0010 32 notes: 1. the initial value is the valu e after a power-on reset or manual reset. 2. this is the address when using the vi rtual/physical address space p4 area. when making an access from physical address space area 7 using the tlb, the upper 3 bits of the address are ignored. 3.1.4 caution operation is not guaranteed if an area designated as a reserved area in this manual is accessed.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 75 of 1076 sep 24, 2013 3.2 register descriptions there are six mmu-related registers. 31 10 9 87 0 vpn ppn ? ? asid 1. pteh 31 30 29 28 10 9 8 76 5 4 3 2 1 0 ? ? ? ? v sz pr sz c d sh wt 2. ptel 31 4 32 0 tc sa 3. ptea 31 0 ttb 4. ttb 31 virtual address at which mmu exception or address error occurred 5. tea 31 26 24 23 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0 lrui ? ? ? ? urc sqmd sv?????ti?at 6. mmucr note: ? indicates a reserved bit: the write value must be 0, and a read will return 0. urb 25 figure 3.2 mmu-related registers
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 76 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1. page table entry high register (pteh): longword access to pteh can be performed from h'ff00 0000 in the p4 area and h'1f00 0000 in area 7. pteh consists of the virtual page number (vpn) and address space identifier (asid). when an mmu exception or address error exception occurs, the vpn of the virtual ad dress at which the exception occu rred is set in the vpn field by hardware. vpn varies according to the page size, but the vpn set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. vpn setting can also be carried out by soft ware. the number of the currently executing process is set in the asid field by software. asid is not updated by hardware. vpn and asid are recorded in the utlb by means of th e ldltb instruction. a branch to the p0, p3, or u0 area which uses th e updated asid after the asid field in pteh is rewritten should be made at least 6 instructions after the pteh update instruction. 2. page table entr y low register (ptel): longword access to ptel can be performed from h'ff00 0004 in the p4 area and h'1f00 0004 in area 7. ptel is used to hold the physical page number and page management information to be recorded in the utlb by means of the ldtlb instruction. the contents of this register are not changed unless a software directive is issued. 3. page table entry assistance register (ptea): longword access to ptea can be performed from h'ff00 0034 in the p4 area and h'1f00 0034 in area 7. ptel is used to store assistance bits for pcmcia access to the utlb by means of the ldtlb instruction. when performing access from the cpu in the SH7750s and SH7750r w ith mmucr.at = 0, access is always performed using the values of the sa and tc bits in this re gister. in the SH7750, it is not possible to access a pcmcia interface area with mmucr. at = 0. in this lsi, access to a pcmcia interface area by the dmac is always performed using the dmac's chcrn.ssan, chcrn.dsan, chcrn.stc, and chcrn.dtc values. the contents of this regi ster are not changed unle ss a software directive is issued. 4. translation table base register (ttb): longword access to ttb can be performed from h'ff00 0008 in the p4 area and h'1f00 0008 in area 7. ttb is used, for example, to hold the base address of the cu rrently used page table. the contents of ttb are not changed unless a software directive is issued. this register can be freely used by software. 5. tlb exception address register (tea): longword access to tea can be performed from h'ff00 000c in the p4 area and h'1f00 000c in area 7. after an mmu exception or address error exception occurs, the virtual address at which the exception occurred is set in tea by hardware. the contents of this register can be changed by software. 6. mmu control register (mmucr): mmucr contains the following bits: lrui: least recently used itlb urb: utlb replace boundary
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 77 of 1076 sep 24, 2013 urc: utlb replace counter sqmd: store queue mode bit sv: single virtual mode bit ti: tlb invalidate at: address translation bit longword access to mmucr can be performed fro m h'ff00 0010 in the p4 area and h'1f00 0010 in area 7. the individual bits perform mmu settings as shown below. therefore, mmucr rewriting should be performed by a program in the p1 or p2 area. after mmucr is updated, an instruction that performs data access to the p0, p3 , u0, or store queue area should be located at least four instructions after the mmucr update inst ruction. also, a branch instruction to the p0, p3, or u0 area should be located at least eight instructions after the mmucr update instruction. mmucr contents can be changed by software. the lrui bits and urc bits may also be updated by hardware. ? lrui: least recently used itlb. the lru (least r ecently used) method is used to decide the itlb entry to be replaced in the event of an itlb miss. the entry to be purged from the itlb can be confirmed using the lrui bits. lrui is updated by means of the algorithm shown below. a dash in this table means that updating is not performed. lrui [5] [4] [3] [2] [1] [0] when itlb entry 0 is used 0 0 0 ? ? ? when itlb entry 1 is used 1 ? ? 0 0 ? when itlb entry 2 is used ? 1 ? 1 ? 0 when itlb entry 3 is used ? ? 1 ? 1 1 other than the above ? ? ? ? ? ? when the lrui bit settings are as shown below, the corresponding itlb entry is updated by an itlb miss. an asterisk in this table means ?don't care?.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 78 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 lrui [5] [4] [3] [2] [1] [0] itlb entry 0 is updated 1 1 1 * * * itlb entry 1 is updated 0 * * 1 1 * itlb entry 2 is updated * 0 * 0 * 1 itlb entry 3 is updated * * 0 * 0 0 other than the above setting prohibited ensure that values for which ?setting prohibited? is indicated in the above table are not set at the discretion of software. after a power-on or ma nual reset the lrui bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. ? urb: utlb replace boundary. bits that in dicate the utlb entry boundary at which replacement is to be performed. valid only wh en urb > 0. ? urc: utlb replace counter. random counte r for indicating the u tlb entry for which replacement is to be performed with an ldtlb instruction. urc is in cremented each time the utlb is accessed. when urb > 0, urc is reset to 0 when th e condition urc = urb occurs. also note that, if a value is written to urc by software which results in the condition urc > urb, incrementing is first performed in excess of urb until urc = h'3f. urc is not incremented by an ldtlb instruction. ? sqmd: store queue mode bit. specifies th e right of access to the store queues. 0: user/privileged access possible 1: privileged access possible (address er ror exception in case of user access) ? sv: single virtual mode bit. bit that switches between single virtual memory mode and multiple virtual memory mode. 0: multiple virtual memory mode 1: single virtual memory mode when this bit is changed, ensure that 1 is also written to the ti bit. ? ti: tlb invalidation bit. writing 1 to this bit invalidates (clears to 0) all valid utlb/itlb bits. this bit always returns 0 when read. ? at: address translation enable bit. sp ecifies mmu enabling or disabling. 0: mmu disabled 1: mmu enabled
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 79 of 1076 sep 24, 2013 mmu exceptions are not generated when the at bit is 0. in the case of software that does not use the mmu, therefore, the at bit should be cleared to 0. 3.3 address space 3.3.1 physical address space the sh-4 supports a 32-bit physi cal address space, and can access a 4-gbyte address space. when the mmucr.at bit is cleared to 0 and the mmu is disabled, the ad dress space is this physical address space. the physical address space is divide d into a number of areas, as shown in figure 3.3. the physical address space is permanently mapped onto 29-b it external memory space; this correspondence can be im plemented by ignoring the upper 3 b its of the physical address space addresses. in privileged mode, th e 4-gbyte space from the p0 area to the p4 area can be accessed. in user mode, a 2-gbyte space in the u0 area can be accessed. accessing the p1 to p4 areas (except the store queue area) in user mode will cause an address error. area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external memory space address error address error store queue area user mode privile g ed mode p1 area cacheable p0 area cacheable p2 area non-cacheable p3 area cacheable p4 area non-cacheable u0 area cacheable h'0000 0000 h'8000 0000 h'e000 0000 h'e400 0000 h'ffff ffff h'0000 0000 h'8000 0000 h'ffff ffff h'a000 0000 h'c000 0000 h'e000 0000 figure 3.3 physical address space (mmucr.at = 0)
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 80 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 in the SH7750, the cpu cannot access a pcmcia interface area. when performing access from the cpu to a pcmcia interface area in the sh 7750s or the SH7750r, access is always performed using the values of the sa and tc bits set in the ptea register. the pcmcia interface area is always accessed by the dmac with the va lues of chcrn.ssan, chcrn.dsan, chcrn.stc, and chcrn.dtc in th e dmac. for details, see section 14, direct memory access cont roller (dmac). p0, p1, p3, u0 areas: the p0, p1, p3, and u0 areas can be accessed using the cache. whether or not the cache is used is determined by the cach e control register (ccr). when the cache is used, with the exception of the p1 area, switching be tween the copy-back method and the write-through method for write accesses is specifi ed by the ccr.wt bit. for the p1 area, switching is specified by the ccr.cb bit. zeroizing the upper 3 bits of an address in these areas gives the corresponding external memory space address. however, since ar ea 7 in the external memory space is a reserved area, a reserved area also appears in these areas. p2 area: the p2 area cannot be accessed using the cache . in the p2 area, zeroizing the upper 3 bits of an address gives the corresponding exte rnal memory space address. however, since area 7 in the external memory space is a reserved area, a reserved area also appears in this area. p4 area: the p4 area is mapped onto sh-4 on-chip i/o channels. this ar ea cannot be accessed using the cache. the p4 area is shown in detail in figure 3.4.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 81 of 1076 sep 24, 2013 h'e000 0000 h'e400 0000 h'f000 0000 h'f100 0000 h'f200 0000 h'f300 0000 h'f400 0000 h'f500 0000 h'f600 0000 h'f700 0000 h'f800 0000 h'fc00 0000 store queue reserved area instruction cache address array instruction cache data array instruction tlb address array instruction tlb data arrays 1 and 2 operand cache address array operand cache data array unified tlb address array unified tlb data arrays 1 and 2 reserved area control re g ister area figure 3.4 p4 area the area from h'e000 0000 to h'e3ff ffff comp rises addresses for accessing the store queues (sqs). when the mmu is disabled (mmucr.at = 0), the sq access right is specified by the mmucr.sqmd bit. for details, see section 4.7, store queues. the area from h'f000 0000 to h'f0ff ffff is used for dir ect access to the instruction cache address array. for details, see s ection 4.5.1, ic address array. the area from h'f100 0000 to h' f1ff ffff is used for direct access to the instruction cache data array. for details, see section 4.5.2, ic data array. the area from h'f200 0000 to h'f2ff ffff is used for dir ect access to the instruction tlb address array. for details, see sec tion 3.7.1, itlb address array.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 82 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 the area from h'f300 0000 to h' f3ff ffff is used for direct access to instruction tlb data arrays 1 and 2. for details, see sections 3.7.2, i tlb data array 1, and 3.7.3, itlb data array 2. the area from h'f400 0000 to h' f4ff ffff is used for direct access to the operand cache address array. for details, see section 4.5.3, oc address array. the area from h'f500 0000 to h' f5ff ffff is used for direct access to the operand cache data array. for details, see section 4.5.4, oc data array. the area from h'f600 0000 to h' f6ff ffff is used for direct access to the unified tlb address array. for details, see section 3.7.4, utlb address array. the area from h'f700 0000 to h'f7ff ffff is used for direct access to unified tlb data arrays 1 and 2. for details, see sections 3.7.5, utlb da ta array 1, and 3.7.6, utlb data array 2. the area from h'ff00 0000 to h'ffff ffff is the on-chip peripheral module control register area. for details, see appe ndix a, address list. 3.3.2 external memory space the sh-4 supports a 29-bit extern al memory space. the external memory space is divided into eight areas as shown in figure 3.5. areas 0 to 6 relate to memory, such as sram, synchronous dram, dram, and pcmcia. area 7 is a reserved area. for details, see section 13, bus state controller (bsc). h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1c00 0000 h'1fff ffff area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 (reserved area) figure 3.5 external memory space
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 83 of 1076 sep 24, 2013 3.3.3 virtual address space setting the mmucr.at bit to 1 enab les the p0, p3, and u0 areas of the physical memory space in the sh-4 to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-mbyte, page units. by using an 8-b it address space identifier, the p0, u0, p3, and store queue areas can be increased to a maximum of 256. this is called the virtual memory space. mapping from virtual memory space to 29-bit external memory space is car ried out using the tlb. only when area 7 in external memory space is accessed using virtual memory space, addresses h'1c00 0000 to h'1fff ffff of area 7 are not designated as a reserved area, but are equivalent to the p4 area control register area in the physical me mory space. virtual memory space is illustrated in figure 3.6. area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external memory space 256 256 u0 area cacheable address translation possible address error address error store queue area p0 area cacheable address translation possible user mode privile g ed mode p1 area cacheable address translation not possible p2 area non-cacheable address translation not possible p3 area cacheable address translation possible p4 area non-cacheable address translation not possible figure 3.6 virtual add ress space (mmucr.at = 1) in the state of cache enabling, when the areas of p0, p3, and u0 are mapped onto a pcmcia interface area by means of the tlb, it is necessary e ither to specify 1 for th e wt bit or to specify
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 84 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 0 for the c bit on that page. at that time, the regions are accessed by the values of sa and tc set in page units of the tlb. here, access to the pcmcia interface area by accessi ng an area of p1, p2, or p4 from the cpu is disabled. in addition, the pcmcia interface area is alwa ys accessed by the dmac with the values of chcrn.ssan, chcrn.dsan, chcrn.stc, and ch crn.dtc in the dmac. for details, see section 14, direct memory access controller (dmac). p0, p3, u0 areas: the p0 area (excluding addresses h'7c 00 0000 to h'7fff ffff), p3 area, and u0 area (excluding addresses h'7c00 0000 to h'7fff ffff) allow access using the cache and address translation using the tlb. these areas can be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-mbyte, page units. wh en ccr is in the cache-enabled state and the tlb enable bit (c bit) is 1, accesses can be perfor med using the cache. in wr ite accesses to the cache, switching between the copy-back method and the write-through method is indicated by the tlb write-through bit (wt bit), and is specified in page units. only when the p0, p3, and u0 areas are mapped onto external memory space by means of the tlb, addresses h'1c00 0000 to h'1fff ffff of area 7 in external memory space are allocated to the control register area. this enables on-chip peripheral module control registers to be accessed from the u0 area in user mode. in this case, the c bit for the corresponding page must be cleared to 0. p1, p2, p4 areas: address translation using the tlb cannot be performed for the p1, p2, or p4 area (except for the store queue area). accesses to these areas are the same as for physical memory space. the store queue area can be mapped on to any external memory space by the mmu. however, operation in the case of an exception di ffers from that for norma l p0, u0, and p3 spaces. for details, see section 4.7, store queues. 3.3.4 on-chip ram space in the sh-4, half of the instruction cache can be used as on-chip ram. this can be done by changing the ccr settings. when the operand cache is used as on-chip ram (ccr.ora = 1), p0 area addresses h'7c00 0000 to h'7fff ffff are an on-chip ram area. data accesses (byte/word/longword/quadword) can be used in this area. this area can only be used in ram mode.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 85 of 1076 sep 24, 2013 3.3.5 address translation when the mmu is used, the virtual address space is divided into units called pages, and translation to physical ad dresses is carried out in these page units. the address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory prot ection codes. fast address transl ation is achieved by caching the contents of the address translation table located in external memory into the tlb. in the sh-4, basically, the itlb is used for instruction acce sses and the utlb for data accesses. in the event of an access to an area other than the p4 area, the accessed virtual address is translated to a physical address. if the virtual address belongs to the p1 or p2 area, the physical address is uniquely determined without accessing the tlb. if th e virtual address belongs to the p0, u0, or p3 area, the tlb is searched using the virtual address, and if the virtual address is recorded in the tlb, a tlb hit is made and the corresponding physical address is read from the tlb. if the accessed virtual address is not recorded in th e tlb, a tlb miss exception is generated and processing switches to the tlb miss exception ro utine. in the tlb miss exception routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the tlb. after the return from the exception handling routine, the instruction which caused the tlb miss exception is re-executed. 3.3.6 single virtual memory mode and multiple virtual memory mode there are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the mmucr.sv bit. in the single virtual me mory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. in the multiple virtual memory system, a number of processes run while sharing the virtual address space, and a particular virtual address may be translated into different physical addresses depending on the process. the only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the tlb address comparison method (see section 3.4.3, address translation method). 3.3.7 address space identifier (asid) in multiple virtual memory mode, the 8-bit address space identifier (asid) is used to distinguish between processes running simulta neously while sharing the virtua l address space. software can set the asid of the currently executing process in pteh in the mmu. the tlb does not have to be purged when processes are switched by means of asid. in single virtual memory mode, asid is used to provide memory protection for processes running simultaneously while using the virtual memory space on an exclusive basis.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 86 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 note: in single virtual memory mode, entries with the same virtual page number (vpn) but different asids cannot be set in the tlb simultaneously. 3.4 tlb functions 3.4.1 unified tlb (utlb) configuration the unified tlb (utlb) is so called because of its use for the following two purposes: 1. to translate a virtual address to a physical address in a data access 2. as a table of address translation information to be recorded in the inst ruction tlb in the event of an itlb miss information in the address translation table located in external memory is cached into the utlb. the address translation table contains virtual page numbers and addre ss space identifiers, and corresponding physical page numbers and page management information. figure 3.7 shows the overall configuration of the utlb. the utlb consists of 64 fully-associativ e type entries. figure 3.8 shows the relationship between the address format and page size. ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sh sh sh c c c pr [1:0] pr [1:0] pr [1:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] v v v entry 0 entry 1 entry 2 d d d wt wt wt ppn [28:10] sz [1:0] sh c pr [1:0] sa [2:0] sa [2:0] sa [2:0] tc tc tc sa [2:0] tc asid [7:0] vpn [31:10] v entry 63 d wt figure 3.7 utlb configuration
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 87 of 1076 sep 24, 2013 31 ? 1-kbyte page 10 9 0 virtual address 31 ? 4-kbyte page 12 11 0 virtual address 31 ? 64-kbyte page 16 15 0 virtual address 31 ? 1-mbyte page 20 19 0 virtual address vpn offset vpn offset vpn offset vpn offset 28 10 9 0 physical address 28 12 11 0 physical address 28 16 15 0 physical address 28 20 19 0 physical address ppn offset ppn offset ppn offset ppn offset figure 3.8 relationship between page size and address format ? vpn: virtual page number for 1-kbyte page: upper 22 bits of virtual address for 4-kbyte page: upper 20 bits of virtual address for 64-kbyte page: upper 16 bits of virtual address for 1-mbyte page: upper 12 bits of virtual address ? asid: address space identifier indicates the process that can access a virtual page. in single virtual memory mode and user mode, or in multiple virtual memory mode, if the sh bit is 0, this identifier is compared with th e asid in pteh when address comparison is performed.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 88 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? sh: share status bit when 0, pages are not shared by processes. when 1, pages are shared by processes. ? sz: page size bits specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-mbyte page ? v: validity bit indicates whether the entry is valid. 0: invalid 1: valid cleared to 0 by a power-on reset. not affected by a manual reset. ? ppn: physical page number upper 22 bits of the physical address. with a 1-kbyte page, ppn bits [28:10] are valid. with a 4-kbyte page, ppn bits [28:12] are valid. with a 64-kbyte page, ppn bits [28:16] are valid. with a 1-mbyte page, ppn bits [28:20] are valid. the synonym problem must be taken into account when setting the ppn (see section 3.5.5, avoiding synonym problems). ? pr: protection key data 2-bit data expressing the page access right as a code. 00: can be read only, in privileged mode 01: can be read and written in privileged mode 10: can be read only, in privileged or user mode 11: can be read and written in privileged mode or user mode
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 89 of 1076 sep 24, 2013 ? c: cacheability bit indicates whether a page is cacheable. 0: not cacheable 1: cacheable when control register space is mapped , this bit must be cleared to 0. when performing pcmcia space mapping in the cach e enabled state, either clear this bit to 0 or set the wt bit to 1. ? d: dirty bit indicates whether a write has been performed to a page. 0: write has not been performed 1: write has been performed ? wt: write-through bit specifies the cache write mode. 0: copy-back mode 1: write-through mode when performing pcmcia space mapping in the cache enabled state, either set this bit to 1 or clear the c bit to 0. ? sa: space attribute bits valid only when the page is mapped onto pcmcia connected to area 5 or 6. 000: undefined 001: variable-size i/o space (base size according to iois16 signal) 010: 8-bit i/o space 011: 16-bit i/o space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space ? tc: timing control bit used to select wait control register bits in the bus control unit for areas 5 and 6. 0: wcr2 (a5w2?a5w0) and pcr (a5pcw1?a5pcw0, a5ted2?a5ted0, a5teh2? a5teh0) are used 1: wcr2 (a6w2?a6w0) and pcr (a6pcw1?a6pcw0, a6ted2?a6ted0, a6teh2? a6teh0) are used
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 90 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3.4.2 instruction tlb (itlb) configuration the itlb is used to translate a virtual address to a physical ad dress in an instruction access. information in the address translation table located in the utlb is cached into the itlb. figure 3.9 shows the overall configuration of the itlb. the itlb consists of 4 fully-associative type entries. the address translation in formation is almost the same as that in the utlb, but with the following differences: 1. d and wt bits are not supported. 2. there is only one pr bit, corresponding to the upper of the pr bits in the utlb. ppn [28:10] ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sz [1:0] sh sh sh sh c c c c pr pr pr pr asid [7:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] vpn [31:10] v v v v entry 0 entry 1 entry 2 entry 3 sa [2:0] sa [2:0] sa [2:0] sa [2:0] tc tc tc tc figure 3.9 itlb configuration 3.4.3 address translation method figures 3.10 and 3.11 show flowcharts of memory accesses using the utlb and itlb.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 91 of 1076 sep 24, 2013 mmucr.at = 1 sh = 0 and (mmucr.sv = 0 or sr.md = 0) vpns match and asids match and v = 1 only one entry matches sr.md? ccr.oce? ccr.cb? ccr.wt? vpns match and v = 1 cache access in write-throu g h mode memory access memory access data tlb multiple hit exception data tlb protection violation exception data tlb miss exception initial pa g e write exception data tlb protection violation exception cache access in copy-back mode data access to virtual address (va) on-chip i/o access r/w? r/w? va is in p4 area va is in p2 area va is in p1 area va is in p0, u0, or p3 area yes no 1 1 0 yes yes no no yes yes yes no no 1 (privile g ed) 1 0 0 pr? 0 (user) d? r/w? w w w r r rr w r/w? (non-cacheable) wt? c = 1 and ccr.oce = 1 no 1 1 0 0 00 or 01 10 11 01 or 11 00 or 10 figure 3.10 flowchart of memory access using utlb
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 92 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 mmucr.at = 1 sh = 0 and (mmucr.sv = 0 or sr.md = 0) vpns match and asids match and v = 1 only one entry matches sr.md? ccr.ice? vpns match and v = 1 memory access instruction tlb multiple hit exception instruction tlb miss exception instruction access to virtual address (va) va is in p4 area va is in p2 area va is in p1 area va is in p0, u0, or p3 area yes no 1 0 yes yes no no yes yes no (non-cacheable) c = 1 and ccr.ice = 1 no pr? instruction tlb protection violation exception match? record in itlb access prohibited 0 1 no yes yes no hardware itlb miss handlin g 0 (user) 1 (privile g ed) search utlb cache access figure 3.11 flowchart of memory access using itlb
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 93 of 1076 sep 24, 2013 3.5 mmu functions 3.5.1 mmu hardware management the sh-4 supports the following mmu functions. 1. the mmu decodes the virtual address to be accessed by software, and performs address translation by controlling the utlb/itlb in accordance with the mmucr settings. 2. the mmu determines the cache access status on the basis of the page management information read during address translation (c, wt, sa, and tc bits). 3. if address translation cannot be performed normally in a data access or instruction access, the mmu notifies software by m eans of an mmu exception. 4. if address translation information is not recorded in the itlb in an instruction access, the mmu searches the utlb, and if the necessary address translati on information is recorded in the utlb, the mmu copies this informa tion into the itlb in accordance with mmucr.lrui. 3.5.2 mmu software management software processing for the mm u consists of the following: 1. setting of mmu-related registers. some registers are also partially updated by hardware automatically. 2. recording, deletion, and reading of tlb entries. there are two methods of recording utlb entries: by using the ldtlb instruction, or by writing directly to the memory-mapped utlb. itlb entries can only be recorded by writin g directly to the memory-mapped itlb. for deleting or reading utlb/itlb entries, it is possible to access the memory-mapped utlb/itlb. 3. mmu exception handling. when an mmu exception occurs, processing is performed based on information set by hardware. 3.5.3 mmu instruction (ldtlb) a tlb load instruction (ldtlb) is provided for recording utlb entries. when an ldtlb instruction is issued, the sh-4 copies the conten ts of pteh, ptel, and ptea to the utlb entry indicated by mmucr.urc. itlb entries are not upd ated by the ldtlb instruction, and therefore address translation in formation purged from the utlb entry may still remain in the itlb entry. as the ldtlb instruction changes addr ess translation information, ensure that it is issued by a program in the p1 or p2 area. the operation of the ldtlb instruction is shown in figure 3.12.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 94 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sh sh sh c c c pr [1:0] pr [1:0] pr [1:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] v v v entry 0 entry 1 entry 2 d d d wt wt wt ppn [28:10] sz [1:0] sh c pr [1:0] sa [2:0] sa [2:0] sa [2:0] tc tc tc sa [2:0] tc asid [7:0] vpn [31:10] v entry 63 d wt 31 29 28 9 8 76 5 4 3 2 1 0 ??vszprszcdsh wt ptel write utlb 31 10 9 87 0 ? asid pteh 31 26 25 24 23 18 17 16 15 10 9 87 3 2 1 0 lrui ? urb ? urc sv sqmd ?ti?at mmucr vpn 10 ppn 31 43 2 0 ?sa tc ptea entry specification figure 3.12 operation of ldtlb instruction 3.5.4 hardware itlb miss handling in an instruction access, the sh-4 searches the itlb. if it cannot find the necessary address translation information (i.e. in the event of an i tlb miss), the utlb is searched by hardware, and if the necessary address translation information is present, it is recorded in the itlb. this procedure is known as hardware itlb miss handling. if the necessary address translation information is not found in the utlb search, an instruction tlb miss exception is generated and processing passes to software.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 95 of 1076 sep 24, 2013 3.5.5 avoiding synonym problems when 1- or 4-kbyte pages are recorded in tl b entries, a synonym pr oblem may arise. the problem is that, when a number of virtual addres ses are mapped onto a single physical address, the same physical address data is r ecorded in a number of cache entr ies, and it becomes impossible to guarantee data integrity. this problem does not occur with the instruction tlb or instruction cache. in the sh-4 , entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operatio n. however, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4-kbyte page, are subject to address translation. as a result, bits [13:10] of the physical ad dress after translation may differ from bits [13:10] of the virtual address. consequently, the following restrictions apply to the recording of address translation information in utlb entries. 1. when address translation information whereby a number of 1-kbyte page utlb entries are translated into the same physical address is recorded in the u tlb, ensure that the vpn [13:10] values are the same. 2. when address translation information whereby a number of 4-kbyte page utlb entries are translated into the same physical address is recorded in the u tlb, ensure that the vpn [13:12] values are the same. 3. do not use 1-kbyte page utlb entry physical addresses with utlb entries of a different page size. 4. do not use 4-kbyte page utlb entry physical addresses with utlb entries of a different page size. the above restrictions apply only when performing accesses us ing the cache. when cache index mode is used, vpn [25] is used for the entry ad dress instead of vpn [13] , and therefore the above restrictions apply to vpn [25]. note: when multiple items of address translation information use the same physical memory to provide for future superh risc engine family expansion, ensure that the vpn [20:10] values are the same. also, do not use the sa me physical address for address translation information of different page sizes.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 96 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3.6 mmu exceptions there are seven mmu exceptions: the instruction tlb multiple hit exception, instruction tlb miss exception, instruction tlb protection violation exception, data tlb multiple hit exception, data tlb miss exception, data tlb protection violation exception, and initial page write exception. refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions occurs. 3.6.1 instruction tlb mult iple hit exception an instruction tlb multiple hit exception occurs when more than one itlb entry matches the virtual address to which an instruction access ha s been made. if multiple hits occur when the utlb is searched by hardware in hardware itlb miss handling, a data tlb multiple hit exception will result. when an instruction tlb multiple hit exception occu rs a reset is executed, and cache coherency is not guaranteed. hardware processing: in the event of an instruction tlb multiple hit exception, hardware carries out the following processing: 1. sets the virtual address at which the exception occurred in tea. 2. sets exception code h'140 in expevt. 3. branches to the reset handling routine (h'a000 0000). software processing (reset routine): the itlb entries which caused the multiple hit exception are checked in the reset handling routine. this exception is intended for use in program debugging, and should not normally be generated. 3.6.2 instruction tlb miss exception an instruction tlb miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in th e utlb entries by the hardware itlb miss handling procedure. the instruction tlb miss excepti on processing carried out by hardware and software is shown below. this is the same as the processing for a data tlb miss exception.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 97 of 1076 sep 24, 2013 hardware processing: in the event of an instruction tlb miss exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'040 in expevt. 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, sets the pc value indicating the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0400 to the contents of vbr, and starts the instruction tlb miss exception handling routine. software processi ng (instruction tlb miss exception handling routine): software is responsible for searching the external memory page table and assigning the necessary page table entry. software should carry out the following pro cessing in order to find and assign the necessary page table entry. 1. write to ptel the values of the ppn, pr, sz, c, d, sh, v, and wt bits in the page table entry recorded in the external memory address tr anslation table. if necessary, the values of the sa and tc bits should be written to ptea. 2. when the entry to be replaced in entry replacement is specified by software, write that value to urc in the mmucr register. if urc is greater than urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction. 3. execute the ldtlb instruction and write the contents of pteh, ptel, and ptea to the tlb. 4. finally, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 98 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3.6.3 instruction tlb protection violation exception an instruction tlb protection violation exception occurs when, even though an itlb entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitte d by the access right specified by the pr bit. the instruction tlb protection violation exception processing carried out by hardware and software is shown below. hardware processing: in the event of an instruction tlb protection violation exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'0a0 in expevt. 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, sets the pc value indicating the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the instruction tlb protection violation exception handling routine. software processing (instruc tion tlb protection violation exception handling routine): resolve the instruction tlb protection violation, execute the exception handling return instruction (rte), terminate the exception handling routine, an d return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 3.6.4 data tlb multiple hit exception a data tlb multiple hit exception occurs when more than one utlb entry matches the virtual address to which a data access has been made. a da ta tlb multiple hit exception is also generated if multiple hits occur when the utlb is searched in hardware itlb miss handling. when a data tlb multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. the contents of ppn in the utlb prior to the exception may also be corrupted.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 99 of 1076 sep 24, 2013 hardware processing: in the event of a data tlb multiple h it exception, hardware carries out the following processing: 1. sets the virtual address at which the exception occurred in tea. 2. sets exception code h'140 in expevt. 3. branches to the reset handling routine (h'a000 0000). software processing (reset routine): the utlb entries which caused the multiple hit exception are checked in the reset handling routine. this exception is intended for use in program debugging, and should not normally be generated. 3.6.5 data tlb miss exception a data tlb miss exception occurs when address tr anslation information for the virtual address to which a data access is made is not found in the utlb entries. the data tlb miss exception processing carried out by hardware and software is shown below. hardware processing: in the event of a data tlb miss exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'040 in the case of a re ad, or h'060 in the case of a write, in expevt (ocbp, ocbwb: read; ocbi, movca.l: write). 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0400 to the contents of vbr, and starts the data tlb miss exception handling routine.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 100 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 software processing (data tlb miss exception handling routine): software is responsible for searching the external memory page table and assigning the necessary page table entry. software should carry out the following processing in order to find and assign the necessary page table entry. 1. write to ptel the values of the ppn, pr, sz, c, d, sh, v, and wt bits in the page table entry recorded in the external memory address tr anslation table. if necessary, the values of the sa and tc bits should be written to ptea. 2. when the entry to be replaced in entry replacement is specified by software, write that value to urc in the mmucr register. if urc is greater than urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction. 3. execute the ldtlb instruction and write th e contents of pteh, ptel, and ptea to the utlb. 4. finally, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 3.6.6 data tlb protection violation exception a data tlb protection violation exception occurs when, even though a utlb entry contains address translation information ma tching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the pr bit. the data tlb protection violation exception processing carried out by hardware and software is shown below. hardware processing: in the event of a data tlb protection violation exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'0a0 in the case of a re ad, or h'0c0 in the case of a write, in expevt (ocbp, ocbwb: read; ocbi, movca.l: write). 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 101 of 1076 sep 24, 2013 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the data tlb protection violation exception handling routine. software processing (data tlb protection violation exception handling routine): resolve the data tlb protection violation, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 3.6.7 initial page write exception an initial page write exception occurs when the d bit is 0 even though a utlb entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. the initial page write exception proce ssing carried out by hardware and software is shown below. hardware processing: in the event of an initial page writ e exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'080 in expevt. 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the initial page write exception handling routine.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 102 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 software processing (ini tial page write exception handling routine): the following processing should be carried out as the responsibility of software: 1. retrieve the necessary page table entry from external memory. 2. write 1 to the d bit in the external memory page table entry. 3. write to ptel the values of the ppn, pr, sz, c, d, wt, sh, and v bits in the page table entry recorded in external memo ry. if necessary, the values of the sa and tc bits should be written to ptea. 4. when the entry to be replaced in entry replacement is specified by software, write that value to urc in the mmucr register. if urc is greater than urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction. 5. execute the ldtlb instruction and write th e contents of pteh, ptel, and ptea to the utlb. 6. finally, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 3.7 memory-mapped tlb configuration to enable the itlb and utlb to be managed by software, their contents can be read and written by a p2 area program with a mov instruction in privileged mode. operation is not guaranteed if access is made from a program in another area. a br anch to an area other than the p2 area should be made at least 8 instructions after this mov instruction. the itlb and utlb are allocated to the p4 area in physical memory space. vpn, v, and asid in the itlb can be accessed as an address array, ppn, v, sz, pr, c, and sh as data array 1, and sa and tc as data array 2. vpn, d, v, and asid in the utlb can be accessed as an address array, ppn, v, sz, pr, c, d, wt, and sh as data array 1, and sa and tc as data arra y 2. v and d can be accessed from both the address array side and the data array side. only longword access is possible. instruction fetches cannot be performed in these areas. for reserv ed bits, a write value of 0 should be specified; their read value is undefined.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 103 of 1076 sep 24, 2013 3.7.1 itlb address array the itlb address array is allocated to addresses h'f200 0000 to h'f2ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). information for selecting the entry to be accessed is specified in the address field, and vpn, v, and asid to be wr itten to the address array are specified in the data field. in the address field, bits [31:24] have the valu e h'f2 indicating the itlb address array, and the entry is selected by bits [9:8]. as longword access is used, 0 should be specified for address field bits [1:0]. in the data field, vpn is indicated by bits [31:10], v by bit [8], and asid by bits [7:0]. the following two kinds of operation can be used on the itlb address array: 1. itlb address array read vpn, v, and asid are read into the data field from the itlb entry corr esponding to the entry set in the address field. 2. itlb address array write vpn, v, and asid specified in the data field are written to th e itlb entry corresponding to the entry set in the address field. address field 31 23 0 11110010 e data field 31 10 9 0 v vpn le g end: vpn: v: e: 24 virtual pa g e number validity bit entry 10 98 7 98 7 asid asid: : address space identifier reserved bits (0 write value, undefined read value) figure 3.13 memory-mapped itlb address array
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 104 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3.7.2 itlb data array 1 itlb data array 1 is allocated to addresses h'f3 00 0000 to h'f37f ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, an d ppn, v, sz, pr, c, and sh to be written to the data array are specified in the data field. in the address field, bits [31:23] have the value h'f30 indicating itlb data array 1, and the entry is selected by bits [9:8]. in the data field, ppn is indicated by bits [28:10], v by bit [8], sz by bits [7] and [4], pr by bit [6], c by bit [3], and sh by bit [1]. the following two kinds of operation can be used on itlb data array 1: 1. itlb data array 1 read ppn, v, sz, pr, c, and sh are read into the data field from the itlb entry corresponding to the entry set in the address field. 2. itlb data array 1 write ppn, v, sz, pr, c, and sh specified in the data field are written to the itlb entry corresponding to the entry set in the address field. address field 31 23 0 111100 0 11 e data field le g end: ppn: v: e: sz: 24 physical pa g e number validity bit entry pa g e size bits 10 98 7 pr: c: sh: : protection key data cacheability bit share status bit reserved bits (0 write value, undefined read value) 31 210 v 10987 30 29 28 4 3 65 sz sh pr c ppn figure 3.14 memory-mapped itlb data array 1
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 105 of 1076 sep 24, 2013 3.7.3 itlb data array 2 itlb data array 2 is allocated to addresses h'f3 80 0000 to h'f3ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, and sa and tc to be written to data array 2 are specified in the data field. in the address field, bits [31:23] have the value h'f38 indicating itlb data array 2, and the entry is selected by bits [9:8]. in the data field, sa is indicated by bits [2:0], and tc by bit [3]. the following two kinds of operation can be used on itlb data array 2: 1. itlb data array 2 read sa and tc are read into the data field from the itlb entry corresponding to the entry set in the address field. 2. itlb data array 2 write sa and tc specified in the data field are writte n to the itlb entry corresponding to the entry set in the address field. address field 31 23 0 1111001 1 1e data field 31 4 0 le g end: tc: e: 24 timin g control bit entry 8 9 7 32 sa: : space attribute bits reserved bits (0 write value, undefined read value) 10 sa tc figure 3.15 memory-mapped itlb data array 2
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 106 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3.7.4 utlb address array the utlb address array is allocated to addresses h'f600 0000 to h'f6ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). inform ation for selecting the entry to be accessed is specified in the address field, an d vpn, d, v, and asid to be written to the address array are specified in the data field. in the address field, bits [31:24] have the valu e h'f6 indicating the utlb address arra y, and the entry is selected by bits [13:8]. the address arra y bit [7] association bit (a bit) specifies whether or not address comparison is performed when writing to the utlb address array. in the data field, vpn is indicated by bits [31:10], d by bit [9], v by bit [8], and asid by bits [7:0]. the following three kinds of operation can be used on the utlb address array: 1. utlb address array read vpn, d, v, and asid are read into the data field from the utlb entry corresponding to the entry set in the address field. in a read, associ ative operation is not performed regardless of whether the association b it specified in the address field is 1 or 0. 2. utlb address array write (non-associative) vpn, d, v, and asid specified in the data field are written to the utlb entry corresponding to the entry set in the address field. the a bi t in the address field should be cleared to 0. 3. utlb address array write (associative) when a write is performed with the a bit in the address field set to 1, comparison of all the utlb entries is carried out us ing the vpn specified in the da ta field and pteh.asid. the usual address comparison rules are followed, but if a utlb miss occurs, the result is no operation, and an exception is not generated. if the comparison identifies a utlb entry corresponding to the vpn specified in the data field, d and v specified in the data field are written to that entry. if there is more than one matching entry, a data tlb multiple hit exception results. this asso ciative operation is simultaneously carried out on the itlb, and if a matching entry is found in the itlb, v is written to that entry. even if the utlb comparison results in no operation, a write to the itlb side only is performed as long as there is an itlb match. if there is a match in bot h the utlb and itlb, the utlb information is also written to the itlb.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 107 of 1076 sep 24, 2013 address field data field le g end: vpn: v: e: d: virtual pa g e number validity bit entry dirty bit asid: a: : address space identifier association bit reserved bits (0 write value, undefined read value) 31 0 v d 10987 30 29 28 a 8 7 asid vpn 31 23 2 1 0 11110110 e 24 14 13 figure 3.16 memory-mapped utlb address array 3.7.5 utlb data array 1 utlb data array 1 is allocated to addresses h'f700 0000 to h'f77f ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, an d ppn, v, sz, pr, c, d, sh, and wt to be written to the data array are specified in the data field. in the address field, bits [31:23] have the value h'f70 indicating utlb data array 1, and the entry is selected by bits [13:8]. in the data field, ppn is indicated by bits [28:10], v by bit [8], sz by bits [7] and [4], pr by bits [6:5], c by bit [3], d by bit [2], sh by bit [1], and wt by bit [0]. the following two kinds of operation can be used on utlb data array 1: 1. utlb data array 1 read ppn, v, sz, pr, c, d, sh, and wt are read into the data field from the utlb entry corresponding to the entry set in the address field. 2. utlb data array 1 write ppn, v, sz, pr, c, d, sh, and wt specified in the data field are written to the utlb entry corresponding to the entry set in the address field.
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 108 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 address field data field le g end: ppn: v: e: sz: d: physical pa g e number validity bit entry pa g e size bits dirty bit pr: c: sh: wt: : protection key data cacheability bit share status bit write-throu g h bit reserved bits (0 write value, undefined read value) 31 210 v 10987 30 29 28 4 3 65 pr c ppn 31 23 0 1111011 1 0 e 24 8 7 14 13 d sz sh wt figure 3.17 memory-mapped utlb data array 1 3.7.6 utlb data array 2 utlb data array 2 is allocated to addresses h'f780 0000 to h'f7ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, and sa and tc to be written to data array 2 are specified in the data field. in the address field, bits [31:23] have the value h'f78 indicating utlb data array 2, and the entry is selected by bits [13:8]. in the data field, tc is indicated by bit [3], and sa by bits [2:0]. the following two kinds of operation can be used on utlb data array 2: 1. utlb data array 2 read sa and tc are read into the data field from the utlb entry corresponding to the entry set in the address field. 2. utlb data array 2 write sa and tc specified in the data field are writte n to the utlb entry corresponding to the entry set in the address field.
SH7750, SH7750s, SH7750r group section 3 memory management unit (mmu) r01uh0456ej0702 rev. 7.02 page 109 of 1076 sep 24, 2013 address field 31 23 0 1111011 1 1e data field 31 4 0 tc 24 8 13 7 3 2 14 sa le g end: tc: e: timin g control bit entry sa: : space attribute bits reserved bits (0 write value, undefined read value) figure 3.18 memory-mapped utlb data array 2 3.8 usage notes 1. address space identi fier (asid) in single virtual memory mode refer to the note in 3.3.7, address space iden tifier (asid).
section 3 memory management unit (mmu) SH7750, SH7750s, SH7750r group page 110 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 111 of 1076 sep 24, 2013 section 4 caches 4.1 overview 4.1.1 features an SH7750 or SH7750s has an on-chip 8-kbyte instruction cache (ic) for instructions and 16- kbyte operand cache (oc) for data. half of the memory of the operand cache (8 kbytes) may alternatively be used as on-chip ram. the feat ures of this cache are su mmarized in table 4.1 the SH7750r has an on-chip 16 -kbyte instruction cache (ic) for instruct ions and 32-kbyte operand cache (oc) for data. half of the me mory of the operand cache (16 kbytes) may alternatively be used as on-chip ram. when the emode bit of the ccr register is 0, the SH7750r's cache is set to operate in the SH7750/SH7750s-compatible mode and behaves as shown in table 4.1. the features of the cache wh en the emode bit in the ccr register is 1 are given in table 4.2. the emode bit is initialized to 0 after a power-on reset or manual reset. for high-speed writing to external memories, this lsi supports 32 bytes 2 of store queues (sq). table 4.3 lists the feat ures of these sqs. table 4.1 cache features (SH7750, SH7750s) item instruction cache operand cache capacity 8-kbyte cache 16-kbyt e cache or 8-kbyte cache + 8-kbyte ram type direct mapping direct mapping line size 32 bytes 32 bytes entries 256 512 write method copy-back/write-through selectable
section 4 caches SH7750, SH7750s, SH7750r group page 112 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 4.2 cache features (SH7750r) item instruction cache operand cache capacity 16-kbyte cache 32-kbyt e cache or 16-kbyte cache + 16-kbyte ram type 2-way set-associative 2-way set-associative line size 32 bytes 32 bytes entries 256 entries/way 512 entries/way write method copy-back/write-through selectable replacement method lru (least-recent ly-used) algorithm lru algorithm table 4.3 features of store queues item store queues capacity 2 32 bytes addresses h'e000 0000 to h'e3ff ffff write store instruct ion (1-cycle write) write-back prefetch instru ction (pref instruction) access right mmu off: a ccording to mmucr.sqmd mmu on: according to individual page pr
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 113 of 1076 sep 24, 2013 4.1.2 register configuration table 4.4 shows the cache control registers. table 4.4 cache control registers name abbreviation r/w initial value * 1 p4 address * 2 area 7 address * 2 access size cache control register ccr r/w h'0000 0000 h'ff 00 001c h'1f00 001c 32 queue address control register 0 qacr0 r/w undefined h'ff00 0038 h'1f00 0038 32 queue address control register 1 qacr1 r/w undefined h 'ff00 003c h'1f00 003c 32 notes: 1. the initial value is the value after a power-on or manual reset. 2. this is the address when using the virt ual/physical address space p4 area. the area 7 address is the address used when making an access from physical address space area 7 using the tlb.
section 4 caches SH7750, SH7750s, SH7750r group page 114 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 4.2 register descriptions there are three cache and store queue related co ntrol registers, as shown in figure 4.1. ccr 31 30 14 16 15 12 11 10 9 8 7 6 5 4 3 2 cb 10 ici ice ora oix oci area wt oce iix emode * qacr0 31 5 4 2 1 0 area qacr1 31 5 4 2 1 0 notes: indicates reserved bits: 0 must be specified in a write; the read value is 0. * SH7750r only figure 4.1 cache and store queue control registers (1) cache control register (ccr): ccr contains the following bits: emode: double-sized cache mode (only for SH7750r; reserved bit for SH7750 and SH7750s) iix: ic index enable ici: ic invalidation ice: ic enable oix: oc index enable ora: oc ram enable oci: oc invalidation cb: copy-back enable wt: write-through enable oce: oc enable longword access to ccr can be performed from h'ff00 001c in the p4 area and h'1f00 001c in area 7. the ccr bits are used for the cache settings described below. consequently, ccr modifications must only be made by a program in the non-cached p2 area. after ccr is updated, an instruction that performs data access to the p0 , p1, p3, or u0 area shou ld be located at least
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 115 of 1076 sep 24, 2013 four instructions after the ccr update instruction. also, a branch instruction to the p0, p1, p3, or u0 area should be located at least eight in structions after the ccr update instruction. ? emode: double-sized cache mode bit in the SH7750r, this bit indicates whether the double-sized cache mode is used or not. this bit is reserved in the SH7750 and SH7750s. the emode bit must not be written to while the cache is being used. 0: SH7750/SH7750s-compatible mode * 1 (initial value) 1: double-sized cache mode ? iix: ic index enable bit 0: effective address bits [12:5] used for ic entry selection 1: effective address bits [25] and [11:5] used for ic entry selection ? ici: ic invalidation bit when 1 is written to this bit, the v bits of all ic entries are cleared to 0. this bit always returns 0 when read. ? ice: ic enable bit indicates whether or not the ic is to be used. when address translation is performed, the ic cannot be used unless the c bit in the page management information is also 1. 0: ic not used 1: ic used ? oix: oc index enable bit * 2 0: effective address bits [13:5] used for oc entry selection 1: effective address bits [25] and [12:5] used for oc entry selection ? ora: oc ram enable bit * 3 when the oc is enabled (oce = 1), the ora bit sp ecifies whether the half of the oc are to be used as ram. when the oc is not enabled (oce = 0), the ora bit should be cleared to 0. 0: normal mode (the entire oc is used as a cache) 1: ram mode (half of the oc is used as a cache and the other half is used as ram) ? oci: oc invalidation bit when 1 is written to this bit, the v and u bits of all oc entries are cleared to 0. this bit always returns 0 when read.
section 4 caches SH7750, SH7750s, SH7750r group page 116 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? cb: copy-back bit indicates the p1 area cache write mode. 0: write-through mode 1: copy-back mode ? wt: write-through bit indicates the p0, u0, and p3 area cache write mode. when address tran slation is performed, the value of the wt bit in the page management information has priority. 0: copy-back mode 1: write-through mode ? oce: oc enable bit indicates whether or not the oc is to be used. when address translation is performed, the oc cannot be used unless the c bit in the page management information is also 1. 0: oc not used 1: oc used notes: 1. no compatibility for ram mode in oc index mode and address assignment in ram mode. 2. when the ora bit is 1 in the SH7750 r, the oix bit should be cleared to 0. 3. when the oix bit in the SH7750r is 1, the ora bit should be cleared to 0. (2) queue address control register 0 (qacr0): longword access to qacr0 can be performed from h'ff00 0038 in the p4 area and h'1f00 0038 in area 7. qacr0 specifies the area onto which store queue 0 (sq0) is mapped when the mmu is off. (3) queue address control register 1 (qacr1): longword access to qacr1 can be performed from h'ff00 003c in the p4 area and h'1f00 003c in area 7. qacr1 specifies the area onto which store queue 1 (sq1) is mapped when the mmu is off. 4.3 operand cache (oc) 4.3.1 configuration the operand cache of the SH7750 or SH7750s is of the direct-mapping type and consists of 512 cache lines, each composed of a 19 -bit tag, v bit, u bit, and 32- byte data. the SH7750r's operand cache is 2-way set-associative. each way consists of 512 cache lines. figure 4.2 shows the configuration of the operand cache for the SH7750 and SH7750s.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 117 of 1076 sep 24, 2013 figure 4.3 shows the configuration of the operand cache for the SH7750r. 31 26 25 5 4 3 2 1 lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits mmu ram area determination ora oix [13] [12] [11:5] 511 19 bits 1 bit 1 bit ta g uv address array data array entry selection lon g word (lw) selection effective address 3 9 22 19 0 write data read data hit si g nal compare 13 12 11 10 9 0 figure 4.2 configuration of operand cache (SH7750, SH7750s)
section 4 caches SH7750, SH7750s, SH7750r group page 118 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 31 26 25 5 4 2 lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits 1 bit mmu ram area jud g ment oix ora [13] [12:5] 511 19 bits 1 bit 1 bit ta g address u v address array (way 0, way 1) data array (way 0, way 1) lru entry selection lon g word (lw) selection effective address 3 9 22 19 0 write data read data hit si g nal compare way 0 compare way 1 13 12 10 0 figure 4.3 configuration of operand cache (SH7750r)
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 119 of 1076 sep 24, 2013 ? tag stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. the tag is not initialized by a power-on or manual reset. ? v bit (validity bit) indicates that valid data is stored in the cache lin e. when this bit is 1, the cache line data is valid. the v bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. ? u bit (dirty bit) the u bit is set to 1 if data is written to the cache line while the cache is being used in copy- back mode. that is, the u bit indicates a mismatch between th e data in the cache line and the data in external memory. the u bit is never set to 1 while the cache is being used in write- through mode, unless it is modified by accessing the memory-mapped cache (see section 4.5, memory-mapped cache configuration (SH7750, SH7750s)). the u bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. ? data field the data field holds 32 bytes (256 bits) of data per cache line. the data array is not initialized by a power-on or manual reset. ? lru (SH7750r only) in a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address. when an entry is registered, the lru bit indicates which of the 2 ways it is to be registered in. the lru bit is a single bit of each entry, and its value is controlled by hardware. the lru (least-recently-used) algo rithm is used for way selecti on, and selects the less recently accessed way. the lru bits are initialized to 0 by a power-on reset but not by a manual reset. the lru bits cannot be read or written by software.
section 4 caches SH7750, SH7750s, SH7750r group page 120 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 4.3.2 read operation when the oc is enabled (ccr.oce = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. the tag, v bit, and u bit are read from the cache line indexed by effective address bits [13:5]. 2. the tag is compared with bits [28:10] of the address resulting from effective address translation by the mmu: ? if the tag matches and the v bit is 1 (3a) ? if the tag matches and the v bit is 0 (3b) ? if the tag does not match and the v bit is 0 (3b) ? if the tag does not match, the v bit is 1, and the u bit is 0 (3b) ? if the tag does not match, the v bit is 1, and the u bit is 1 (3c) 3a. cache hit the data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13: 5] in accordance with the access size (quadword/longword/word/byte). 3b. cache miss (no write-back) data is read into the cache line from the extern al memory space corresp onding to the effective address. data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the cpu. wh ile the remaining one cache line of data is being read, the cpu can execute the next processing. when reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the v bit. 3c. cache miss (with write-back) the tag and data field of the cache line indexed by effective address bits [13:5] are saved in the write-back buffer. then data is read into the cache line from the external memory space corresponding to the effective address. data reading is pe rformed, using the wraparound method, in order from the longword data correspo nding to the effective address, and when the corresponding data arrives in the cache, the read data is re turned to the cpu. while the remaining one cache line of data is being read, the cpu can execute the next processing. when reading of one line of data is completed, th e tag corresponding to th e effective address is recorded in the cache, 1 is writte n to the v bit, and 0 to the u bi t. the data in the write-back buffer is then written back to external memory.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 121 of 1076 sep 24, 2013 4.3.3 write operation when the oc is enabled (ccr.oce = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. the tag, v bit, and u bit are read from the cache line indexed by effective addr ess bits [13:5]. 2. the tag is compared with bits [28:10] of the address re sulting from e ffective address translation by the mmu: copy-back write-through ? if the tag matches and the v bit is 1 (3a) (3b) ? if the tag matches and the v bit is 0 (3c) (3d) ? if the tag does not match and the v bit is 0 (3c) (3d) ? if the tag does not match, the v bit is 1, and the u bit is 0 (3c) (3d) ? if the tag does not match, the v bit is 1, and the u bit is 1 (3e) (3d) 3a. cache hit (copy-back) a data write in accordance with the access size (quadword/longword/word /byte) is performed for the data indexed by bits [4:0] of the effec tive address of the data field of the cache line indexed by effective address bits [13:5]. then 1 is set in the u bit. 3b. cache hit (write-through) a data write in accordance with the access size (quadword/longword/word /byte) is performed for the data indexed by bits [4:0] of the effec tive address of the data field of the cache line indexed by effective address bits [13:5]. a write is also performed to the corresponding external memory using the specified access size. 3c. cache miss (no copy-back/write-back) a data write in accordance with the access size (quadword/longword/word /byte) is performed for the data indexed by bits [4:0] of the effec tive address of the data field of the cache line indexed by effective address bits [13:5]. then, data is read into the cache line from the external memory space corresp onding to the effective ad dress. data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. during this time, the cpu can execute the next processing. when reading of one line of data is completed, the tag corresponding to the eff ective address is recorded in the cache , and 1 is written to the v bit and u bit. 3d. cache miss (write-through) a write of the specified access size is performed to the external memory corresponding to the effective address. in this case, a write to cache is not performed.
section 4 caches SH7750, SH7750s, SH7750r group page 122 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3e. cache miss (with copy-back/write-back) the tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective addr ess bits [13:5]. then, data is read into the cache line from the external memory space co rresponding to the effective address. data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. during this time, the cpu can execute the next processing. when reading of one line of data is completed, the tag correspondin g to the effective addre ss is recorded in the cache, and 1 is written to the v bit and u bit. the data in the write-back buffer is then written back to external memory. 4.3.4 write-back buffer in order to give priority to da ta reads to the cache and improve pe rformance, this lsi has a write- back buffer which holds the releva nt cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. the writ e-back buffer contains one cache line of data and the physical addr ess of the purg e destination. lw7 physical address bits [28:5] lw6 lw5 lw4 lw3 lw2 lw1 lw0 figure 4.4 configuration of write-back buffer 4.3.5 write-through buffer this lsi has a 64-bit buffer for holding write da ta when writing data in write-through mode or writing to a non-cacheable area. this allows the cp u to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory. physical address bits [28:0] lw1 lw0 figure 4.5 configuration of write-through buffer
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 123 of 1076 sep 24, 2013 4.3.6 ram mode setting ccr.ora to 1 enables half of the operand cac he to be used as ram. in the SH7750 or SH7750s, the 8 kbytes of operand cache entries 128 to 255 and 384 to 511 are used as ram. in the SH7750/SH7750s-compatible mode of the SH7750r, the 8-kbyte area otherwise used for oc entries 256 to 511 is designated as a ram area. in the double-s ized cache mode of the SH7750r, a total of 16 kbytes, comprising entries 256 to 511 in both of the ways of the operand cache, is designated as a ram area. other entries can s till be used as cache. ram can be accessed using addresses h'7c00 0000 to h'7fff ffff. byte-, word-, longword-, and quadword-size data reads and writes can be performed in the operand c ache ram area. instruction fetches cannot be performed in this area. with the SH7750r, the oc index mode is not available in ram mode. an example of ram use in the SH7750 or SH7750s is shown below. here, the 4 kbytes comprising oc entries 128 to 255 are designated as ram area 1, and the 4 kbytes comprising oc entries 384 to 511 as ram area 2. ? when oc index mode is off (ccr.oix = 0) h'7c00 0000 to h'7c00 0fff (4 kb): corresponds to ram area 1 h'7c00 1000 to h'7c00 1fff (4 kb): corresponds to ram area 1 h'7c00 2000 to h'7c00 2fff (4 kb): corresponds to ram area 2 h'7c00 3000 to h'7c00 3fff (4 kb): corresponds to ram area 2 h'7c00 4000 to h'7c00 4fff (4 kb): corresponds to ram area 1 : : : ram areas 1 and 2 in the SH7750 or SH7750s then repeat every 8 kbytes up to h'7fff ffff. thus, to secure a continuous 8-kbyte ram ar ea, the area from h'7c00 1000 to h'7c00 2fff can be used, for example. ? when oc index mode is on (ccr.oix = 1) h'7c00 0000 to h'7c00 0fff (4 kb): corresponds to ram area 1 h'7c00 1000 to h'7c00 1fff (4 kb): corresponds to ram area 1 h'7c00 2000 to h'7c00 2fff (4 kb): corresponds to ram area 1 : : : h'7dff f000 to h'7dff ffff (4 kb): corresponds to ram area 1 h'7e00 0000 to h'7e00 0fff (4 kb): corresponds to ram area 2 h'7e00 1000 to h'7e00 1fff (4 kb): corresponds to ram area 2 : : : h'7fff f000 to h'7fff ffff (4 kb): corresponds to ram area 2
section 4 caches SH7750, SH7750s, SH7750r group page 124 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 as the distinction between ram areas 1 and 2 is indicated by address bit [25], the area from h'7dff f000 to h'7e00 0fff should be used to secure a continuous 8-kbyte ram area. examples of ram usage with the SH7750r is shown below. ? in SH7750/SH7750s-compatible mode (ccr.emode = 0) h'7c00 0000 to h'7c00 1fff (8 kb): ram area (entries 256 to 511) h'7c00 2000 to h'7c00 3fff (8 kb): ram area (entries 256 to 511) : : : in the same pattern, shadows of the ram area are created in 8-kbyte blocks until h'7fff ffff is reached. ? in double-sized cache mode (ccr.emode = 1) in this mode, the 8 kbytes comprising entries 256 to 511 of oc way 0 are designated as ram area 1 and the 8-kbytes comprising entries 256 to 511 of oc way 1 are designated as ram area 2. h'7c00 0000 to h'7c00 1fff (8 kb): corresponds to ram area 1 h'7c00 2000 to h'7c00 3fff (8 kb): corresponds to ram area 2 h'7c00 4000 to h'7c00 5fff (8 kb): corresponds to ram area 1 h'7c00 6000 to h'7c00 7fff (8 kb): corresponds to ram area 2 : : : in the same pattern, shadows of the ram area are created in 16-kbyte blocks until h'7fff ffff is reached. 4.3.7 oc index mode setting ccr.oix to 1 enables oc indexing to be performed using bit [25] of the effective address. this is called oc index mode. in normal mode, with ccr.oix cleared to 0, oc indexing is performed using bits [13:5] of the effective address. using index mode allows the oc to be handled as two areas by means of effective address bit [25], providing effici ent use of the cache. the SH7750r cannot be used in ram mode when oc index mode is selected.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 125 of 1076 sep 24, 2013 4.3.8 coherency between cache and external memory coherency between cache and external memory should be assured by software. in this lsi, the following four new instructions are supported for cache operations. details of these instructions are given in the programming manual. invalidate instruction: ocbi @rn cache invalidation (no write-back) purge instruction: ocbp @rn cache invalidation (with write-back) write-back instruction: ocbwb @rn cache write-back allocate instruction: movca. l r0,@rn cache allocation 4.3.9 prefetch operation this lsi supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. if it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data before hand by means of the prefetch in struction to prevent a cache miss due to the read or write operation, and so improve software performance. if a prefetch instruction is executed for data already held in the cache, or if the prefetch address re sults in a utlb miss or a protection violation, the result is no operation, and an exception is not generated. details of the prefetch instruction are given in the programming manual. prefetch instruction: pref @rn 4.3.10 notes on using cache enhanced mode (SH7750r only) when cache enhanced mode (ccr.emode = 1) is specified and oc ram mode (ccr.ora = 1) is selected, in which half of the operand cache is used as internal ram, internal ram data may be updated incorrectly. conditions under which problem occurs: incorrect data may be written to ram when the following four conditions are satisfied. condition 1: cache enhanced mode (ccr.emode = 1) is specified. condition 2: the ram m ode (ccr.ora = 1) in which half of the operand cache is used as internal ram is specified. condition 3: an exception or an interrupt occurs.
section 4 caches SH7750, SH7750s, SH7750r group page 126 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 note: this includes a break triggered by a debugging tool swapping an instruction (a break occurring when a trapa instruction or undefined instruction code h'fffd is swapped for an instruction). condition 4: a store instruction (mov, fmov, and.b, or, b, xor.b, movca.l, stc.l, or sts.l) that accesses internal ram (h'7c000 000 to h'7fffffff) exists within four instructions after the instruct ion associated with the exception or interrupt described in condition 3. this includes cases where th e store instruction that accesses internal ram itself generates an exception. description: when the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary that includes an addres s that differs by h'2000 from the address accessed by the store instruction that accesses internal ram mentione d in condition 4. for ex ample, when a long word is stored at address h'7c000204, the 8 bytes of data in the internal ram mapped to addresses h'7c002200 to h'7c002207 becomes corrupted. examples example 1 a store instruction accessing internal ram occurs with in four instructions after an instruction generating a tlb miss exception. mov.l #h'0c400000, r0 r0 is an address causing a tlb miss. mov.l #h'7c000204, r1 r1 is an address mapped to internal ram. mov.l @r0, r2 tlb miss exception occurs. nop 1st word nop 2nd word nop 3rd word mov.l r3, @r1 store instruction accessing internal ram example 2 a store instruction accessing internal ram occurs with in four instructions after an instruction causing an in terrupt to be accepted. mov.l #h'7c002000, r1 r1 is an address mapped to internal ram. mov.l #h'12345678, r0 an interrupt is accepted after this instruction. nop 1st word nop 2nd word nop 3rd word mov.l r0, @r1 store instruction accessing internal ram
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 127 of 1076 sep 24, 2013 example 3 a debugging tool generates a break to swap an instruction. original instruction string a fter instruction swap break mov.l #h'c000000, r0 mov.l #h'7c000000, r0 contains address corresponding to r0. add r0, r0 trapa #h'01 r0 address is not a problem in original instruction string. mov.l r1, @r0 mov.l r1, @r0 internal ram is accessed by a store operation because add is not executed. the store is cancelled, but 2lw starting at h'7c002000 is corrupted. workarounds: when ram mode is specified in cache en hanced mode, either of the following workarounds can be used to avoid the problem. workaround 1: use only 8 kbytes of the 16-kbyte internal ram area. in this case, ram areas for which address bits [12:0] are identical and only bit [13] differs must not be used. for example, the 8-kbyte ram area from h'7c000000 to h'7c001fff or from h'7c001000 to h'7c002fff may be used. note: when a break is used to swap instru ctions by a debugging t ool, etc., a memory access address may be changed when an instruction following the instruction generating the break is swapped for another instruction, causing the unused 8-kbyte ram area to be accessed. this will result in the problem de scribed above. however, this phenomenon only occurs during debugging when a break is used to swap instructions. using a break with no instruction swapping will not cause the problem. workaround 2: ensure that there are no instructions that ge nerate an interrupt or exception within four instructions after an instruction that accesse s internal ram. for example, the internal ram area can be used as a data table that is accessed only by load instructions, with writes to the internal ram area only being performed when the table is generated. it this case, set sr.bl to 1 to disable interrupts while writing to the table. also take measures to ensure that no exceptions du e to tlb misses, etc., occur while writing to the table. note: the problem still may occur when a break is used to swap instructions by a debugging tool. this phenomenon only occurs during debugging when a break is used to swap instructions. using a break with no instruction swapping will not cause the problem.
section 4 caches SH7750, SH7750s, SH7750r group page 128 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 4.4 instruction cache (ic) 4.4.1 configuration the instruction cache of the SH7750 or sh77 50s is of the direct-mapping type and consists of 256 cache lines, each composed of a 19-bit tag, v bit, and 32-byte data (16 instructions). the SH7750r's instruction cache is 2-way set associative. each way consists of 256 cache lines. figure 4.6 shows the configuration of the instruction cache for the SH7750 and SH7750s. figure 4.7 shows the configuration of the instruction cache for the SH7750r. lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits 255 19 bits 1 bit ta g v address array lon g word (lw) selection data array 0 read data hit si g nal compare 31 26 25 5 4 3 2 1 mmu iix [12] [11:5] entry selection effective address 8 3 22 19 13 12 11 10 9 0 figure 4.6 configuration of instruction cache (SH7750, SH7750s)
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 129 of 1076 sep 24, 2013 31 25 5 4 2 lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits 1 bit mmu iix [12] [11:5] 255 19 bits 1 bit ta g address v address array (way 0, way1) lon g word (lw) selection lru entry selection data array (way 0, way 1) effective address 3 8 22 19 0 read data hit si g nal compare way 0 compare way 1 13 12 11 10 0 figure 4.7 configuration of instruction cache (SH7750r) ? tag stores the upper 19 bits of the 29-bit external ad dress of the data line to be cached. the tag is not initialized by a power-on or manual reset. ? v bit (validity bit) indicates that valid data is stored in the cache lin e. when this bit is 1, the cache line data is valid. the v bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
section 4 caches SH7750, SH7750s, SH7750r group page 130 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? data array the data field holds 32 bytes (256 bits) of data per cache line. the data array is not initialized by a power-on or manual reset. ? lru (SH7750r only) in a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address. when an entry is registered, the lru bit indicates which of the 2 ways it is to be registered in. the lru bit is a single bit of each entry, and its usage is controlled by hardware. the lru (least-recently-used) algo rithm is used for way selection, and selects the less recently accessed way. the lru bits are initialized to 0 by a power-on reset but not by a manual reset. the lru bits cannot be read or written by software. 4.4.2 read operation when the ic is enabled (ccr.ice = 1) and inst ruction fetches are performed by means of an effective address from a cacheable area, th e instruction cache operates as follows: 1. the tag and v bit are read from the cache line indexed by effective address bits [12:5]. 2. the tag is compared with bits [28:10] of the address resulting from effective address translation by the mmu: ? if the tag matches and the v bit is 1 (3a) ? if the tag matches and the v bit is 0 (3b) ? if the tag does not match and the v bit is 0 (3b) ? if the tag does not match and the v bit is 1 (3b) 3a. cache hit the data indexed by effective address bits [4:2] is read as an instruction from the data field of the cache line indexed by effe ctive address bits [12:5]. 3b. cache miss data is read into the cache line from the extern al memory space corresp onding to the effective address. data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the cpu as an instruction. when read ing of one line of data is completed, the tag corresponding to the effec tive address is recorded in the cache, and 1 is written to the v bit.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 131 of 1076 sep 24, 2013 4.4.3 ic index mode setting ccr.iix to 1 enables ic indexing to be perf ormed using bit [25] of the effective address. this is called ic index mode. in normal mode, with ccr.iix cleared to 0, ic indexing is performed using bits [12:5] of the effective address. using index mode allows the ic to be handled as two areas by means of effective address b it [25], providing efficient use of the cache. 4.5 memory-mapped cache configuration (SH7750, SH7750s) to enable the ic and oc to be managed by software, their contents can be read and written by a p2 area program with a mov instru ction in privileged mode. opera tion is not guaranteed if access is made from a program in another area. in this cas e, a branch to the p0, u0 , p1, or p3 area should be made at least 8 instructions after this mov instruction. the ic and oc are allocated to the p4 area in physical memory space. only data accesse s can be used on both the ic address array and data array and the oc address array and data array, and accesses are always longword-size. instruction fetches cannot be performed in these areas. for reserved bits, a write value of 0 should be specified; their read value is undefined. 4.5.1 ic address array the ic address array is allocated to addresses h' f000 0000 to h'f0ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. th e entry to be accessed is specified in the address field, and the write tag and v bit are speci fied in the data field. in the address field, bits [31:24] have the value h'f0 indicating the ic address array, and the entry is specified by bits [12:5]. ccr.iix has no effect on this entry specification. the address array bit [3] association bit (a bit) specifies whether or not association is performed when writing to the ic address array. as only longword acces s is used, 0 should be specified for address field bits [1:0]. in the data field, the tag is indicated by bits [ 31:10], and the v bit by bit [0]. as the ic address array tag is 19 bits in length, data field bits [ 31:29] are not used in the case of a write in which association is not performed. data field bits [3 1:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the ic address array: 1. ic address array read the tag and v bit are read into th e data field from the ic entry corresponding to the entry set in the address field. in a read, associative opera tion is not performed regardless of whether the association bit specified in th e address field is 1 or 0.
section 4 caches SH7750, SH7750s, SH7750r group page 132 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 2. ic address array write (non-associative) the tag and v bit specified in the data field ar e written to the ic entry corresponding to the entry set in the address field. the a bit in the address field shoul d be cleared to 0. 3. ic address array write (associative) when a write is performed with the a bit in the address field set to 1, the tag stored in the entry specified in the address fiel d is compared with the tag specified in the data field. if the mmu is enabled at this time, comparison is pe rformed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the itlb. if the addresses match and the v bit is 1, the v bit specified in the data field is written into the ic entry. in other cases, no operation is performed. this opera tion is used to invalid ate a specific ic entry. if an itlb miss occurs during address transla tion, or the comparison shows a mismatch, an interrupt is not generated, no operation is pe rformed, and the write is not executed. if an instruction tlb multiple hit exception occurs during address translation, processing switches to the instruction tlb multiple hit exception handling routine. address field 31 23 12 543210 1 1 1 1 0 0 0 0 entry a data field 31 10 9 1 0 v ta g le g end: v: validity bit a: association bit : reserved bits (0 write value, undefined read value) 24 13 figure 4.8 memory-mapped ic address array 4.5.2 ic data array the ic data array is allocated to addresses h'f1 00 0000 to h'f1ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the entry to be accessed is specified in the address field, an d the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f1 indicating the ic data array, and the entry is specified by bits [12:5]. ccr.iix has no effect on this entry specification. address field bits [4:2] are used for the longword data specification in the entry. as only longword access is used, 0 should be specified for address field bits [1:0].
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 133 of 1076 sep 24, 2013 the data field is used for th e longword data specification. the following two kinds of operation can be used on the ic data array: 1. ic data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the ic entry corre sponding to the entry set in the address field. 2. ic data array write the longword data specified in th e data field is written for the data specified by the longword specification bits in the address field in the ic entry corresponding to the entry set in the address field. address field 31 23 12 5 4 2 1 0 11110001 entry l data field 31 0 lon g word data le g end: l: lon g word specification bits : reserved bits (0 write value, undefined read value) 24 13 figure 4.9 memory-mapped ic data array 4.5.3 oc address array the oc address array is allocated to addresses h'f400 0000 to h'f4ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. th e entry to be accessed is specified in the address field, and the write tag, u bit, and v bit are specified in the data field. in the address field, bits [31:24] have the value h'f4 indicating the oc address array, and the entry is specified by bits [13:5]. ccr.oix and ccr.ora have no effect on this entry specification. the address array bit [3] association bit (a bit) specifies whether or not association is performed when writing to the oc address arra y. as only longword acce ss is used, 0 should be specified for address field bits [1:0]. in the data field, the tag is indicated by bits [31:10], the u bit by bit [1], and the v bit by bit [0]. as the oc address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a
section 4 caches SH7750, SH7750s, SH7750r group page 134 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 write in which association is not performed. data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the oc address array: 1. oc address array read the tag, u bit, and v bit are read into the data field from the oc entry corresponding to the entry set in the address field. in a read, associ ative operation is not performed regardless of whether the association b it specified in the address field is 1 or 0. 2. oc address array write (non-associative) the tag, u bit, and v bit specified in the data fi eld are written to the oc entry corresponding to the entry set in the address field. the a bit in the address field shou ld be cleared to 0. when a write is performed to a cache line for which the u bit and v bit are both 1, after write- back of that cache line, the ta g, u bit, and v bit specified in the data field are written. 3. oc address array write (associative) when a write is performed with the a bit in the address field set to 1, the tag stored in the entry specified in the address fiel d is compared with the tag specified in the data field. if the mmu is enabled at this time, comparison is pe rformed after the virtua l address specified by data field bits [31:10] has been translated to a physical address using the utlb. if the addresses match and the v bit is 1, the u bit an d v bit specified in the data field are written into the oc entry. this operation is used to invalidate a specific oc entry. in other cases, no operation is performed. if the oc entry u bit is 1, and 0 is written to the v bit or to the u bit, write-back is performed. if an utlb miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. if a data tlb multiple hit exception occurs during address translation, processing switches to the data tlb multiple hit exception handling routine. address field 31 23 543210 11110100 entry a data field 31 10 9 1 0 v ta g 24 13 14 2 u le g end: v : validity bit u: dirty bit a : association bit : reserved bits (0 write value, undefined read value) figure 4.10 memory-mapped oc address array
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 135 of 1076 sep 24, 2013 4.5.4 oc data array the oc data array is allocated to addresses h'f5 00 0000 to h'f5ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the entry to be accessed is specified in the address field, an d the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f5 indicating the oc data array, and the entry is specified by bits [13:5]. ccr.oix and ccr.ora have no effect on this entry specification. address field bits [4:2] are used for the longword da ta specification in the entry. as only longword access is used, 0 should be specified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the oc data array: 1. oc data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the oc entry corresp onding to the entry set in the address field. 2. oc data array write the longword data specified in th e data field is written for the data specified by the longword specification bits in the address field in the oc entry corresponding the en try set in the address field. this write does not set the u bit to 1 on the address array side. address field 31 23 54 210 11110101 entry l data field 31 0 lon g word data 24 13 14 le g end: l : lon g word specification bits : reserved bits (0 write value, undefined read value) figure 4.11 memory-mapped oc data array
section 4 caches SH7750, SH7750s, SH7750r group page 136 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 4.6 memory-mapped cache configuration (SH7750r) to enable the management of the ic and oc by software, a program running in the privileged mode is allowed to access their contents. the contents of ic can be read and written by using mov instructions in a p2-area program running in the privileged mode. operation is not guaranteed fo r access from a program in some other area. any branching to othe r areas must take place at least 8 instructions after this mov instruction. the contents of ic can be read and written by using mov instructions in a p1- or p2-area program running in the privileged mode. operation is not guaranteed if access is attempted from a program running in some other area. a branch to the p0, u0, or p3 area must be made at least 8 instructions after this mov instruction. the ic and oc are allocated to the p4 area of the physical memory space. the address and data arrays of both the ic and oc are only accessible by their data fields. longword operations must be used. instruction fetches from these areas are not possible. for reserved bits, a write value of 0 should be specified; values read from such bits are undefined. note that, in the SH7750/SH7750s- compatible mode, the configura tion of the SH7750r's memory-mapped cache is the same as that of the SH7750 or SH7750s.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 137 of 1076 sep 24, 2013 4.6.1 ic address array the ic address array is allocated to addresses h' f000 0000 to h'f0ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. th e way and entry to be accessed is specified in the address field, and the write tag and v bit are specified in the data field. in the address field, bits [31:24] have the value h'f0 indicating the ic address array, the way is specified by bit [13], and the entry by bits [12:5]. ccr.iix has no effect on this entry specification. the address array bit [3] association bit (a bit) specifies whether or not association is performed when writing to the ic address array. as only longw ord access is used, 0 should be specified for address field bits [1:0]. in the data field, the tag is indicated by bits [ 31:10], and the v bit by bit [0]. as the ic address array tag is 19 bits in length, data field bits [ 31:29] are not used in the case of a write in which association is not performed. data field bits [3 1:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the ic address array: 1. ic address array read the tag and v bit are read into the data field from the ic entry corresponding to the way and the entry set in the address field. in a read, as sociative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. ic address array write (non-associative) the tag and v bit specified in the data field ar e written to the ic entry corresponding to the way and the entry set in the address field. the a b it in the address field sh ould be cleared to 0. 3. ic address array write (associative) when a write is performed with the a bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. the way number set by bit [13] is not used. if the mmu is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the itlb . if the addresses match and the v bit for that way is 1, the v bit specified in the data field is written into the ic entry. in other cases, no operation is performed. this operation is used to invalidate a specific ic entry. if an itlb miss occurs during address translation, or the comparison shows a mism atch, an interrupt is not generated, no operation is performed, and the write is not executed. if an instruction tlb multiple hit exception occurs during address translation, processing switches to the instruction tlb multiple hit exception handling routine.
section 4 caches SH7750, SH7750s, SH7750r group page 138 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 address field 31 23 12 543210 11110000 entry way a data field 31 10 9 1 0 v ta g le g end: v: validity bit a: association bit : reserved bits (0 write value, undefined read value 24 13 figure 4.12 memory-mapped ic address array 4.6.2 ic data array the ic data array is allocated to addresses h'f1 00 0000 to h'f1ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the way and entry to be accessed is specified in th e address field, and the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f1 indicating the ic data array, the way is specified by bit [13], and the entry by bits [12:5]. ccr.iix has no effect on this entry specification. address field bits [4 :2] are used for the longword data specification in the entry. as only longword access is used, 0 should be sp ecified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the ic data array: 1. ic data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the ic entry corresponding to the way and entry set in the address field. 2. ic data array write the longword data specified in th e data field is written for the data specified by the longword specification bits in the address field in the ic entry corresponding to the way and entry set in the address field.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 139 of 1076 sep 24, 2013 address field 31 23 12 5 4 2 1 0 11110001 entry l data field 31 0 lon g word data le g end: l: lon g word specification bits : reserved bits (0 write value, undefined read value) 24 13 way figure 4.13 memory-mapped ic data array 4.6.3 oc address array the oc address array is allocated to addresses h'f400 0000 to h'f4ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. th e way and entry to be accessed is specified in the address field, and the write tag, u bit, and v bit are specified in the data field. in the address field, bits [31:24] have the value h'f4 indicating the oc address array, the way is specified by bit [14], and the entry by bits [13:5]. ccr.oix has no effect on this entry specification. in ram mode (ccr.ora = 1), the oc's address arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. for details about address mapping, see section 4.6.5, summary of the memory-mapping of the oc. the address array bit [3] association bit (a bit) specifies whether or not association is performed when writing to the oc address array. as only longword access is used , 0 should be specified for address field bits [1:0]. in the data field, the tag is indicated by bits [31:10], the u bit by bit [1], and the v bit by bit [0]. as the oc address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the oc address array: 1. oc address array read the tag, u bit, and v bit are read into the data field from the oc entry corresponding to the way and the entry set in the address field. in a read, associative oper ation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. oc address array write (non-associative)
section 4 caches SH7750, SH7750s, SH7750r group page 140 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 the tag, u bit, and v bit specified in the data fi eld are written to the oc entry corresponding to the way and the entry set in the address field. the a bit in the address field should be cleared to 0. when a write is performed to a cache line for which the u bit and v bit are both 1, after write- back of that cache line, the ta g, u bit, and v bit specified in the data field are written. 3. oc address array write (associative) when a write is performed with the a bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. the way number set by bit [14] is not used. if the mmu is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the utlb . if the addresses match and the v bit for that way is 1, the u bit and v bit specified in the da ta field are written into the oc entry. this operation is used to invalidate a specific oc entry. in other cases, no operation is performed. if the oc entry u bit is 1, and 0 is written to the v bit or to the u bit, write-back is performed. if an utlb miss occurs during ad dress translation, or the comp arison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. if a data tlb multiple hit exception occurs during address translation, processing switches to the data tlb multiple hit exception handling routine. address field 31 23 543210 11110100 entry a data field 31 10 9 1 0 v ta g 24 13 14 15 2 u le g end: v : validity bit u: dirty bit a : association bit : reserved bits (0 write value, undefined read value) way figure 4.14 memory-mapped oc address array
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 141 of 1076 sep 24, 2013 4.6.4 oc data array the oc data array is allocated to addresses h'f5 00 0000 to h'f5ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the way and entry to be accessed is specified in th e address field, and the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f5 indicating the oc data array, the way is specified by bit [14], and the entry by bits [13:5]. ccr.oix has no effect on this entry specification. in ram mode (ccr.ora = 1), the oc's data arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. for details about address mapping, see section 4.6.5, summary of the memory-mapping of the oc. address field bits [4:2] are used for the longword data specification in the entry. as only longword access is used, 0 should be specified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the oc data array: 1. oc data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the oc entry corresp onding to the way and entry set in the address field. 2. oc data array write the longword data specified in th e data field is written for the data specified by the longword specification bits in the address field in the oc entry corresponding the way and entry set in the address field. this write does not set the u bit to 1 on the address array side. address field 31 23 54 210 11110101 entry l data field 31 0 lon g word data 24 13 14 15 le g end: l : lon g word specification bits : reserved bits (0 write value, undefined read value) way figure 4.15 memory-mapped oc data array
section 4 caches SH7750, SH7750s, SH7750r group page 142 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 4.6.5 summary of the memory-mapping of the oc the address ranges to which the oc is memory-mapped in the double-sized cache mode of the SH7750r are summarized below, using examples of data-array access. ? in normal mode (ccr.ora = 0) h'f500 0000 to h'f500 3fff (16 kb ): way 0 (entries 0 to 511) h'f500 4000 to h'f500 7fff (16 kb ): way 1 (entries 0 to 511) : : : in the same pattern, shadows of the cache area are created in 32-kbyte blocks until h'f5ff ffff. ? in ram mode (ccr. ora = 1) h'f500 0000 to h'f500 1fff (8 kb ): way 0 (entries 0 to 255) h'f500 2000 to h'f500 3fff (8 kb ): way 1 (entries 0 to 255) : : : in the same pattern, shadows of the cache area are created in 16-kbyte blocks until h'f5ff ffff. 4.7 store queues this lsi supports two 32-byte store queues (sqs) to perform high-speed writes to external memory. in the SH7750s or SH7750r, if the sqs are not used the low power dissipation power-down modes, in which sq functions are stopped, can be used. the queue address control registers (qacr0 and qacr1) cannot be accessed while sq f unctions are stopped. see section 9, power- down modes, for the procedure for stopping sq functions. 4.7.1 sq configuration there are two 32-byte store queues, sq0 and sq1, as shown in figure 4.16. these two store queues can be set independently.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 143 of 1076 sep 24, 2013 sq0 sq0[0] sq0[1] sq0[2] sq0[3] sq0[4] sq0[5] sq0[6] sq0[7] sq1 sq1[0] sq1[1] sq1[2] sq1[3] sq1[4] sq1[5] sq1[6] sq1[7] 4b 4b 4b 4b 4b 4b 4b 4b figure 4.16 store queue configuration 4.7.2 sq writes a write to the sqs can be performed using a store instruction (mov) on p4 area h'e000 0000 to h'e3ff fffc. a longword or quad word access size can be used. the meaning of the address bits is as follows: [31:26]: 111000 store queue specification [25:6]: don't care used for exte rnal memory transfer/access right [5]: 0/1 0: sq0 specification 1: sq1 specification [4:2]: lw specification specifies longword position in sq0/sq1 [1:0] 00 fixed at 0 4.7.3 transfer to external memory transfer from the sqs to external memory can be performed with a prefet ch instruction (pref). issuing a pref instruction for p4 area h'e000 0000 to h'e3ff fffc starts a burst transfer from the sqs to external memory. the burst transfer lengt h is fixed at 32 bytes, and the start address is always at a 32-byte bound ary. while the contents of one sq are being transferred to external memory, the other sq can be written to without a penalty cycle, but writing to the sq involved in the transfer to external memory is de ferred until the transf er is completed. the sq transfer destination external memory addr ess bit [28:0] specificatio n is as shown below, according to whether the mmu is on or off. ? when mmu is on the sq area (h'e000 0000 to h'e3ff ffff) is set in vpn of the utlb, and the transfer destination external memory address in ppn. the asid, v, sz, sh, pr, and d bits have the same meaning as for normal address translation, but the c and wt bits have no meaning with regard to this page. since burst transfer is prohibited for pcmcia areas, the sa and tc bits also have no meaning.
section 4 caches SH7750, SH7750s, SH7750r group page 144 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 when a prefetch instruction is issued for the sq area, address translation is performed and external memory address bits [28:10] are generated in accordance with the sz bit specification. for external memory address bits [9:5], the addr ess prior to address translation is generated in the same way as when the mmu is off. external memory addres s bits [4:0] are fixed at 0. transfer from the sqs to external memory is perf ormed to this address. ? when mmu is off the sq area (h'e000 0000 to h'e3ff ffff) is specified as the addr ess to issue a pref instruction. the meaning of address bits [31:0] is as follows: [31:26]: 111000 store queue specification [25:6]: address external memory address bits [25:6] [5]: 0/1 0: sq0 specification 1: sq1 specification and exte rnal memory address bit [5] [4:2]: don't care no meaning in a prefetch [1:0] 00 fixed at 0 external memory address bits [28:26], which cannot be generated from the above address, are generated from the qacr0/1 registers. qacr0 [4:2]: external memory address bits [28:26] corresponding to sq0 qacr1 [4:2]: external memory address bits [28:26] corresponding to sq1 external memory address bits [4:0] are always fi xed at 0 since burst transfer starts at a 32-byte boundary. in the SH7750, data transfer to a pcmcia interface area cannot be performed using an sq. in the SH7750s or SH7750r, data tran sfer to a pcmcia interface area is always performed using the sa and tc bits in the ptea register.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 145 of 1076 sep 24, 2013 4.7.4 sq protection determination of an exception in a write to an sq or transfer to external memory (pref instruction) is performed as follows according to whether the mmu is on or off. in the SH7750 or SH7750s, if an exception occurs in an sq wr ite, the sq contents may be corrupted. in the SH7750r, original sq contents ar e guaranteed. if an exce ption occurs in transfer from an sq to external memory, the transfer to external memory will be aborted. ? when mmu is on operation is in accordance with the address tran slation information recorded in the utlb, and mmucr.sqmd. write type exception judgment is performed for writes to the sqs, and read type for transfer from the sqs to external memory (pref instruction), and a tlb miss exception, protection violation exception, or initial page write exception is generated. however, if sq access is enab led, in privileged mode only , by mmucr.sqmd, an address error will be flagged in user mode ev en if address transl ation is successful. ? when mmu is off operation is in accordance with mmucr.sqmd. 0: privileged/user access possible 1: privileged access possible if the sq area is accessed in user mode when mmu cr.sqmd is set to 1, an address error will be flagged. 4.7.5 reading the sqs (SH7750r only) in the SH7750r, a load instruction may be executed in the privileged mode to read the contents of the sqs from the address range of h'ff001000 to h'ff00103c in the p4 area. only longword access is possible. [31:6] : h'ff001000 : store queue specification [5] : 0/1 : 0: sq0 specification, 1: sq1 specification [4:2] : lw specification : specification of longword position in sq0 or sq1 [1:0] : 00 : fixed at 0
section 4 caches SH7750, SH7750s, SH7750r group page 146 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 4.7.6 sq usage notes if an exception occurs within the three instructions preceding an instruction th at writes to an sq in the SH7750 and SH7750s, a branch may be ma de to the exception handling routine after execution of the sq write that should be suppressed when an exception occurs. this may be due to the bug described in (1) or (2) below. (1) when sq data is transferred to ex ternal memory within a normal program if a pref instruction for transfer from an sq to external memory is included in the three instructions preceding an sq stor e instruction, the sq is updat ed because the sq write that should be suppressed when a branch is made to the exception handling routine is executed, and after returning from the exception handling routine the execution order of the pref instruction and sq store instruction is reversed, so that erroneous data may be transferred to external memory. (2) when sq data is transferred to extern al memory in an excep tion handling routine if store queue contents are transferred to external memory within an exception handling routine, erroneous data may be transferred to external memory. example 1: when an sq store instruction is executed after a pref instruction for transfer from that same sq to external memory pref instruction ; pref instruction for transfer from sq to external memory ; address of this instruction is saved to spc when exception occurs. ; instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling routine. instruction 1 ; may be executed if an sq store instruction. instruction 2 ; may be executed if an sq store instruction. instruction 3 ; may be executed if an sq store instruction. instruction 4 ; not executed even if an sq store instruction.
SH7750, SH7750s, SH7750r group section 4 caches r01uh0456ej0702 rev. 7.02 page 147 of 1076 sep 24, 2013 example 2: when an instruction that generates an exception branches using a branch instruction instruction 1 (branch instruction) ; address of this instruction is saved to spc when exception occurs. instruction 2 ; may be executed if instruction 1 is a delay slot instruction and an instruction to store data to sq. instruction 3 instruction 4 instruction 5 instruction 6 instruction 7 (branch destination of instruction 1) ; may be executed if an sq access instruction. instruction 8 ; may be executed if an sq store instruction. example 3: when an instruction that generates an except ion does not branch using a branch instruction instruction 1 (branch instruction) ; address of this instruction is saved to spc when exception occurs. instruction 2 ; may be executed if an sq store instruction. instruction 3 ; may be executed if an sq store instruction. instruction 4 ; may be executed if an sq store instruction. instruction 5 to recover from this problem it is necessary that conditions a and b be satisfied. a: after the pref instruction to transfer data from the store queue (s q0, sq1) to external memory, a store instruction for the same store qu eue must be executed, and conditions (1) and (2) below must be satisfied. (1) three nop instructions * 1 must be inserted between the above two instructions. (2) there must not be a pref instruction to tr ansfer data from the st ore queue to external memory in the delay slot of the branch instruction. b: there must be no pref instruction to transfer data from the store queue to external memory executed in the exception handling routine. if such an instruction is executed, and if there is a store to the store queue instruction among the four instructions * 2 at the address referred to by spc , the data transferred to external memory by the pref instruction may indicate that execution of the store instruction has completed. notes: 1. if there are other instructions between the above two instructions, the problem can be avoided if the other instructions and nop instructions together total three or more instructions. 2. if the instruction at the address referred to by spc is a branch instruction the two instructions at the branch destination may be affected.
section 4 caches SH7750, SH7750s, SH7750r group page 148 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 149 of 1076 sep 24, 2013 section 5 exceptions 5.1 overview 5.1.1 features exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the cpu in case of abnormal events. for ex ample, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality befo re terminating the processing. the process of generating an exception handling request in response to abnormal termination, and passing control to a user-written exception handling routine, in order to support such functions, is given the generic name of exception handling. sh-4 exception handling is of three kinds: fo r resets, general exceptions, and interrupts. 5.1.2 register configuration the registers used in exception handling are shown in table 5.1. table 5.1 exception-related registers name abbrevia- tion r/w initial value * 1 p4 address * 2 area 7 address * 2 access size trapa exception register tra r/w undefined h 'ff00 0020 h'1f00 0020 32 exception event register expevt r/w h'0000 0000/ h'0000 0020 * 1 h'ff00 0024 h'1f00 0024 32 interrupt event register intevt r/w undefined h'ff00 0028 h'1f00 0028 32 notes: 1. h'0000 0000 is set in a power-on reset, and h'0000 0020 in a manual reset. 2. this is the address when using the virt ual/physical address space p4 area. the area 7 address is the address used when making an access from physical address space area 7 using the tlb.
section 5 exceptions SH7750, SH7750s, SH7750r group page 150 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 5.2 register descriptions there are three registers related to exception hand ling. addresses are allocated to these registers, and they can be accessed by specifying the p4 address or area 7 address. 1. the exception event register (expevt) reside s at p4 address h'ff00 0024, and contains a 12- bit exception code. the exception code set in expevt is that for a reset or general exception event. the exception code is set automatica lly by hardware when an exception occurs. expevt can also be modified by software. 2. the interrupt event register (intevt) resides at p4 address h'ff00 002 8, and contains a 12- bit exception code. the exception code set in intevt is that for an interrupt request. the exception code is set automatically by hardware when an exception occurs. intevt can also be modified by software. 3. the trapa exception register (tra) resides at p4 address h'ff00 0020, and contains 8-bit immediate data (imm) for the tr apa instruction. tra is set automatically by hardware when a trapa instruction is executed. tra can also be modified by software. the bit configurations of expevt, intevt, and tra are shown in figure 5.1. 31 0 0 0 0 0 0 0 31 10 9 1 0 le g end: 0: reserved bits. these bits are always read as 0, and should only be written with 0. imm: 8-bit immediate data of the trapa instruction 12 11 2 expevt and intevt tra imm exception code figure 5.1 register bit configurations
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 151 of 1076 sep 24, 2013 5.3 exception handling functions 5.3.1 exception handling flow in exception handling, the contents of the program counter (pc), status register (sr), and r15 are saved in the saved program counter (spc), saved status register (ssr), and saved general register15(sgr), and the cpu st arts execution of the appropri ate exception handling routine according to the vector address. an exception handling routine is a program written by the user to handle a specific exception. the ex ception handling routine is terminated and control returned to the original program by executing a return-from- exception instruction (rte). this instruction restores the pc and sr contents and returns control to the normal processing routine at the point at which the exception occurred. the sgr contents are not written back to r15 by an rte instruction. the basic processing flow is as follows. see section 2, programming model, for the meaning of the individual sr bits. 1. the pc, sr, and r15 contents are saved in spc, ssr, and sgr. 2. the block bit (bl) in sr is set to 1. 3. the mode bit (md) in sr is set to 1. 4. the register bank bit (rb) in sr is set to 1. 5. in a reset, the fpu disable b it (fd) in sr is cleared to 0. 6. the exception code is written to bits 11?0 of the exception event register (expevt) or interrupt event register (intevt). 7. the cpu branches to the determined excep tion handling vector address, and the exception handling routine begins. 5.3.2 exception handling vector addresses the reset vector address is fixed at h'a000 0000 . general exception and interrupt vector addresses are determined by adding the offset for the specifi c event to the vector base address, which is set by software in the vector base register (vbr). in the case of the tlb miss exception, for example, the offset is h'0000 0400, so if h'9c08 0000 is set in vbr, the exception handling vector address will be h'9c08 0400. if a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; th erefore, fixed physical addresses (p1, p2) should be specified for vector addresses.
section 5 exceptions SH7750, SH7750s, SH7750r group page 152 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 5.4 exception types and priorities table 5.2 shows the types of exceptions, with thei r relative priorities, vector addresses, and exception/interrupt codes. table 5.2 exceptions exception category execution mode exception priority level priority order vector address offset exception code power-on reset 1 1 h'a000 0000 ? h'000 manual reset 1 2 h'a000 0000 ? h'020 h-udi reset 1 1 h'a000 0000 ? h'000 instruction tlb multiple-hit exception 1 3 h'a000 0000 ? h'140 reset abort type data tlb multiple-hit exception 1 4 h'a000 0000 ? h'140 user break before instruction execution * 1 2 0 (vbr/dbr) h'100/ ? h'1e0 instruction address error 2 1 (vbr) h'100 h'0e0 instruction tlb miss exception 2 2 (vbr) h'400 h'040 instruction tlb protection violation exception 2 3 (vbr) h'100 h'0a0 general illegal instruction exception 2 4 (vbr) h'100 h'180 slot illegal instruction exception 2 4 (vbr) h'100 h'1a0 general fpu disable exception 2 4 (vbr) h'100 h'800 slot fpu disable exception 2 4 (vbr) h'100 h'820 data address error (read) 2 5 (vbr) h'100 h'0e0 data address error (write) 2 5 (vbr) h'100 h'100 data tlb miss exception (read) 2 6 (vbr) h'400 h'040 data tlb miss exception (write) 2 6 (vbr) h'400 h'060 data tlb protection violation exception (read) 2 7 (vbr) h'100 h'0a0 data tlb protection violation exception (write) 2 7 (vbr) h'100 h'0c0 fpu exception 2 8 (vbr) h'100 h'120 re- execution type initial page write exception 2 9 (vbr) h'100 h'080 unconditional trap (trapa) 2 4 (vbr) h'100 h'160 general exception completion type user break after instruction execution * 1 2 10 (vbr/dbr) h'100/ ? h'1e0
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 153 of 1076 sep 24, 2013 exception category execution mode exception priority level priority order vector address offset exception code nonmaskable interrupt 3 ? (vbr) h'600 h'1c0 0 h'200 1 h'220 2 h'240 3 h'260 4 h'280 5 h'2a0 6 h'2c0 7 h'2e0 8 h'300 9 h'320 a h'340 b h'360 c h'380 d h'3a0 external interrupts irl3?irl0 e 4 * 2 (vbr) h'600 h'3c0 tmu0 tuni0 h'400 tmu1 tuni1 h'420 tuni2 h'440 tmu2 ticpi2 h'460 tmu3 tuni3 h'b00 tmu4 tuni4 h'b80 ati h'480 pri h'4a0 rtc cui h'4c0 sci eri h'4e0 rxi h'500 txi h'520 tei h'540 wdt iti h'560 rcmi h'580 ref rovi 4 * 2 (vbr) h'600 h'5a0 interrupt completion type peripheral module interrupt (module/ source) h-udi h-udi h'600 gpio gpioi h'620
section 5 exceptions SH7750, SH7750s, SH7750r group page 154 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 exception category execution mode exception priority level priority order vector address offset exception code dmte0 h'640 dmte1 h'660 dmte2 h'680 dmte3 h'6a0 dmte4 * 3 h'780 dmte5 * 3 h'7a0 dmte6 * 3 h'7c0 dmte7 * 3 h'7e0 dmac dmae h'6c0 eri h'700 rxi h'720 bri h'740 interrupt completion type peripheral module interrupt (module/ source) scif txi 4 * 2 (vbr) h'600 h'760 priority: priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). exception transition destination: control passes to h'a000 0000 in a reset, and to [vbr + offset] in other cases. exception code: stored in expevt for a reset or gener al exception, and in intevt for an interrupt. irl: interrupt request level (pins irl3?irl0). module/source: see the sections on the relevant peripheral modules. notes: 1. when brcr.ubde = 1, pc = db r. in other cases, pc = vbr + h'100. 2. the priority order of external interrupts and peripheral module interrupts can be set by software. 3. SH7750r only.
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 155 of 1076 sep 24, 2013 5.5 exception flow 5.5.1 exception flow figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. for the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/gener al exception/interrupt). register settings in the event of an exception are shown only for ssr, spc, sgr, expevt/intevt, sr, and pc, but other registers may be set automatically by hardware, depending on the exception. for details, see section 5.6, description of exceptions. also, see section 5.6.4, priority order with multiple exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, and in the case of instru ctions in which two data accesses are performed. execute next instruction is highest- priority exception re-exception type? cancel instruction execution result yes yes yes no no no no yes ssr sr spc pc sgr r15 expevt/intevt exception code sr.{md,rb,bl} 111 pc (brcr.ubde=1 && user_break? dbr: (vbr + offset)) expevt exception code sr. {md, rb, bl, fd, imask} 11101111 pc h'a000 0000 interrupt requested? general exception requested? reset requested? figure 5.2 instruction execution and exception handling
section 5 exceptions SH7750, SH7750s, SH7750r group page 156 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 5.5.2 exception source acceptance a priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. five of the general exceptions?the general illegal instruction exception, slot illegal instruction exception, general fpu disable exception, slot fpu disable exception, and uncon ditional trap exception?are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. these exceptions therefore all have the same priority. general exceptions are detected in the order of instruction execution. however, exception handling is performed in the order of instruction flow (program order). thus, an exceptio n for an earlier instruction is accepted before that for a later instruction. an example of the order of acceptance for general ex ceptions is shown in figure 5.3.
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 157 of 1076 sep 24, 2013 if if id id ex ex ma ma wb wb tlb miss (data access) pipeline flow: order of detection: instruction n instruction n+1 general illegal instruction exception (instruction n+1) and tlb miss (instruction n+2) are detected simultaneously order of exception handling: tlb miss (instruction n) program order 1 instruction n+2 general illegal instruction exception if id ex ma wb if id ex ma wb tlb miss (instruction access) 2 3 4 legend: if: instruction fetch id: instruction decode ex: instruction execution ma: memory access wb: write-back instruction n+3 tlb miss (instruction n) re-execution of instruction n general illegal instruction exception (instruction n+1) re-execution of instruction n+1 tlb miss (instruction n+2) re-execution of instruction n+2 execution of instruction n+3 figure 5.3 example of general exception acceptance order
section 5 exceptions SH7750, SH7750s, SH7750r group page 158 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 5.5.3 exception requests and bl bit when the bl bit in sr is 0, genera l exception and interrupts are accepted. when the bl bit in sr is 1 and a general exception other than a user break is generated, the cpu's internal registers and the registers of the other mo dules are set to their st ates following a manual reset, and the cpu branches to the same address as in a reset (h'a000 000 0). for the operation in the event of a user break, see sec tion 20, user break controller (ubc). if an ordinary interrupt occurs, the interrupt reque st is held pending and is accepted after the bl bit has been cleared to 0 by so ftware. if a nonmaskable interrupt (nmi) occurs, it can be held pending or accepted according to the setting made by software. thus, normally, spc and ssr are saved and then th e bl bit in sr is cleared to 0, to enable multiple exception state acceptance. 5.5.4 return from exception handling the rte instruction is used to return from exception handling. when the rte instruction is executed, the spc contents are restored to pc and the ssr contents to sr, and the cpu returns from the exception handling routine by branching to the spc address. if spc and ssr were saved to external memory, set the bl bit in sr to 1 before restoring the spc and ssr contents and issuing the rte instruction. 5.6 description of exceptions the various exception handling operations are described here, covering exception sources, transition addresses, and processor operation when a transition is made.
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 159 of 1076 sep 24, 2013 5.6.1 resets (1) power-on reset ? sources: ? sck2 pin high level and reset pin low level ? when the watchdog timer overflows while the wt/ it bit is set to 1 and the rsts bit is cleared to 0 in wtcsr. for details, see section 10, clock oscillation circuits. ? transition address: h'a000 0000 ? transition operations: exception code h'000 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cleared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed. for details, see the register descriptions in the relevant sections. for some cpu functions, the trst pin and reset pin must be driven low. it is therefore essen tial to execute a power-on reset and drive the trst pin low when powering on. if the sck2 pin is changed to the low level while the reset pin is low, a manual reset may occur after the power-on reset operation. do not drive the sck2 pin low during this interval (see figure 22.3). power_on_reset() { expevt = h'00000000; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd=0; initialize_cpu(); initialize_module(poweron); pc = h'a0000000; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 160 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (2) manual reset ? sources: ? sck2 pin low level and reset pin low level ? when a general exception other than a user break occurs while the bl bit is set to 1 in sr ? when the watchdog timer overflows while the wt/ it bit and rsts bit are both set to 1 in wtcsr. for details, see section 10, clock oscillation circuits. ? transition address: h'a000 0000 ? transition operations: exception code h'020 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed. for details, see the register descriptions in the relevant sections. manual_reset() { expevt = h'00000020; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(manual); pc = h'a0000000; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 161 of 1076 sep 24, 2013 table 5.3 types of reset reset state transition conditions internal states type sck2 reset cpu on-chip peripheral modules power-on reset high low initialized manual reset low low initialized see register configuration in each section (3) h-udi reset ? source: sdir.ti3?ti0 = b'0110 (negation) or b'0111 (assertion) ? transition address: h'a000 0000 ? transition operations: exception code h'000 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed. for details, see the register descriptions in the relevant sections. h-udi_reset() { expevt = h'00000000; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(poweron); pc = h'a0000000; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 162 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (4) instruction tlb multiple-hit exception ? source: multiple itlb address matches ? transition address: h'a000 0000 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. exception code h'140 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed in the same way as in a manual reset. for details, see the register descriptions in the relevant sections. tlb_multi_hit() { tea = exception_address; pteh.vpn = page_number; expevt = h'00000140; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(manual); pc = h'a0000000; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 163 of 1076 sep 24, 2013 (5) operand tlb multiple-hit exception ? source: multiple utlb address matches ? transition address: h'a000 0000 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. exception code h'140 is set in expevt, initia lization of vbr and sr is performed, and a branch is made to pc = h'a000 0000. in the initialization processing, the vbr register is set to h'0000 0000, and in sr, the md, rb, and bl bits are set to 1, the fd bit is cl eared to 0, and the interrupt mask bits (imask) are set to b'1111. cpu and on-chip peripheral module initialization is performed in the same way as in a manual reset. for details, see the register de scriptions in the relevant sections. tlb_multi_hit() { tea = exception_address; pteh.vpn = page_number; expevt = h'00000140; vbr = h'00000000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.imask = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(manual); pc = h'a0000000; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 164 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 5.6.2 general exceptions (1) data tlb miss exception ? source: address mismatch in utlb address comparison ? transition address: vbr + h'0000 0400 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'040 (for a read access) or h' 060 (for a write access) is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0400. to speed up tlb miss processing, the offset is separate from that of other exceptions. data_tlb_miss_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access ? h'00000040 : h'00000060; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000400; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 165 of 1076 sep 24, 2013 (2) instruction tlb miss exception ? source: address mismatch in itlb address comparison ? transition address: vbr + h'0000 0400 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'040 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0400. to speed up tlb miss processing, the offset is separate from that of other exceptions. itlb_miss_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'00000040; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000400; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 166 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (3) initial page write exception ? source: tlb is hit in a store access, but dirty bit d = 0 ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'080 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. initial_write_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'00000080; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 167 of 1076 sep 24, 2013 (4) data tlb protectio n violation exception ? source: the access does not a ccord with the utlb protection information (pr bits) shown below. pr privileged mo de user mode 00 only read access possible access not possible 01 read/write access possible access not possible 10 only read access possible only read access possible 11 read/write access possible read/write access possible ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'0a0 (for a read access) or h' 0c0 (for a write access) is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. data_tlb_protection_violation_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access ? h'000000a0 : h'000000c0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 168 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (5) instruction tlb protection violation exception ? source: the access does not a ccord with the itlb protection information (pr bits) shown below. pr privileged mo de user mode 0 access possible access not possible 1 access possibl e access possible ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'0a0 is set in expevt. the bl , md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. itlb_protection_violation_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'000000a0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 169 of 1076 sep 24, 2013 (6) data address error ? sources: ? word data access from other than a word boundary (2n +1) ? longword data access from other than a longwor d data boundary (4n +1, 4n + 2, or 4n +3) ? quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ? access to area h'8000 0000?h'ffff ffff in user mode ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'0e0 (for a read access) or h'10 0 (for a write access) is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. for details, see section 3, memory management unit (mmu). data_address_error() { tea = exception_address; pten.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access? h'000000e0: h'00000100; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 170 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (7) instruction address error ? sources: ? instruction fetch from other than a word boundary (2n +1) ? instruction fetch from area h'8000 0000?h'ffff ffff in user mode ? transition address: vbr + h'0000 0100 ? transition operations: the virtual address (32 bits) at which this exception occurred is set in tea, and the corresponding virtual page number (22 bits) is set in pteh [31:10]. asid in pteh indicates the asid when this exception occurred. the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'0e0 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. for details, see section 3, memory management unit (mmu). instruction_address_error() { tea = exception_address; pten.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'000000e0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 171 of 1076 sep 24, 2013 (8) unconditional trap ? source: execution of trapa instruction ? transition address: vbr + h'0000 0100 ? transition operations: as this is a processing-completion-type exception, the pc contents for the instruction following the trapa instruction are saved in spc. the values of sr and r15 when the trapa instruction is executed are saved in ssr and sgr. the 8-bit immediate value in the trapa instruction is multiplied by 4, and the result is set in tra [9:0]. exception code h'160 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. trapa_exception() { spc = pc + 2; ssr = sr; sgr = r15; tra = imm << 2; expevt = h'00000160; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 172 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (9) general illegal instruction exception ? sources: ? decoding of an undefined instruction not in a delay slot delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s undefined instruction: h'fffd ? decoding in user mode of a privileged instruction not in a delay slot privileged instructions: ldc, stc, rt e, ldtlb, sleep, but excluding ldc/stc instructions that access gbr ? transition address: vbr + h'0000 0100 ? transition operations: the pc and sr contents for the instruction at which this excepti on occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'180 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. operation is not guaranteed if an undefined code other than h'fffd is decoded. general_illegal_instruction_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'00000180; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 173 of 1076 sep 24, 2013 (10) slot illegal instruction exception ? sources: ? decoding of an undefined instruction in a delay slot delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s undefined instruction: h'fffd ? decoding of an instruction that modifies pc in a delay slot instructions that modify pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l @rm+, sr ? decoding in user mode of a privileged instruction in a delay slot privileged instructions: ldc, stc, rte, ldtlb, sleep, but excluding ldc/stc instructions that access gbr ? decoding of a pc-relative mov instruction or mova instruction in a delay slot ? transition address: vbr + h'0000 0100 ? transition operations: the pc contents for the preceding delayed bran ch instruction are saved in spc. the sr and r15 contents when this exception occurred are saved in ssr and sgr. exception code h'1a0 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. operation is not guaranteed if an undefined code other than h'fffd is decoded. slot_illegal_instruction_exception() { spc = pc - 2; ssr = sr; sgr = r15; expevt = h'000001a0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 174 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (11) general fpu disable exception ? source: decoding of an fpu instruction* not in a delay slot with sr.fd =1 ? transition address: vbr + h'0000 0100 ? transition operations: the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'800 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. note: * fpu instructions are instructions in whic h the first 4 bits of the instruction code are h'f (but excluding undefined instruction h'fffd), and the lds, sts, lds.l, and sts.l instructions corresponding to fpul and fpscr. general_fpu_disable_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'00000800; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 175 of 1076 sep 24, 2013 (12) slot fpu disable exception ? source: decoding of an fpu instruction in a delay slot with sr.fd =1 ? transition address: vbr + h'0000 0100 ? transition operations: the pc contents for the preceding delayed bran ch instruction are saved in spc. the sr and r15 contents when this exception occurred are saved in ssr and sgr. exception code h'820 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. slot_fpu_disable_exception() { spc = pc - 2; ssr = sr; sgr = r15; expevt = h'00000820; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 176 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (13) user breakpoint trap ? source: fulfilling of a break condition set in the user break controller ? transition address: vbr + h'0000 0100, or dbr ? transition operations: in the case of a post-execution break, the pc contents for the instruction following the instruction at which the breakpoint is set are se t in spc. in the case of a pre-execution break, the pc contents for the instruction at wh ich the breakpoint is set are set in spc. the sr and r15 contents when the break occurred are saved in ssr and sgr. exception code h'1e0 is set in expevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0100. it is also possible to branch to pc = dbr. for details of pc, etc., when a data break is se t, see section 20, user break controller (ubc). user_break_exception() { spc = (pre_execution break? pc : pc + 2); ssr = sr; sgr = r15; expevt = h'000001e0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = (brcr.ubde==1 ? dbr : vbr + h'00000100); }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 177 of 1076 sep 24, 2013 (14) fpu exception ? source: exception due to execution of a floating-point operation ? transition address: vbr + h'0000 0100 ? transition operations: the pc and sr contents for the instruction at which this exception occurred are saved in spc and ssr, and the contents of r15 are saved in sgr. exception code h'120 is set in expevt. the bl, md, and rb bits are set to 1 in sr, an d a branch is made to pc = vbr + h'0100. fpu_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'00000120; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000100; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 178 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 5.6.3 interrupts (1) nmi ? source: nmi pin edge detection ? transition address: vbr + h'0000 0600 ? transition operations: the contents of pc and sr immediately after the instruction at which this interrupt was accepted are saved in spc and ssr, and th e contents of r15 are saved in sgr. exception code h'1c0 is set in intevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to pc = vbr + h'0600. when th e bl bit in sr is 0, this interrupt is not masked by the interrupt mask bits in sr, and is accepted at th e highest priority level. when the bl bit in sr is 1, a software setting can specify whether this interrupt is to be masked or accepted. for details, see section 19 , interrupt controller (intc). nmi() { spc = pc; ssr = sr; sgr = r15; intevt = h'000001c0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000600; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 179 of 1076 sep 24, 2013 (2) irl interrupts ? source: the interrupt mask bit setting in sr is smaller than the irl (3?0) level, and the bl bit in sr is 0 (accepted at instruction boundary). ? transition address: vbr + h'0000 0600 ? transition operations: the pc contents immediately afte r the instruction at which the interrupt is accepted are set in spc. the sr and r15 contents at the time of acceptance are set in ssr and sgr. the code corresponding to the irl (3?0) level is set in intevt. see table 19.5, interrupt exception handling sources and priority order, for the corresponding codes. the bl, md, and rb bits are set to 1 in sr, and a branch is made to vbr + h'0600. the acceptance level is not set in the interrupt mask bits in sr. when the bl bit in sr is 1, the interrupt is masked. for details, see section 19, interrupt controller (intc). irl() { spc = pc; ssr = sr; sgr = r15; intevt = h'00000200 ~ h'000003c0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000600; }
section 5 exceptions SH7750, SH7750s, SH7750r group page 180 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (3) peripheral module interrupts ? source: the interrupt mask bit setting in sr is smaller than the peripheral module (h-udi, gpio, dmac, tmu, rtc, sci, scif, wdt, or ref) interrupt level, and the bl bit in sr is 0 (accepted at inst ruction boundary). ? transition address: vbr + h'0000 0600 ? transition operations: the pc contents immediately afte r the instruction at which the interrupt is accepted are set in spc. the sr and r15 contents at the tim e of acceptance are set in ssr and sgr. the code corresponding to the interrupt source is set in intevt. the bl, md, and rb bits are set to 1 in sr, and a branch is made to vbr + h'0600. the module interrupt levels should be set as values between b'0000 and b'1111 in the interrupt priority registers (ipra?iprc) in the interrupt controller. for details, see section 19, interrupt controller (intc). module_interruption() { spc = pc; ssr = sr; sgr = r15; intevt = h'00000400 ~ h'00000b80; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'00000600; }
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 181 of 1076 sep 24, 2013 5.6.4 priority order with multiple exceptions with some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. care is required in these cases, as the exception priority order differs from the normal order. 1. instructions that make two accesses to memory with mac instructions, memory-to-memory arithmetic/logic instructions, and tas instructions, two data transfers are performed by a single instruction, and an exception will be detected for each of these data transfers. in these cases, therefor e, the following order is used to determine priority. a. data address error in first data transfer b. tlb miss in first data transfer c. tlb protection violation in first data transfer d. initial page write exception in first data transfer e. data address error in second data transfer f. tlb miss in second data transfer g. tlb protection violation in second data transfer h. initial page write exception in second data transfer 2. indivisible delayed branch instruction and delay slot instruction as a delayed branch instruction and its associated delay slot instruction are indivisible, they are treated as a single instructi on. consequently, the priority order for exceptions that occur in these instructions differs from the usual priority order. the priority order shown below is for the case where the delay slot instru ction has only one data transfer. a. a check is performed for the interrupt type and reexecution type exceptions of priority levels 1 and 2 in the delayed branch instruction. b. a check is performed for the interrupt type and reexecution type exceptions of priority levels 1 and 2 in the delay slot instruction. c. a check is performed for the completion type exception of priority level 2 in the delayed branch instruction. d. a check is performed for the completion type exception of priority level 2 in the delay slot instruction. e. a check is performed for priority level 3 in the delayed branch instruction and priority level 3 in the delay slot instruction. (there is no priority ranking between these two.) f. a check is performed for priority level 4 in the delayed branch instruction and priority level 4 in the delay slot instruction. (there is no priority ranking between these two.)
section 5 exceptions SH7750, SH7750s, SH7750r group page 182 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 if the delay slot instruction has a second data transfer, two checks are performed in step b, as in 1 above. if the accepted exception (the highest-priority exception) is a delay slot instruction re- execution type exception, the branch instru ction pr register write operation (pc pr operation performed in bsr, bsrf, jsr) is inhibited. 5.7 usage notes 1. return from exception handling a. check the bl bit in sr with software. if spc and ssr have been saved to external memory, set the bl bit in sr to 1 before restoring them. b. issue an rte instruction. wh en rte is executed, the spc c ontents are set in pc, the ssr contents are set in sr, and branch is made to the spc address to return from the exception handling routine. 2. if a general exception or inte rrupt occurs when sr.bl = 1 a. general exception when a general exception other than a user br eak occurs, a manual reset is executed. the value in expevt at this time is h'0000 0020; the value of the spc and ssr registers is undefined. b. interrupt if an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the bl bit in sr has been cleared to 0 by software. if a nonmaskable interrupt (nmi) occurs, it can be held pending or accepted accord ing to the setting made by software. in the sleep or standby state, however, an interrupt is accepted even if the bl bit in sr is set to 1. 3. spc when an exception occurs a. re-execution type general exception the pc value for the instruction in which the general exception occurred is set in spc, and the instruction is re-executed after returning from exception handling. if an exception occurs in a delay slot instruction, however, the pc value for the delay slot instruction is saved in spc regardless of whether or no t the preceding delayed branch instruction condition is satisfied. b. completion type general exception or interrupt the pc value for the instruction following that in which the general exception occurred is set in spc. if an exception occurs in a branch instruction with delay slot, however, the pc value for the branch destination is saved in spc.
SH7750, SH7750s, SH7750r group section 5 exceptions r01uh0456ej0702 rev. 7.02 page 183 of 1076 sep 24, 2013 4. an exception must not be generated in an rte instruction delay slot, as the operation will be undefined in this case. 5.8 restrictions 1. restrictions on first instruction of exception handling routine ? do not locate a bt, bf, bt/s, bf/s, bra, or bsr instruction at address vbr + h'100, vbr + h'400, or vbr + h'600. ? when the ubde bit in the brcr register is set to 1 and the user break debug support function* is used, do not locate a bt, bf, bt/s , bf/s, bra, or bsr instruction at the address indicated by the dbr register. note: * see section 20.4, user break debug support function.
section 5 exceptions SH7750, SH7750s, SH7750r group page 184 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 185 of 1076 sep 24, 2013 section 6 floating-point unit (fpu) 6.1 overview the floating-point unit (fpu) has the following features: ? conforms to ieee754 standard ? 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) ? two rounding modes: round to nearest and round to zero ? two denormalization modes: flush to zero and treat denormalized number ? six exception sources: fpu error, invalid operation, divide by zero, overflow, underflow, and inexact ? comprehensive instructions: single-precision, double-precision, graphics support, system control when the fd bit in sr is set to 1, the fpu cannot be used, and an attempt to execute an fpu instruction will cause an fpu disable exception. 6.2 data formats 6.2.1 floating-point format a floating-point number consists of the following three fields: ? sign (s) ? exponent (e) ? fraction (f) the fpu can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 31 se f 30 23 22 0 figure 6.1 format of single -precision floati ng-point number
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 186 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 63 se f 62 52 51 0 figure 6.2 format of double -precision floating-point number the exponent is expressed in biased form, as follows: e = e + bias the range of unbiased exponent e is e min ? 1 to e max + 1. the two values e min ? 1 and e max + 1 are distinguished as follows. e min ? 1 indicates zero (both positive and negative sign) and a denormalized number, and e max + 1 indicates positive or negative infinity or a non-number (nan). table 6.1 shows bias, e min , and e max values. table 6.1 floating-point number formats and parameters parameter single-preci sion double-precision total bit width 32 bits 64 bits sign bit 1 bit 1 bit exponent field 8 bits 11 bits fraction field 23 bits 52 bits precision 24 bits 53 bits bias +127 +1023 e max +127 +1023 e min ?126 ?1022 floating-point number value v is determined as follows: if e = e max + 1 and f 0, v is a non-number (nan) irrespective of sign s if e = e max + 1 and f = 0, v = (?1) s (infinity) [positive or negative infinity] if e min e e max , v = (?1) s 2 e (1.f) [normalized number] if e = e min ? 1 and f 0, v = (?1) s 2 emin (0.f) [denormalized number] if e = e min ? 1 and f = 0, v = (?1) s 0 [positive or negative zero]
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 187 of 1076 sep 24, 2013 table 6.2 shows the ranges of the various numbers in hexadecimal notation. table 6.2 floating-point ranges type single-precision double-precision signaling non-numbe r h'7fffffff to h'7fc00000 h'7fffffff ffffffff to h'7ff80000 00000000 quiet non-number h'7fbfffff to h' 7f800001 h'7ff7ffff ffffffff to h'7ff00000 00000001 positive infinity h'7f800000 h'7ff00000 00000 positive normalized number h'7f7fffff to h'00800000 h' 7fefffff ffffffff to h'00100000 00000000 positive denormalized number h'007fffff to h'00000001 h' 000fffff ffffffff to h'00000000 00000001 positive zero h'00000000 h'00000000 00000000 negative zero h'80000000 h'80000000 00000000 negative denormalized number h'80000001 to h'807fffff h'800 00000 00000001 to h'800fffff ffffffff negative normalized number h'80800000 to h'ff7fffff h' 80100000 0000 0000 to h'ffefffff ffffffff negative infinity h'ff 800000 h'fff00000 00000000 quiet non-number h'ff800001 to h'ffb fffff h'fff00000 00000001 to h'fff7ffff ffffffff signaling non-number h'ffc00000 to h'ffffffff h'fff80000 00000000 to h'ffffffff ffffffff 6.2.2 non-numbers (nan) figure 6.3 shows the bit pattern of a non-number (nan). a value is nan in the following case: ? sign bit: don't care ? exponent field: all bits are 1 ? fraction field: at least one bit is 1 the nan is a signaling nan (snan) if the msb of the fraction field is 1, and a quiet nan (qnan) if the msb is 0.
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 188 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 31 x 11111111 nxxxxxxxxxxxxxxxxxxxxxx 30 23 22 0 n = 1: snan n = 0: qnan figure 6.3 single-precision nan bit pattern an snan is input in an operation, except copy, fabs, and fneg, that generates a floating-point value. ? when the en.v bit in the fpscr register is 0, the operation result (output) is a qnan. ? when the en.v bit in the fpscr register is 1, an invalid operation exception will be generated. in this case, the contents of the operation destination register are unchanged. if a qnan is input in an operation that generates a floating-point value, and an snan has not been input in that operation, the output will always be a qnan irrespective of the setting of the en.v bit in the fpscr register. an exception will not be generated in this case. the qnan values generated by the fpu as operation results are as follows: ? single-precision qnan: h'7fbfffff ? double-precision qnan: h'7ff7ffff ffffffff see the individual instruction descriptions for details of floating-point operations when a non- number (nan) is input. 6.2.3 denormalized numbers for a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. when the dn bit in the fpu's status register f pscr is 1, a denormalized number (source operand or operation result) is always flushed to 0 in a floating-point operation that generates a value (an operation other than copy, fneg, or fabs). when the dn bit in fpscr is 0, a denormalized number (source operand or operation result) is processed as it is. see the individual instruction descriptions for details of floating-point operations when a denormalized number is input.
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 189 of 1076 sep 24, 2013 6.3 registers 6.3.1 floating-point registers figure 6.4 shows the floating-point register conf iguration. there are thirty-two 32-bit floating- point registers, referenced by specifying fr0?fr15, dr0/2/4/6/8/10/12/14, fv0/4/8/12, xf0? xf15, xd0/2/4/6/8/10/12/14, or xmtrx. 1. floating-point registers, fpri_bankj (32 registers) fpr0_bank0?fpr15_bank0 fpr0_bank1?fpr15_bank1 2. single-precision floating-point registers, fri (16 registers) when fpscr.fr = 0, fr0?fr15 in dicate fpr0_bank0?fpr15_bank0; when fpscr.fr = 1, fr0?fr15 in dicate fpr0_bank1?fpr15_bank1. 3. double-precision floating-point registers, dri (8 registers): a dr register comprises two fr registers dr0 = {fr0, fr1}, dr2 = {fr2, fr3}, dr4 = {fr4, fr5}, dr6 = {fr6, fr7}, dr8 = {fr8, fr9}, dr10 = {fr10, fr11}, dr12 = {fr12, fr13}, dr14 = {fr14, fr15} 4. single-precision floating-point vector registers, fvi (4 registers): an fv register comprises four fr registers fv0 = {fr0, fr1, fr2, fr3}, fv4 = {fr4, fr5, fr6, fr7}, fv8 = {fr8, fr9, fr10, fr11}, fv 12 = {fr12, fr13, fr14, fr15} 5. single-precision floating-point extended registers, xfi (16 registers) when fpscr.fr = 0, xf0?xf15 in dicate fpr0_bank1?fpr15_bank1; when fpscr.fr = 1, xf0?xf15 in dicate fpr0_bank0?fpr15_bank0. 6. double-precision floating-point extended registers, xdi (8 registers): an xd register comprises two xf registers xd0 = {xf0, xf1}, xd2 = {xf2, xf3}, xd4 = {xf4, xf5}, xd6 = {xf6, xf7}, xd8 = {xf8, xf9}, xd10 = {xf10, xf11}, xd12 = {xf12, xf13}, xd14 = {xf14, xf15}
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 190 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 7. single-precision floating-point extended register matrix: xmtrx xmtrx comprises all 16 xf registers xmtrx = xf0 xf4 xf8 xf12 xf1 xf5 xf9 xf13 xf2 xf6 xf10 xf14 xf3 xf7 xf11 xf15 fpr0 _bank0 fpr1_bank0 fpr2_bank0 fpr3_bank0 fpr4_bank0 fpr5_bank0 fpr6_bank0 fpr7_bank0 fpr8_bank0 fpr9_bank0 fpr10_bank0 fpr11_bank0 fpr12_bank0 fpr13_bank0 fpr14_bank0 fpr15_bank0 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpr0_bank1 fpr1_bank1 fpr2_bank1 fpr3_bank1 fpr4_bank1 fpr5_bank1 fpr6_bank1 fpr7_bank1 fpr8_bank1 fpr9_bank1 fpr10_bank1 fpr11_bank1 fpr12_bank1 fpr13_bank1 fpr14_bank1 fpr15_bank1 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpscr.fr = 0 fpscr.fr = 1 figure 6.4 floating-point registers
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 191 of 1076 sep 24, 2013 6.3.2 floating-point status/control register (fpscr) floating-point status/control register, fpscr (32 bits, initial value = h'0004 0001) 31 22 21 20 19 18 17 12 11 7 6 2 1 0 ? fr sz pr dn cause enable flag rm note: ?: reserved. these bits are always read as 0, and should only be written with 0. ? fr: floating-point register bank fr = 0: fpr0_bank0?fpr15_bank0 are assigned to fr0?fr15; fpr0_bank1? fpr15_bank1 are assigned to xf0?xf15. fr = 1: fpr0_bank0?fpr15_bank0 are assigned to xf0?xf15; fpr0_bank1? fpr15_bank1 are assigned to fr0?fr15. ? sz: transfer size mode sz = 0: the data size of the fmov instruction is 32 bits. sz = 1: the data size of the fmov instruc tion is a 32-bit register pair (64 bits). ? pr: precision mode pr = 0: floating-point instructions are executed as single-precision operations. pr = 1: floating-point instructions are executed as double-precision operations (graphics support instructions are undefined). do not set sz and pr to 1 simultaneously; this setting is reserved. [sz, pr = 11]: reserved (fpu operation instruction is undefined.) ? dn: denormalization mode dn = 0: a denormalized number is treated as such. dn = 1: a denormalized nu mber is treated as zero. ? cause: fpu exception cause field ? enable: fpu exception enable field
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 192 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? flag: fpu exception flag field fpu error (e) invalid operation (v) division by zero (z) overflow (o) underflow (u) inexact (i) cause fpu exception cause field bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 enable fpu exception enable field none bit 11 bit 10 bit 9 bit 8 bit 7 flag fpu exception flag field none bit 6 bit 5 bit 4 bit 3 bit 2 when an fpu operation instruction is executed, the fpu exception cause field is cleared to zero first. when the next fpu exception is occured, the corresponding bits in the fpu exception cause field and fpu excep tion flag field are set to 1. the fpu exception flag field holds the status of the exception gene rated after the field was last cleared. ? rm: rounding mode rm = 00: round to nearest rm = 01: round to zero rm = 10: reserved rm = 11: reserved ? bits 22 to 31: reserved these bits are always read as 0, and should only be written with 0. 6.3.3 floating-point communication register (fpul) information is transferred between the fpu and cpu via the fpul regist er. the 32-bit fpul register is a system register, and is accessed from the cpu side by means of lds and sts instructions. for example, to convert the integer stored in general register r1 to a single-precision floating-point number, the processing flow is as follows: r1 (lds instruction) fpul (single-precision float instruction) fr1
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 193 of 1076 sep 24, 2013 6.4 rounding in a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. therefore, the result of combination instructions such as fmac, ftrv, and fipr will differ from the result when using a basic instructio n such as fadd, fsub, or fmul. rounding is performed once in fmac, but twice in fadd, fsub, and fmul. there are two rounding methods, the method to be used being determined by the rm field in fpscr. ? rm = 00: round to nearest ? rm = 01: round to zero round to nearest: the value is rounded to the nearest expr essible value. if there are two nearest expressible values, the one with an lsb of 0 is selected. if the unrounded value is 2 emax (2 ? 2 ?p ) or more, the result will be infinity with the same sign as the unrounded value. the values of emax and p, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. round to zero: the digits below the round bit of the unrounded value are discarded. if the unrounded value is larger than the maximum expressible absolute value, the value will be the maximum expressibl e absolute value. 6.5 floating-point exceptions fpu-related exceptions are as follows: ? general illegal instruction/slot illegal instruction exception the exception occurs if an fpu instru ction is executed when sr.fd = 1. ? fpu exceptions the exception sources are as follows: ? fpu error (e): when fpscr.dn = 0 and a denormalized number is input ? invalid operation (v): in case of an invalid operation, such as nan input ? division by zero (z): division with a zero divisor ? overflow (o): when the operation result overflows ? underflow (u): when the operation result underflows ? inexact exception (i): when overflow, underflow, or rounding occurs
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 194 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 the fpscr cause field contains bits corresponding to all of above sources e, v, z, o, u, and i, and the fpscr flag and enable fields contain bits corresponding to sources v, z, o, u, and i, but not e. thus, fpu errors cannot be disabled. when an exception source occurs, the corresponding bit in the cause field is set to 1, and 1 is added to the corresponding bit in the flag field. when an exception source does not occur, the corresponding bit in the cause field is cleared to 0, but the corresponding bit in the flag field remains unchanged. ? enable/disable exception handling the fpu supports enable exception handling and disable exception handling. enable exception handling is initiated in the following cases: ? fpu error (e): fpscr.dn = 0 and a denormalized number is input ? invalid operation (v): fpscr.en.v = 1 and (i nstruction = ftrv or invalid operation) ? division by zero (z): fpscr.en.z = 1 and division with a zero divisor ? overflow (o): fpscr.en.o = 1 and instruction with possibility of operation result overflow ? underflow (u): fpscr.en.u = 1 and instruction with possibility of operation result underflow ? inexact exception (i): fpscr.en.i = 1 and instruction with possibility of inexact operation result for information on these possibilities, see the indi vidual instruction descriptions in chapter 9 of the sh-4 software manual. the particulars differ demanding on the instruction. all exception events that originate in the fpu are assigned as the same exception event. the meaning of an exception is determined by soft ware by reading system register fpscr and interpreting the information it contains. if no bits are set in the cause field of fpscr when one or more of bits o, u, i, and v (in case of ftrv only) are set in the enable field, this indicates that an actual exception source is not generated. also, the destination register is not changed by any enable exception handling operation. except for the above, the fpu disables exception handling. in all processing, the bit corresponding to source v, z, o, u, or i is set to 1, and disable exception handling is provided for each exception. ? invalid operation (v): qnan is generated as the result. ? division by zero (z): infinity with the same sign as the unrounded value is generated.
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 195 of 1076 sep 24, 2013 ? overflow (o): when rounding mode = rz, the maximum normal ized number, with th e same sign as the unrounded value, is generated. when rounding mode = rn, infinity with the same sign as the unrounded value is generated. ? underflow (u): when fpscr.dn = 0, a denormalized number wi th the same sign as the unrounded value, or zero with the same sign as the unrounded value, is generated. when fpscr.dn = 1, zero with the same sign as the unrounded value, is generated. ? inexact exception (i): an inexact result is generated. 6.6 graphics support functions the fpu supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 geometric operation instructions geometric operation instructions perform approximate-value computations. to enable high-speed computation with a minimum of hardware, the fp u ignores comparatively small values in the partial computation results of four multiplications. consequently, the error shown below is produced in the result of the computation: maximum error = max (individ ual multiplication result 2 ?min (number of multiplier significant digits?1, number of multiplicand significant digits?1) ) + max (result value 2 ?23 , 2 ?149 ) the number of significant digits is 24 for a norm alized number and 23 fo r a denormalized number (number of leading zeros in the fractional part). in future version of superh risc engine family, the above error is guaranteed, but the same result as SH7750 is not guaranteed. fipr fvm, fvn (m, n: 0, 4, 8, 12): this instruction is basically used for the following purposes: ? inner product (m n): this operation is generally used for surface/r ear surface determination for polygon surfaces. ? sum of square of elements (m = n): this operation is generally used to find the length of a vector.
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 196 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 since approximate-value computations are performed to enable high-speed computation, the inexact exception (i) bit in the cause field and flag field is always set to 1 when an fipr instruction is executed. therefore, if the corresponding bit is set in the enable field, enable exception handling will be executed. ftrv xmtrx, fvn (n: 0, 4, 8, 12): this instruction is basically used for the following purposes: ? matrix (4 4) ? vector (4): this operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). since affine transformation processing for angle + parallel movement basically requires a 4 4 matrix, the fpu supports 4-dimensional operations. ? matrix (4 4) matrix (4 4): this operation requires the execution of four ftrv instructions. since approximate-value computations are performed to enable high-speed computation, the inexact exception (i) bit in the cause field and flag field is always set to 1 when an ftrv instruction is executed. therefore, if the corresponding bit is set in the enable field, enable exception handling will be executed. for the same reason, it is not possible to check all data types in the registers beforehand when executing an ftrv instruction. if the v bit is set in the enable field, enable exception handling will be executed. frchg: this instruction modifies banked registers. for example, when the ftrv instruction is executed, matrix elements must be set in an arra y in the background bank. however, to create the actual elements of a translation matrix, it is easie r to use registers in the foreground bank. when the ldc instruction is used on fpscr, this instru ction expends 4 to 5 cycles in order to maintain the fpu state. with the frchg instruction, an fpscr.fr bit modification can be performed in one cycle. 6.6.2 pair single-precision data transfer in addition to the geometric operation instructions , the fpu also supports high-speed data transfer instructions. when fpscr.sz = 1, the fpu can perform data transfer by means of pair single-precision data transfer instructions. ? fmov drm/xdm, drn/xdrn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) ? fmov drm/xdm, @rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 197 of 1076 sep 24, 2013 these instructions enable two single-precision (2 32-bit) data items to be transferred; that is, the transfer performance of thes e instructions is doubled. ? fschg this instruction changes the value of the sz bit in fpscr, enabling fast switching between use and non-use of pair single-precision data transfer. programming note: when fpscr.sz = 1 and big-endian mode is used, fmov can be used for a double-precision floating-point load or store. in little-endian mode, a double-precision floating-point load or store requires execution of two 32-bit data size operations with fpscr.sz = 0. 6.7 usage notes 6.7.1 rounding mode and underflow flag when using the round to nearest rounding mode, the underflow flag may not be set in cases defined as underflow by the ieee754 standard. under the ieee754 standard, when the round to nearest rounding mode is used and infinite- precision operation result x is (i) or (ii) (single-precision) or (iii) or (iv) (double-precision), there are cases where ?the result after rounding is a normalized number, but an underflow results.? in such cases where ?the result after rounding is a normalized number, but an underflow results,? the fpu does not set the underflow flag to 1. in these cases the operation result, the value written to frn, is correct. also, if an fpu exception oc curs, the underflow flag is not set to 1 but the inexact flag is set to 1 in such cases. generation of fpu exceptions can be enabled by setting the enable field to 1. (i) h'007fffff < x < h'00800000 (ii) h'807fffff > x > h'80800000 (iii) h'000fffff ffffffff < x < h'00100000 00000000 (iv) h'800fffff ffffffff > x > h'80100000 00000000 examples ? single-precision when fpscr.rm = 00 (round to nearest) and fpscr.pr = 0 (single-precision), and the fmul instruction (h'00fff000 * h'3f000800) is executed.
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 198 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 a. according to ieee754 standard operation result: h'00800000 fpscr: h'0004300c b. fpu operation result: h'00800000 fpscr: h'00041004 ? double-precision when fpscr.rm = 00 (round to nearest) and fpscr.pr = 1 (double-precision), and the fdiv instruction (h'001fffff ffffffff / h'40000000 00000000) is executed. a. according to ieee754 standard operation result: h'00100000 00000000 fpscr: h'000c300c b. fpu operation result: h'00100000 00000000 fpscr: h'000c1004 workarounds 1. use fpscr.rm = 01, that is to say round to zero rather than round to nearest mode. 2. use fpscr.rm = 00, that is to say round to nearest mode, and set the enable field to 1 to enable generation of inexact ex ceptions so that the exception ha ndling routine can be used to check whether or not an underflow has occurred. 6.7.2 setting of overflow flag by fipr or ftrv instruction when the maximum error produced by the fipr or ftrv instruction exceeds the maximum value expressible as a normalized nu mber (h'7f7fffff), the overflow fl ag may be set, even through the operation result is a positive or ne gative zero (h'00000000 or h'80000000). example: the operation result (fr7) after executi ng the instruction fipr fv4, fv0 is h'00000000 (positive zero), but the overflow flag may be set nevertheless. fpscr = h'00040001 fr0 = h'ff7ef631 , fr1 = h80000000 , fr2 = h'8087f451 , fr3 = h'7f7ef631 fr4 = h'7f7ef631 , fr5 = h'0087f451 , fr6 = h'7f7ef631 , fr7 = h'7f7ef631 workaround: avoid using the fipr and ftrv instructions, and use the fadd, fmul, and fmac instructions instead.
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 199 of 1076 sep 24, 2013 6.7.3 sign of operation result when using fipr or ftrv instruction when two or more data items used in an operation by the fipr or ftrv instruction are infinity, and all of the infinity items in the multiplication results have the same sign, the sign of the operation result may be incorrect. workarounds 1. do not use infinity. if conditions a. to c. below are satisfied, infinity is never used in operations. a. use round to zero (fpscr. rm = 01) as the rounding mode. b. do not divide by zero. c. do not transfer a value of positive or negative infinity to fr0 to fr15 or to xf0 to xf15. 2. avoid using the fipr and ftrv instructions, and use the fadd, fmul, and fmac instructions instead. 6.7.4 notes on double-precision fa dd and fsub instructions description: if the input data for a double-precision fadd instruction or a double-precision fsub instruction satisfies all of the conditions li sted below, the inexact bits (fpscr.flag.i and fpscr.cause.i) may not be set even through the operation result is inexact. condition 1: the operation instruction is a double-precision fadd instruction or a double- precision fsub instruction. condition 2: the difference between the drn and drm exponents is between 43 and 50. condition 3: at least one of bits 31 to 24 of the mantissa portion of whichever of drn and drm has the smaller absolute value is 1. condition 4: bits 23 to 0 of the mantissa portion of whichever of drn and drm has the smaller absolute value are all 0. condition 5: bits 40 to 32 of the mantissa portion of whichever of drn and drm has the smaller absolute value are all 0. in addition, the result of an operation meeting the above conditions may have a rounding error. specifically, in a case where the closest expressibl e value less than the unro unded value should be selected, the closest expressible value greater than the unrounde d value is selected instead. conversely, in a case wher e the closest expressible value greater than the unrounded value should be selected, the closest expressi ble value less than the unrou nded value is selected instead.
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 200 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 example: if the double-precision fsub instruction (fsub dr0, dr2) is executed with input data dr0 = h'c1f00000 80000000, dr2 = h'c4b250d2 0cc1fb74, and fpscr = h'000c0001, the correct operation result is dr2 = h'c4b250d2 0cc1f973, and fpscr.flag.i and fpscr.cause.i should be set to 1. however, the result actually produced by the fpu is dr2 = h'c4b250d2 0cc1f974, and fpscr.flag.i and fpscr.cause.i are not set to 1. effects: in addition to the problem described above , the numerical size of the result of the operation may contain a minute operation error equivalent to 1/256 of the lsb of the mantissa of the unrounded value. this is can be described as within the scope of the subsequent rounding mechanism. strictly speaking, it consists of the following. a: the infinite-preci sion operation result b: the closest expressible value less than a c: the closest expressible value greater than a d: the operation result when a is rounded correctly e: the operation result when a is rounded by the fpu ? the rounding error when rounding is performed correctly in round to nearest mode is: 0 | d ? a | (1/2) (c ? b ) and the rounding error when rounding is performed by the fpu is: 0 | e ? a | < (129/256) ( c ? b ) if c ? b is considered the lsb of the mantissa, the range of rounding error is equivalent to 1/256 of the lsb of the mantissa of the correctly rounded value. ? the rounding error when rounding is performed correctly in round to zero mode is: ( ? 1) (c ? b) < | d |?| a | 0 and the rounding error when rounding is performed by the fpu is: ( ? 1) (c ? b) < | e |?| a | < (1/256) (c ? b) if c ? b is considered the lsb of the mantissa, the range of rounding error is equivalent to 1/256 of the lsb of the mantissa of the correctly rounded value. 6.7.5 notes on fpu double-precision opera tion instructions (SH7750 only) the operation result may be incorrect when de normalized numbers are us ed as input with a double-precision fdiv, fadd, fsub, or fmul instruction, even in the mode capable of handling denormalized numbers.
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 201 of 1076 sep 24, 2013 this problem affects applications in science and engineering wher e extreme precision is required. it is limited to cases where double-precision floating-point instructions are used to handle denormalized numbers. the problem does not affect cases where double-precision floating-point instructions are used but denormalized numbers ar e treated as zero, or cas es where only single- precision floating-point instructions are used. examples: the problem manifests itself in either of tw o ways. in one type of case a. and b. the result is incorrect when denormalized numbers are used as input. in the other c. the result is incorrect when a denormalized numb er and qnan are used as input. a. when the input for a double-precision fdiv instruction includes a denormalized number, an incorrect result of zero or infinity may be generated. b. when the input for a double-precision fmul instruction includes a denormalized number, an incorrect result of infinity may be generated. c. when the input for a double-precision fdiv, fadd, fsub, or fmul instruction consists of a denormalized number and qnan, the result may be incorrect. effects: the effect of the problem is greatest in cases where denor malized numbers are used as input with a double-precision fdiv or fmul instru ction, and an incorrect value is written to a register as a result (a or b). in particular, math ematically inappropriate values may be generated, such as denormalized number / denormalized number = 0 or denormalized number / 0 = 0. workarounds: ordinarily, workaround 1. may be used. workaround 2. is for calculations in science or engineering applicati ons where extreme precision and the use of denormalized numbers are necessary. 1. when using double-precision floating-point instructions, set fpscr.dn to 1 to select the mode in which denormalized numbers are treated as 0. this workaround does not result in any decrease in performance. 2. avoid cases where using denorm alized numbers as input produce incorrect results a. and b. by means of software. refer to ?modifying software? below for details. (i) save the contents of the source and destination registers (drn). (ii) when a double-precision fdiv instruction gene rates a result of zero or infinity, call a user- specified function for processing denormalized numbers. use a trap routine to avoid cases where an incorrect result is generated when using a denormalized number and qnan as input c.. re fer to ?modifying a trap routine? below for details. (i) when the input for a double-precision fdiv, fadd, fsub, or fmul instruction consists of a denormalized number and qnan, use a trap routine to write the value of qnan (h'7ff7ffff_ffffffff) to th e destination register.
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 202 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 details definitions: the data patterns that cause the problem are defined below. item (a) to (d) in the tables correspond to the following data patterns. ? double-precision deno rmalized number (a) h'00000000_xxxxxxxx or h'80000000_xxxxxxxx (x: 0 or 1) however, h'xxxxxxxx != h'00000000 ? double-precision deno rmalized number (b) h'000yyyyy_xxxxxxxx or h'800yyyyy_xxxxxxxx (x: 0 or 1) however, h'yyyyy != h'00000 ? double-precision qnan (c) however, h'xxxxxxxx != h'00000000 ? double-precision qnan (d) note: as defined h'7ffxxxxx_xxxxxxxx or h'fffxxxxx_xxxxxxxx (x: 0 or 1) however, h'xxxxx_xxxxxxxx != h'00000_00000000 incorrect operation results: table 6.3 lists instructions and data combinations that produce incorrect operation results when fpscr.dn = i' b0 (mode in which denormalized numbers are treated as denormalized numbers). input items (a) to (c) are the data patterns defined in ?definitions? above, and problem types (1) to (7) correspond to the incorrect operation results classified in tables 6.4 to 6.6. the incorrect operation results fo r problem types (1), (2), (3), and (7) are zero or infinity. in problem types (4), (5), and (6), an fpu error exception trap is generated and no value is output for qnan. case (a) corresponds to problem types (1), (2), and (3); case (b) corresponds to (7); and case (c) corresponds to (4), (5), and (6).
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 203 of 1076 sep 24, 2013 table 6.3 incorrect operation result input problem type instruction drm drn sh-4 expected value (1) fdiv +0/?0 (a) denorm +0/?0 dz (a) denorm +0/?0 (2) fdiv (a) denorm (a) denorm +0/?0 fpu error (3) fdiv (a) denorm +inf /?inf +inf/?inf fpu error (c) qnan (a) denorm (c) qnan (b) denorm (4) fdiv (b) denorm (c) qnan fpu error qnan * (c) qnan denorm (5) fadd/fsub denorm (c) qnan fpu error qnan * (c) qnan (b) denorm (6) fmul (b) denorm (c) qnan fpu error qnan * (a) denorm +inf/?inf (7) fmul +inf/?inf (a) denorm +inf/?inf fpu error note: * qnan: h'7ff7ffff_ffffffff the above operations complete normally when fpscr.dn = 1.
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 204 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 special cases involving double-precision fdiv , fadd, fsub, and fmul instructions are summarized below. : shaded portion indicates normal operation. : unshaded portion indicates incorrect oper ation result, and fpu output values are listed table 6.4 fdiv drm, drn (drn/drm drn) drn drm norm div dz 0 +0 0 invalid +0 ? 0 ? 0 ? 0 +0 +inf inf +inf inf invalid ? inf inf +inf (a) positive denorm + 0 (1) ? 0 (1) (a) negative denorm error ? 0 (1) + 0 (1) error (b) denorm dz (c) qnan qnan (d) qnan snan invalid norm +0 ? 0 +inf ? inf (a) positive denorm (a) negative denorm (b) denorm (c) qnan (d) qnan snan ? 0 (2) +0 (2) + 0 (2) ? 0 (2) ? 0 (2) error (4) +0 (2) + 0 (2) ? 0 (2) (3) +inf (3) ? inf (3) ? inf (3) +inf error (4)
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 205 of 1076 sep 24, 2013 table 6.5 fadd drm, drn (drn + drm drn) fsub drm, drn (drn ? drm drn) drn drm norm add ? inf +0 +0 ? 0 ? 0 +inf +inf invalid ? inf ? inf invalid ? inf (a) positive denorm (a) negative denorm error (b) denorm (c) qnan qnan (d) qnan snan invalid norm +0 ? 0 +inf ? inf (a) positive denorm (a) negative denorm (b) denorm (c) qnan (d) qnan snan error (5) error (5) table 6.6 fmul drm, drn (drn * drm drn) drn drm norm mul inf +0 0 +0 ? 0 invalid ? 0 ? 0 +0 +inf inf invalid +inf ? inf ? inf ? inf +inf (a) positive denorm +inf (7) ? inf (7) (a) negative denorm error ? inf (7) +inf (7) (b) denorm (c) qnan qnan (d) qnan snan invalid norm +0 ? 0 +inf ? inf (a) positive denorm (a) negative denorm (b) denorm (c) qnan (d) qnan snan error (6) +inf (7) ? inf (7) ? inf (7) +inf (7) error (6)
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 206 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 modifying software problem types (1), (2), and (3): deal with problem types (1), (2), and (3) in table 6.3 using software based on the flowchart below. adjust the source operands by multiplying them by 2 1536 , then calculate them as normalized numbers. in the case of problem type (1), if the divide by zero exception is enabled, the divide by zero exception trap is generated and the destination register does not change. if the divide by zero exception is disabled, the contents of the destination register become infinity with the sign based on the input operands. is operation result inf or 0? yes no start end save source drn fdiv drm, drn problem type (1), (2), or (3)? yes restore source drn drm 2 1536 , drn 2 1536 fdiv drm, drn no problem type (7): in the case of problem type (7 ) in table 6.3, no fpu er ror occurs. the operation result is correct and there is no need for a software workaround.
SH7750, SH7750s, SH7750r group section 6 floating-point unit (fpu) r01uh0456ej0702 rev. 7.02 page 207 of 1076 sep 24, 2013 modifying a trap routine: for problem types (4), (5), and (6) in table 6.3, add code to the trap routine to check the instruction and input data as indicated in table 6.7 and to write the contents of qnan to the destination register. in this case the value of qnan must always be h'7ff7ffff_ffffffff. table 6.7 trap routine processing input check problem type instruction check drm drn operation result fdiv qnan denorm qnan fdiv qnan denorm qnan (4) fdiv denorm qnan qnan fadd/fsub qnan denorm qnan (5) fadd/fsub denorm qnan qnan fmul qnan denorm qnan (6) fmul denorm qnan qnan
section 6 floating-point unit (fpu) SH7750, SH7750s, SH7750r group page 208 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 209 of 1076 sep 24, 2013 section 7 instruction set 7.1 execution environment pc: at the start of instruction ex ecution, pc indicates the addres s of the instruction itself. data sizes and data types: the sh-4's instruction set is implemented with 16-bit fixed-length instructions. the sh-4 can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64- bit) data sizes for memory access. single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. double-precision floating-point data (64 bits) can be moved to and from memory using longword size. when a double-precision floating-point operation is specified (fpscr.pr = 1), the result of an operati on using quadword access will be undefined. when the sh-4 moves byte-size or word-size data from memory to a register, the data is sign-extended. load-store architecture: the sh-4 features a load-store ar chitecture in which operations are basically executed using registers. except for bit-manipulation operations such as logical and that are executed directly in memory, operands in an operati on that requires memory access are loaded into registers and the operatio n is executed between the registers. delayed branches: except for the two branch instructions bf and bt, the sh-4's branch instructions and rte are delayed branches. in a delayed branch, the instruction following the branch is executed before the branch destination instruction. this execution slot following a delayed branch is called a delay slot. for example, the bra execution sequence is as follows: static sequence dynamic sequence bra target bra target add r1, r0 next_2 add r1, r0 target_instr add in delay slot is executed before branching to target delay slot: an illegal instruction exception may occur when a specific instruction is executed in a delay slot. see section 5, exceptions. the instruction following bf/s or bt/s for which the branch is not taken is also a delay slot instruction. t bit: the t bit in the status register (sr) is used to show the result of a compare operation, and is referenced by a conditional branch instruction. an example of the use of a conditional branch instruction is shown below.
section 7 instruction set SH7750, SH7750s, SH7750r group page 210 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 add #1, r0 ; t bit is not changed by add operation cmp/eq r1, r0 ; if r0 = r1, t bit is set to 1 bt target ; branches to target if t bit = 1 (r0 = r1) in an rte delay slot, status register (sr) bits ar e referenced as follows. in instruction access, the md bit is used before modification, and in data access, the md bit is accessed after modification. the other bits?s, t, m, q, fd, bl, and rb?after modification are used for delay slot instruction execution. the stc and stc.l sr inst ructions access all sr bits after modification. constant values: an 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a pc-relative load instruction. mov.w @(disp, pc), rn mov.l @(disp, pc), rn there are no pc-relative load instructions for floati ng-point operations. however, it is possible to set 0.0 or 1.0 by using the fldi0 or fldi1 instruction on a single-precision floating-point register.
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 211 of 1076 sep 24, 2013 7.2 addressing modes addressing modes and effective address calculation methods are shown in table 7.1. when a location in virtual memory space is accessed (mmucr. at = 1), the effective address is translated into a physical memory addr ess. if multiple virtual memory space systems are selected (mmucr.sv = 0), the least significant bit of pt eh is also referenced as the access asid. see section 3, memory management unit (mmu). table 7.1 addressing modes and effective addresses addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn ea (ea: effective address) register indirect with post- increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. rn rn 1/2/4/8 + rn + 1/2/4/8 rn ea after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn quadword: rn + 8 rn register indirect with pre- decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. rn 1/2/4/8 rn ? 1/2/4/8 ? rn ? 1/2/4/8 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn quadword: rn ? 8 rn rn ea (instruction executed with rn after calculation)
section 7 instruction set SH7750, SH7750s, SH7750r group page 212 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 addressing mode instruction format effective address calculation method calculation formula register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn rn + disp 1/2/4 + 1/2/4 disp (zero-extended) byte: rn + disp ea word: rn + disp 2 ea longword: rn + disp 4 ea indexed register indirect @(r0, rn) effective address is sum of register rn and r0 contents. rn r0 rn + r0 + rn + r0 ea gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr 1/2/4 gbr + disp 1/2/4 + disp (zero-extended) byte: gbr + disp ea word: gbr + disp 2 ea longword: gbr + disp 4 ea indexed gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr r0 gbr + r0 + gbr + r0 ea
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 213 of 1076 sep 24, 2013 addressing mode instruction format effective address calculation method calculation formula pc-relative with displacement @(disp:8, pc) effective address is pc+4 with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc h'fffffffc pc + 4 + disp 2 or pc & h'fffffffc + 4 + disp 4 + 4 2/4 + & * disp (zero-extended) * with lon g word operand word: pc + 4 + disp 2 ea longword: pc & h'fffffffc + 4 + disp 4 ea pc-relative disp:8 effective address is pc+4 with 8-bit displacement disp added after being sign-extended and multiplied by 2. 2 + disp (si g n-extended) 4 + pc pc + 4 + disp 2 pc + 4 + disp 2 branch- target
section 7 instruction set SH7750, SH7750s, SH7750r group page 214 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 addressing mode instruction format effective address calculation method calculation formula pc-relative disp:12 effective address is pc+4 with 12-bit displacement disp added after being sign-extended and multiplied by 2. 2 + disp (si g n-extended) 4 + pc pc + 4 + disp 2 pc + 4 + disp 2 branch- target rn effective address is sum of pc+4 and rn. pc 4 rn + + pc + 4 + rn pc + 4 + rn branch-target immediate #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. ? note: for the addressing modes below that use a di splacement (disp), the assembler descriptions in this manual show the value before scaling ( 1, 2, or 4) is performed according to the operand size. this is done to clarify the oper ation of the chip. refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, rn) ; register indirect with displacement @ (disp:8, gbr) ; gbr i ndirect with displacement @ (disp:8, pc) ; pc-relative with displacement disp:8, disp:1 2 ; pc-relative
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 215 of 1076 sep 24, 2013 7.3 instruction set table 7.2 shows the notation used in the following sh instruction list. table 7.2 notation used in instruction list item format description instruction mnemonic op.sz src, dest op: operation code sz: size src: source dest: source and/or destination operand summary of operation , : transfer direction (xx): memory operand m/q/t: sr flag bits &: logical and of individual bits |: logical or of individual bits : logical exclusive-or of individual bits ~: logical not of individual bits <>n: n-bit shift instruction code msb ? lsb mmmm: register number (rm, frm) nnnn: register number (rn, frn) 0000: r0, fr0 0001: r1, fr1 : 1111: r15, fr15 mmm: register number (drm, xdm, rm_bank) nnn: register number (drm, xdm, rn_bank) 000: dr0, xd0, r0_bank 001: dr2, xd2, r1_bank : 111: dr14, xd14, r7_bank mm: register number (fvm) nn: register number (fvn) 00: fv0 01: fv4 10: fv8 11: fv12 iiii: immediate data dddd: displacement privileged mode ?privileged? means the instruction can only be executed in privileged mode. t bit value of t bit after instruction execution ?: no change note: scaling ( 1, 2, 4, or 8) is executed according to the size of the instruction operand(s).
section 7 instruction set SH7750, SH7750s, SH7750r group page 216 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 7.3 fixed-point transfer instructions instruction operation instruction code privileged t bit mov #imm,rn imm sign extension rn 1110nnnniiiiiiii ? ? mov.w @(disp,pc),rn (disp 2 + pc + 4) sign extension rn 1001nnnndddddddd ? ? mov.l @(disp,pc),rn (disp 4 + pc & h'fffffffc + 4) rn 1101nnnndddddddd ? ? mov rm,rn rm rn 0110nnnnmmmm0011 ? ? mov.b rm,@rn rm (rn) 0010nnnnmmmm0000 ? ? mov.w rm,@rn rm (rn) 0010nnnnmmmm0001 ? ? mov.l rm,@rn rm (rn) 0010nnnnmmmm0010 ? ? mov.b @rm,rn (rm) sign extension rn 0110nnnnmmmm0000 ? ? mov.w @rm,rn (rm) sign extension rn 0110nnnnmmmm0001 ? ? mov.l @rm,rn (rm) rn 0110nnnnmmmm0010 ? ? mov.b rm,@-rn rn-1 rn, rm (rn) 0010nnnnmmmm0100 ? ? mov.w rm,@-rn rn-2 rn, rm (rn) 0010nnnnmmmm0101 ? ? mov.l rm,@-rn rn-4 rn, rm (rn) 0010nnnnmmmm0110 ? ? mov.b @rm+,rn (rm) sign extension rn, rm + 1 rm 0110nnnnmmmm0100 ? ? mov.w @rm+,rn (rm) sign extension rn, rm + 2 rm 0110nnnnmmmm0101 ? ? mov.l @rm+,rn (rm) rn, rm + 4 rm 0110nnnnmmmm0110 ? ? mov.b r0,@(disp,rn) r0 (disp + rn) 10000000nnnndddd ? ? mov.w r0,@(disp,rn) r0 (disp 2 + rn) 10000001nnnndddd ? ? mov.l rm,@(disp,rn) rm (disp 4 + rn) 0001nnnnmmmmdddd ? ? mov.b @(disp,rm),r0 (disp + rm) sign extension r0 10000100mmmmdddd ? ? mov.w @(disp,rm),r0 (disp 2 + rm) sign extension r0 10000101mmmmdddd ? ? mov.l @(disp,rm),rn (disp 4 + rm) rn 0101nnnnmmmmdddd ? ? mov.b rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0100 ? ? mov.w rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0101 ? ? mov.l rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0110 ? ? mov.b @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1100 ? ? mov.w @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1101 ? ?
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 217 of 1076 sep 24, 2013 instruction operation instruction code privileged t bit mov.l @(r0,rm),rn (r0 + rm) rn 0000nnnnmmmm1110 ? ? mov.b r0,@(disp,gbr) r0 (disp + gbr) 11000000dddddddd ? ? mov.w r0,@(disp,gbr) r0 (disp 2 + gbr) 11000001dddddddd ? ? mov.l r0,@(disp,gbr) r0 (disp 4 + gbr) 11000010dddddddd ? ? mov.b @(disp,gbr),r0 (disp + gbr) sign extension r0 11000100dddddddd ? ? mov.w @(disp,gbr),r0 (disp 2 + gbr) sign extension r0 11000101dddddddd ? ? mov.l @(disp,gbr),r0 (disp 4 + gbr) r0 11000110dddddddd ? ? mova @(disp,pc),r0 disp 4 + pc & h'fffffffc + 4 r0 11000111dddddddd ? ? movt rn t rn 0000nnnn00101001 ? ? swap.b rm,rn rm swap lower 2 bytes rn 0110nnnnmmmm1000 ? ? swap.w rm,rn rm swap upper/lower words rn 0110nnnnmmmm1001 ? ? xtrct rm,rn rm:rn middle 32 bits rn 0010nnnnmmmm1101 ? ?
section 7 instruction set SH7750, SH7750s, SH7750r group page 218 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 7.4 arithmetic operation instructions instruction operation instruction code privileged t bit add rm,rn rn + rm rn 0011nnnnmmmm1100 ? ? add #imm,rn rn + imm rn 0111nnnniiiiiiii ? ? addc rm,rn rn + rm + t rn, carry t 0011nnnnmmmm1110 ? carry addv rm,rn rn + rm rn, overflow t 0011nnnnmmmm1111 ? overflow cmp/eq #imm,r0 when r0 = imm, 1 t otherwise, 0 t 10001000iiiiiiii ? comparison result cmp/eq rm,rn when rn = rm, 1 t otherwise, 0 t 0011nnnnmmmm0000 ? comparison result cmp/hs rm,rn when rn rm (unsigned), 1 t otherwise, 0 t 0011nnnnmmmm0010 ? comparison result cmp/ge rm,rn when rn rm (signed), 1 t otherwise, 0 t 0011nnnnmmmm0011 ? comparison result cmp/hi rm,rn when rn > rm (unsigned), 1 t otherwise, 0 t 0011nnnnmmmm0110 ? comparison result cmp/gt rm,rn when rn > rm (signed), 1 t otherwise, 0 t 0011nnnnmmmm0111 ? comparison result cmp/pz rn when rn 0, 1 t otherwise, 0 t 0100nnnn00010001 ? comparison result cmp/pl rn when rn > 0, 1 t otherwise, 0 t 0100nnnn00010101 ? comparison result cmp/str rm,rn when any bytes are equal, 1 t otherwise, 0 t 0010nnnnmmmm1100 ? comparison result div1 rm,rn 1-step division (rn rm) 0011nnnnmmmm0100 ? calculation result div0s rm,rn msb of rn q, msb of rm m, m^q t 0010nnnnmmmm0111 ? calculation result div0u 0 m/q/t 0000000000011001 ? 0 dmuls.l rm,rn signed, rn rm mac, 32 32 64 bits 0011nnnnmmmm1101 ? ? dmulu.l rm,rn unsigned, rn rm mac, 32 32 64 bits 0011nnnnmmmm0101 ? ? dt rn rn ? 1 rn; when rn = 0, 1 t when rn 0, 0 t 0100nnnn00010000 ? comparison result
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 219 of 1076 sep 24, 2013 instruction operation instruction code privileged t bit exts.b rm,rn rm sign-extended from byte rn 0110nnnnmmmm1110 ? ? exts.w rm,rn rm sign-extended from word rn 0110nnnnmmmm1111 ? ? extu.b rm,rn rm zero-extended from byte rn 0110nnnnmmmm1100 ? ? extu.w rm,rn rm zero-extended from word rn 0110nnnnmmmm1101 ? ? mac.l @rm+,@rn+ signed, (rn) (rm) + mac mac rn + 4 rn, rm + 4 rm 32 32 + 64 64 bits 0000nnnnmmmm1111 ? ? mac.w @rm+,@rn+ signed, (rn) (rm) + mac mac rn + 2 rn, rm + 2 rm 16 16 + 64 64 bits 0100nnnnmmmm1111 ? ? mul.l rm,rn rn rm macl 32 32 32 bits 0000nnnnmmmm0111 ? ? muls.w rm,rn signed, rn rm macl 16 16 32 bits 0010nnnnmmmm1111 ? ? mulu.w rm,rn unsigned, rn rm macl 16 16 32 bits 0010nnnnmmmm1110 ? ? neg rm,rn 0 ? rm rn 0110nnnnmmmm1011 ? ? negc rm,rn 0 ? rm ? t rn, borrow t 0110nnnnmmmm1010 ? borrow sub rm,rn rn ? rm rn 0011nnnnmmmm1000 ? ? subc rm,rn rn ? rm ? t rn, borrow t 0011nnnnmmmm1010 ? borrow subv rm,rn rn ? rm rn, underflow t 0011nnnnmmmm1011 ? underflow
section 7 instruction set SH7750, SH7750s, SH7750r group page 220 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 7.5 logic operation instructions instruction operation instruction code privileged t bit and rm,rn rn & rm rn 0010nnnnmmmm1001 ? ? and #imm,r0 r0 & imm r0 11001001iiiiiiii ? ? and.b #imm,@(r0,gbr) (r0 + gbr) & imm (r0 + gbr) 11001101iiiiiiii ? ? not rm,rn ~rm rn 0110nnnnmmmm0111 ? ? or rm,rn rn | rm rn 0010nnnnmmmm1011 ? ? or #imm,r0 r0 | imm r0 11001011iiiiiiii ? ? or.b #imm,@(r0,gbr) (r0 + gbr) | imm (r0 + gbr) 11001111iiiiiiii ? tas.b @rn when (rn) = 0, 1 t otherwise, 0 t in both cases, 1 msb of (rn) 0100nnnn00011011 ? test result tst rm,rn rn & rm; when result = 0, 1 t otherwise, 0 t 0010nnnnmmmm1000 ? test result tst #imm,r0 r0 & imm; when result = 0, 1 t otherwise, 0 t 11001000iiiiiiii ? test result tst.b #imm,@(r0,gbr) (r0 + gbr) & imm; when result = 0, 1 t otherwise, 0 t 11001100iiiiiiii ? test result xor rm,rn rn rm rn 0010nnnnmmmm1010 ? ? xor #imm,r0 r0 imm r0 11001010iiiiiiii ? ? xor.b #imm,@(r0,gbr) (r0 + gbr) imm (r0 + gbr) 11001110iiiiiiii ? ?
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 221 of 1076 sep 24, 2013 table 7.6 shift instructions instruction operation instruction code privileged t bit rotl rn t rn msb 0100nnnn00000100 ? msb rotr rn lsb rn t 0100nnnn00000101 ? lsb rotcl rn t rn t 0100nnnn00100100 ? msb rotcr rn t rn t 0100nnnn00100101 ? lsb shad rm,rn when rn 0, rn << rm rn when rn < 0, rn >> rm [msb rn] 0100nnnnmmmm1100 ? ? shal rn t rn 0 0100nnnn00100000 ? msb shar rn msb rn t 0100nnnn00100001 ? lsb shld rm,rn when rn 0, rn << rm rn when rn < 0, rn >> rm [0 rn] 0100nnnnmmmm1101 ? ? shll rn t rn 0 0100nnnn00000000 ? msb shlr rn 0 rn t 0100nnnn00000001 ? lsb shll2 rn rn << 2 rn 0100nnnn00001000 ? ? shlr2 rn rn >> 2 rn 0100nnnn00001001 ? ? shll8 rn rn << 8 rn 0100nnnn00011000 ? ? shlr8 rn rn >> 8 rn 0100nnnn00011001 ? ? shll16 rn rn << 16 rn 0100nnnn00101000 ? ? shlr16 rn rn >> 16 rn 0100nnnn00101001 ? ?
section 7 instruction set SH7750, SH7750s, SH7750r group page 222 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 7.7 branch instructions instruction operation instruction code privileged t bit bf label when t = 0, disp 2 + pc + 4 pc when t = 1, nop 10001011dddddddd ? ? bf/s label delayed branch; when t = 0, disp 2 + pc + 4 pc when t = 1, nop 10001111dddddddd ? ? bt label when t = 1, disp 2 + pc + 4 pc when t = 0, nop 10001001dddddddd ? ? bt/s label delayed branch; when t = 1, disp 2 + pc + 4 pc when t = 0, nop 10001101dddddddd ? ? bra label delayed branch, disp 2 + pc + 4 pc 1010dddddddddddd ? ? braf rn delayed branch, rn + pc + 4 pc 0000nnnn00100011 ? ? bsr label delayed branch, pc + 4 pr, disp 2 + pc + 4 pc 1011dddddddddddd ? ? bsrf rn delayed branch, pc + 4 pr, rn + pc + 4 pc 0000nnnn00000011 ? ? jmp @rn delayed branch, rn pc 0100nnnn00101011 ? ? jsr @rn delayed branch, pc + 4 pr, rn pc 0100nnnn00001011 ? ? rts delayed branch, pr pc 0000000000001011 ? ?
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 223 of 1076 sep 24, 2013 table 7.8 system control instructions instruction operation instruction code privileged t bit clrmac 0 mach, macl 0000000000101000 ? ? clrs 0 s 0000000001001000 ? ? clrt 0 t 0000000000001000 ? 0 ldc rm,sr rm sr 0100mmmm00001110 privileged lsb ldc rm,gbr rm gbr 0100mmmm00011110 ? ? ldc rm,vbr rm vbr 0100mmmm00101110 privileged ? ldc rm,ssr rm ssr 0100mmmm00111110 privileged ? ldc rm,spc rm spc 0100mmmm01001110 privileged ? ldc rm,dbr rm dbr 0100mmmm11111010 privileged ? ldc rm,rn_bank rm rn_bank (n = 0 to 7) 0100mmmm1nnn1110 privileged ? ldc.l @rm+,sr (rm) sr, rm + 4 rm 0100mmmm00000111 privileged lsb ldc.l @rm+,gbr (rm) gbr, rm + 4 rm 0100mmmm00010111 ? ? ldc.l @rm+,vbr (rm) vbr, rm + 4 rm 0100mmmm00100111 privileged ? ldc.l @rm+,ssr (rm) ssr, rm + 4 rm 0100mmmm00110111 privileged ? ldc.l @rm+,spc (rm) spc, rm + 4 rm 0100mmmm01000111 privileged ? ldc.l @rm+,dbr (rm) dbr, rm + 4 rm 0100mmmm11110110 privileged ? ldc.l @rm+,rn_bank (rm) rn_bank, rm + 4 rm 0100mmmm1nnn0111 privileged ? lds rm,mach rm mach 0100mmmm00001010 ? ? lds rm,macl rm macl 0100mmmm00011010 ? ? lds rm,pr rm pr 0100mmmm00101010 ? ? lds.l @rm+,mach (rm) mach, rm + 4 rm 0100mmmm00000110 ? ? lds.l @rm+,macl (rm) macl, rm + 4 rm 0100mmmm00010110 ? ? lds.l @rm+,pr (rm) pr, rm + 4 rm 0100mmmm00100110 ? ? ldtlb pteh/ptel tlb 0000000000111000 privileged ? movca. l r0,@rn r0 (rn) (without fetching cache block) 0000nnnn11000011 ? ? nop no operation 0000000000001001 ? ? ocbi @rn invalidates operand cache block 0000nnnn10010011 ? ? ocbp @rn writes back and invalidates operand cache block 0000nnnn10100011 ? ? ocbwb @rn writes back operand cache block 0000nnnn10110011 ? ? pref @rn (rn) operand cache 0000nnnn10000011 ? ?
section 7 instruction set SH7750, SH7750s, SH7750r group page 224 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 instruction operation instruction code privileged t bit rte delayed branch, ssr/spc sr/pc 0000000000101011 privileged ? sets 1 s 0000000001011000 ? ? sett 1 t 0000000000011000 ? 1 sleep sleep or standby 0000000000011011 privileged ? stc sr,rn sr rn 0000nnnn00000010 privileged ? stc gbr,rn gbr rn 0000nnnn00010010 ? ? stc vbr,rn vbr rn 0000nnnn00100010 privileged ? stc ssr,rn ssr rn 0000nnnn00110010 privileged ? stc spc,rn spc rn 0000nnnn01000010 privileged ? stc sgr,rn sgr rn 0000nnnn00111010 privileged ? stc dbr,rn dbr rn 0000nnnn11111010 privileged ? stc rm_bank,rn rm_bank rn (m = 0 to 7) 0000nnnn1mmm0010 privileged ? stc.l sr,@-rn rn ? 4 rn, sr (rn) 0100nnnn00000011 privileged ? stc.l gbr,@-rn rn ? 4 rn, gbr (rn) 0100nnnn00010011 ? ? stc.l vbr,@-rn rn ? 4 rn, vbr (rn) 0100nnnn00100011 privileged ? stc.l ssr,@-rn rn ? 4 rn, ssr (rn) 0100nnnn00110011 privileged ? stc.l spc,@-rn rn ? 4 rn, spc (rn) 0100nnnn01000011 privileged ? stc.l sgr,@-rn rn ? 4 rn, sgr (rn) 0100nnnn00110010 privileged ? stc.l dbr,@-rn rn ? 4 rn, dbr (rn) 0100nnnn11110010 privileged ? stc.l rm_bank,@-rn rn ? 4 rn, rm_bank (rn) (m = 0 to 7) 0100nnnn1mmm0011 privileged ? sts mach,rn mach rn 0000nnnn00001010 ? ? sts macl,rn macl rn 0000nnnn00011010 ? ? sts pr,rn pr rn 0000nnnn00101010 ? ? sts.l mach,@-rn rn ? 4 rn, mach (rn) 0100nnnn00000010 ? ? sts.l macl,@-rn rn ? 4 rn, macl (rn) 0100nnnn00010010 ? ? sts.l pr,@-rn rn ? 4 rn, pr (rn) 0100nnnn00100010 ? ? trapa #imm pc + 2 spc, sr ssr, #imm << 2 tra, h'160 expevt, vbr + h'0100 pc 11000011iiiiiiii ? ?
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 225 of 1076 sep 24, 2013 table 7.9 floating-point si ngle-precision instructions instruction operation instruction code privileged t bit fldi0 frn h'00000000 frn 1111nnnn10001101 ? ? fldi1 frn h'3f800000 frn 1111nnnn10011101 ? ? fmov frm,frn frm frn 1111nnnnmmmm1100 ? ? fmov.s @rm,frn (rm) frn 1111nnnnmmmm1000 ? ? fmov.s @(r0,rm),frn (r0 + rm) frn 1111nnnnmmmm0110 ? ? fmov.s @rm+,frn (rm) frn, rm + 4 rm 1111nnnnmmmm1001 ? ? fmov.s frm,@rn frm (rn) 1111nnnnmmmm1010 ? ? fmov.s frm,@-rn rn-4 rn, frm (rn) 1111nnnnmmmm1011 ? ? fmov.s frm,@(r0,rn) frm (r0 + rn) 1111nnnnmmmm0111 ? ? fmov drm,drn drm drn 1111nnn0mmm01100 ? ? fmov @rm,drn (rm) drn 1111nnn0mmmm1000 ? ? fmov @(r0,rm),drn (r0 + rm) drn 1111nnn0mmmm0110 ? ? fmov @rm+,drn (rm) drn, rm + 8 rm 1111nnn0mmmm1001 ? ? fmov drm,@rn drm (rn) 1111nnnnmmm01010 ? ? fmov drm,@-rn rn-8 rn, drm (rn) 1111nnnnmmm01011 ? ? fmov drm,@(r0,rn) drm (r0 + rn) 1111nnnnmmm00111 ? ? flds frm,fpul frm fpul 1111mmmm00011101 ? ? fsts fpul,frn fpul frn 1111nnnn00001101 ? ? fabs frn frn & h'7fff ffff frn 1111nnnn01011101 ? ? fadd frm,frn frn + frm frn 1111nnnnmmmm0000 ? ? fcmp/eq frm,frn when frn = frm, 1 t otherwise, 0 t 1111nnnnmmmm0100 ? comparison result fcmp/gt frm,frn when frn > frm, 1 t otherwise, 0 t 1111nnnnmmmm0101 ? comparison result fdiv frm,frn frn/frm frn 1111nnnnmmmm0011 ? ? float fpul,frn (float) fpul frn 1111nnnn00101101 ? ? fmac fr0,frm,frn fr0 * frm + frn frn 1111nnnnmmmm1110 ? ? fmul frm,frn frn * frm frn 1111nnnnmmmm0010 ? ? fneg frn frn h'80000000 frn 1111nnnn01001101 ? ? fsqrt frn frn frn 1111nnnn01101101 ? ? fsub frm,frn frn ? frm frn 1111nnnnmmmm0001 ? ? ftrc frm,fpul (long) frm fpul 1111mmmm00111101 ? ?
section 7 instruction set SH7750, SH7750s, SH7750r group page 226 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 7.10 floating-point do uble-precision instructions instruction operation instruction code privileged t bit fabs drn drn & h'7fff ffff ffff ffff drn 1111nnn001011101 ? ? fadd drm,drn drn + drm drn 1111nnn0mmm00000 ? ? fcmp/eq drm,drn when drn = drm, 1 t otherwise, 0 t 1111nnn0mmm00100 ? comparison result fcmp/gt drm,drn when drn > drm, 1 t otherwise, 0 t 1111nnn0mmm00101 ? comparison result fdiv drm,drn drn /drm drn 1111nnn0mmm00011 ? ? fcnvds drm,fpul double_to_ float[drm] fpul 1111mmm010111101 ? ? fcnvsd fpul,drn float_to_ double [fpul] drn 1111nnn010101101 ? ? float fpul,drn (float)fpul drn 1111nnn000101101 ? ? fmul drm,drn drn * drm drn 1111nnn0mmm00010 ? ? fneg drn drn ^ h'8000 0000 0000 0000 drn 1111nnn001001101 ? ? fsqrt drn drn drn 1111nnn001101101 ? ? fsub drm,drn drn ? drm drn 1111nnn0mmm00001 ? ? ftrc drm,fpul (long) drm fpul 1111mmm000111101 ? ? table 7.11 floating-point control instructions instruction operation instruction code privileged t bit lds rm,fpscr rm fpscr 0100mmmm01101010 ? ? lds rm,fpul rm fpul 0100mmmm01011010 ? ? lds.l @rm+,fpscr (rm) fpscr, rm+4 rm 0100mmmm01100110 ? ? lds.l @rm+,fpul (rm) fpul, rm+4 rm 0100mmmm01010110 ? ? sts fpscr,rn fpscr rn 0000nnnn01101010 ? ? sts fpul,rn fpul rn 0000nnnn01011010 ? ? sts.l fpscr,@-rn rn ? 4 rn, fpscr (rn) 0100nnnn01100010 ? ? sts.l fpul,@-rn rn ? 4 rn, fpul (rn) 0100nnnn01010010 ? ?
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 227 of 1076 sep 24, 2013 table 7.12 floating-point grap hics acceleration instructions instruction operation instruction code privileged t bit fmov drm,xdn drm xdn 1111nnn1mmm01100 ? ? fmov xdm,drn xdm drn 1111nnn0mmm11100 ? ? fmov xdm,xdn xdm xdn 1111nnn1mmm11100 ? ? fmov @rm,xdn (rm) xdn 1111nnn1mmmm1000 ? ? fmov @rm+,xdn (rm) xdn, rm + 8 rm 1111nnn1mmmm1001 ? ? fmov @(r0,rm),xdn (r0 + rm) xdn 1111nnn1mmmm0110 ? ? fmov xdm,@rn xdm (rn) 1111nnnnmmm11010 ? ? fmov xdm,@-rn rn ? 8 rn, xdm (rn) 1111nnnnmmm11011 ? ? fmov xdm,@(r0,rn) xdm (r0+rn) 1111nnnnmmm10111 ? ? fipr fvm,fvn inner_product [fvm, fvn] fr[n+3] 1111nnmm11101101 ? ? ftrv xmtrx,fvn transform_vector [xmtrx, fvn] fvn 1111nn0111111101 ? ? frchg ~fpscr.fr fpscr.fr 1111101111111101 ? ? fschg ~fpscr.sz fpscr.sz 1111001111111101 ? ? 7.4 usage notes 7.4.1 notes on trapa instruction, sleep in struction, and unde fined instruction (h'fffd) ? incorrect data may be written to the cache when a trapa instru ction or undefi ned instruction code h'fffd is executed. ? the itlb hit judgment may be incorrect when a trapa instruction or undefined instruction code h'fffd is executed, causing a multi-hit exception to occur after re-registration. ? incorrect data may be written to an fpu-related register or to the mach or macl register when a trapa instruction, sleep instruction, or undefined instruction code h'fffd is executed. conditions under which problem occurs 1. incorrect data may be writt en to the instructio n cache when the following three conditions occur at the same time. a. the instruction cache is enabled (ccr.ice = 1). b. a trapa instruction or undefined instruction code h'fffd in a cache-enabled area is executed.
section 7 instruction set SH7750, SH7750s, SH7750r group page 228 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 c. the four words of data following the trapa instruction or undefined instruction code h'fffd mentioned in b. contai n code that can be interprete d as an instruction to access (read or write) an address (h'f0000000 to h'f7ffffff) mapped to the internal cache or internal tlb. 2. incorrect data may be writte n to the operand cache when the following three conditions occur at the same time. a. the operand cache is enabled (ccr.oce = 1). b. undefined instruction code h'fffd is executed. c. the four words of data following the undefined instruction code h'fffd mentioned in b. contain code that can be interpreted as an ocbi, ocbp, ocbwb, or tas.b instruction accessing an address (h'e0000000 to h'e3ffff ff) mapped to the internal store queue. 3. the itlb hit judgment may be incorrect when the following three conditions occur at the same time. if an itlb hit is erroneously j udged to be a miss, itlb re-registration is performed. this can cause an i tlb multi-hit exception to occur. a. the mmu enabled (mmucr.at = 1). b. a trapa instruction or undefined instruction code h'fffd in a tlb conversion area (area u0, p0, or p3) is executed. c. the four words of data following the trapa instruction or undefined instruction code h'fffd mentioned in b. contai n code that can be interprete d as an instruction to access (read or write) an address (h'f0000000 to h'f7ffffff) mapped to the internal cache or internal tlb. 4. incorrect data may be written to an fpu-rela ted register (fr0 to fr15, xf0 to xf15, fpscr, or fpul) or to the mach or macl register wh en the following two conditions occur at the same time. a. a trapa instruction, sleep instruction, or undefined instruction code h'fffd is executed b. the eight words of data following the trapa instruction, sleep instruction, or undefined instruction code h'fffd mentioned in a. contain h'fxxx (an instruction with h'f as the first four bits), excluding h'fffd, and the c ode can be interpreted, in combination with fpscr.pr at that point, as an undefined instruction. example: instruction h'fxxe (x: any hexadecimal digit) is defined here as undefined when fpscr.pr is set to 1. note: the number of instructions following the instructions mentioned above that may be affected by the problem is as follows: in the case of 1. to 3., the number of instructions that can be executed in 2xick, and in the case of 4., the number of instructions that can be executed in 4xick. the maximum nu mber of instructions that can be executed in 2xick or
SH7750, SH7750s, SH7750r group section 7 instruction set r01uh0456ej0702 rev. 7.02 page 229 of 1076 sep 24, 2013 4xick is four or eight, respectively. therefore, the affected codes are those occurring in ?the four words (or eight words) of data following the instruction.? workarounds: to prevent the problem, use either of workarounds a. or b. below. a. include a nop instruction in the eight words of data fo llowing each trap a instruction, sleep instruction, or undefi ned instruction code h'fffd. b. include an or r0,r0 instruc tion in the five words of data following each trapa instruction, sleep instruction, or undefine d instruction code h'fffd. this workaround also applies to cases where ?the eight words of data follow ing the ? instruction ? contain h'fxxx,? as mentioned in condition 4. b., because two or instructions are never executed simultaneously, so a minimum of 5xick is required for execution.
section 7 instruction set SH7750, SH7750s, SH7750r group page 230 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 231 of 1076 sep 24, 2013 section 8 pipelining this lsi is a 2-ilp (instruction-level-paralle lism) superscalar pipelining microprocessor. instruction execution is pipelined, and two instruc tions can be executed in parallel. the execution cycles depend on the implementation of a processor. definitions in this section may not be applicable to sh-4 series products other than this lsi. 8.1 pipelines figure 8.1 shows the basic pipelines. normally, a pipeline consists of five or six stages: instruction fetch (i), decode and re gister read (d), exec ution (ex/sx/f0/f1/f2/f3 ), data access (na/ma), and write-back (s/fs). an instruction is executed as a combination of basic pipelines. figure 8.2 shows the instruction execution patterns.
section 8 pipelining SH7750, SH7750s, SH7750r group page 232 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1. general pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? destination address calculation for pc-relative branch ? non-memory data access ? write-back i d ex ? operation na s 2. general load/store pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? memory data access ? write-back i d ex ? address calculation ma s 3. special pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? non-memory data access ? write-back i d sx ? operation na s 4. special load/store pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? memory data access ? write-back i d sx ? address calculation ma s 5. floatin g -point pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? computation 2 ? computation 3 ? write-back i d f1 ? computation 1 f2 fs 6. floatin g -point extended pipeline ? instruction fetch ? instruction decode ? issue ? re g ister read ? computation 1 ? computation 3 ? write-back i d f0 ? computation 0 f1 f2 fs ? computation 2 f3 computation: takes several cycles 7. fdiv/fsqrt pipeline figure 8.1 basic pipelines
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 233 of 1076 sep 24, 2013 1. 1-step operation: 1 issue cycle ext[su].[bw], mov, mov#, mova, movt, swap.[bw], xtrct, add * , cmp * , div * , dt, neg * , sub * , and, and#, not, or, or#, tst, tst#, xor, xor#, rot * , sha * , shl * , bf * , bt * , bra, nop, clrs, clrt, sets, sett, lds to fpul, sts from fpul/fpscr, fldi0, fldi1, fmov, flds, fsts, sin g le-/double-precision fabs/fneg i d ex na s 2. load/store: 1 issue cycle mov.[bwl]. fmov * @, lds.l to fpul, ldtlb, pref, sts.l from fpul/fpscr i d ex ma s 3. gbr-based load/store: 1 issue cycle mov.[bwl]@(d,gbr) i d sx ma s 4. jmp, rts, braf: 2 issue cycles i d ex na s d ex na s 5. tst.b: 3 issue cycles i d sx ma s d sx na s d sx na s 6. and.b, or.b, xor.b: 4 issue cycles i d sx ma s d sx na s d sx na s d sx ma s 7. tas.b: 5 issue cycles i d ex ma s d ex ma s d ex na s d ex na s d ex ma s 8. rte: 5 issue cycles i d ex na s d ex na s d ex na s d ex na s d ex na s 9. sleep: 4 issue cycles i d ex na s d ex na s d ex na s d ex na s figure 8.2 instruction execution patterns
section 8 pipelining SH7750, SH7750s, SH7750r group page 234 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 10. ocbi: 1 issue cycle i d ex ma s ma 11. ocbp, ocbwb: 1 issue cycle i d ex ma s ma ma ma ma 12. movca.l: 1 issue cycle i d ex ma s ma ma ma ma ma ma 13. trapa: 7 issue cycles i d ex na s d ex na s d ex na s d ex na s d ex na s d ex na s d ex na s 14. ldc to dbr/rp_bank/ssr/spc/vbr, bsr: 1 issue cycle i d ex na s sx sx 15. ldc to gbr: 3 issue cycles i d ex na s d d sx sx 16. ldc to sr: 4 issue cycles i d ex na s d d d sx sx sx i d ex ma s 17. ldc.l to dbr/rp_bank/ssr/spc/vbr: 1 issue cycle sx sx 18. ldc.l to gbr: 3 issue cycles i d ex ma s d d sx sx figure 8.2 instruction execution patterns (cont)
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 235 of 1076 sep 24, 2013 19. ldc.l to sr: 4 issue cycles i d ex ma s d d d sx sx sx 20. stc from dbr/gbr/rp_bank/sr/ssr/spc/vbr: 2 issue cycles i d sx na s d sx na s 21. stc.l from sgr: 3 issue cycles i d sx na s d sx na s d sx na s 22. stc.l from dbr/gbr/rp_bank/sr/ssr/spc/vbr: 2 issue cycles i d sx na s d sx ma s 23. stc.l from sgr: 3 issue cycles i d sx na s d sx na s d sx ma s 24. lds to pr, jsr, bsrf: 2 issue cycles i d ex na s d sx sx 25. lds.l to pr: 2 issue cycles i d ex ma s d sx sx 26. sts from pr: 2 issue cycles i d sx na s d sx na s 27. sts.l from pr: 2 issue cycles i d sx na s d sx ma s 28. clrmac, lds to mach/l: 1 issue cycle i d ex na s f1 f1 f2 fs 29. lds.l to mach/l: 1 issue cycle i d ex ma s f1 f1 f2 fs 30. sts from mach/l: 1 issue cycle i d ex na s figure 8.2 instruction execution patterns (cont)
section 8 pipelining SH7750, SH7750s, SH7750r group page 236 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 31. sts.l from mach/l: 1 issue cycle i d ex ma s 32. lds to fpscr: 1 issue cycle i d ex na s f1 f1 f1 f1 f1 f1 33. lds.l to fpscr: 1 issue cycle i d ex ma s 34. fixed-point multiplication: 2 issue cycles dmuls.l, dmulu.l, mul.l, muls.w, mulu.w i d ex na s (cpu) d ex na s f1 (fpu) f1 f1 f1 f2 fs 35. mac.w, mac.l: 2 issue cycles i d ex ma s (cpu) d ex ma s f1 (fpu) f1 f1 f1 f2 fs 36. sin g le-precision floatin g -point computation: 1 issue cycle fcmp/eq,fcmp/gt, fadd,float,fmac,fmul,fsub,ftrc,frchg,fschg i d f1 f2 fs 37. sin g le-precision fdiv/sqrt: 1 issue cycle i d f1 f2 fs f3 f1 f2 fs 38. double-precision floatin g -point computation 1: 1 issue cycle fcnvds, fcnvsd, float, ftrc i d f1 f2 fs d f1 f2 fs 39. double-precision floatin g -point computation 2: 1 issue cycle fadd, fmul, fsub i d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 f2 fs figure 8.2 instruction execution patterns (cont)
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 237 of 1076 sep 24, 2013 i d f1 f2 fs d f1 f2 fs 40. double-precision fcmp: 2 issue cycles fcmp/eq,fcmp/gt i d f1 f2 fs f3 f1 f2 fs 41. double-precision fdiv/sqrt: 1 issue cycle fdiv, fsqrt f1 f2 d f1 f2 fs f1 f2 fs 42. fipr: 1 issue cycle i d f0 f1 f2 fs 43. ftrv: 1 issue cycle f1 f2 fs d f0 i f1 f2 fs d f0 f1 f2 fs d f0 f1 f2 fs d f0 notes: ?? : locks d-sta g e : re g ister read only : locks, but no operation is executed. : can overlap another f1, but not another f1. d d ?? f1 : cannot overlap a sta g e of the same kind, except when two instructions are executed in parallel. figure 8.2 instruction execution patterns (cont)
section 8 pipelining SH7750, SH7750s, SH7750r group page 238 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 8.2 parallel-executability instructions are categorized into six groups according to the inte rnal function bl ocks used, as shown in table 8.1. table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. for example, add in the ex group and bra in the br group can be executed in parallel. table 8.1 instruction groups 1. mt group clrt cmp/hi rm,rn mov rm,rn cmp/eq #imm,r0 cmp/hs rm,rn nop cmp/eq rm,rn cmp/pl rn sett cmp/ge rm,rn cmp/pz rn tst #imm,r0 cmp/gt rm,rn cmp/str rm,rn tst rm,rn 2. ex group add #imm,rn movt rn shll2 rn add rm,rn neg rm,rn shll8 rn addc rm,rn negc rm,rn shlr rn addv rm,rn not rm,rn shlr16 rn and #imm,r0 or #imm,r0 shlr2 rn and rm,rn or rm,rn shlr8 rn div0s rm,rn rotcl rn sub rm,rn div0u rotcr rn subc rm,rn div1 rm,rn rotl rn subv rm,rn dt rn rotr rn swap.b rm,rn exts.b rm,rn shad rm,rn swap.w rm,rn exts.w rm,rn shal rn xor #imm,r0 extu.b rm,rn shar rn xor rm,rn extu.w rm,rn shld rm,rn xtrct rm,rn mov #imm,rn shll rn mova @(disp,pc),r0 shll16 rn
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 239 of 1076 sep 24, 2013 3. br group bf disp bra disp bt disp bf/s disp bsr disp bt/s disp 4. ls group fabs drn fmov.s @rm+,frn mov.l r0,@(disp,gbr) fabs frn fmov.s frm,@(r0,rn) mov.l rm,@(disp,rn) fldi0 frn fmov.s frm,@-rn mov.l rm,@(r0,rn) fldi1 frn fmov.s frm,@rn mov.l rm,@-rn flds frm,fpul fneg drn mov.l rm,@rn fmov @(r0,rm),drn fneg frn mov.w @(disp,gbr),r0 fmov @(r0,rm),xdn fsts fpul,frn mov.w @(disp,pc),rn fmov @rm,drn lds rm,fpul mov.w @(disp,rm),r0 fmov @rm,xdn mov.b @(disp,gbr),r0 mov.w @(r0,rm),rn fmov @rm+,drn mov.b @(disp,rm),r0 mov.w @rm,rn fmov @rm+,xdn mov.b @(r0,rm),rn mov.w @rm+,rn fmov drm,@(r0,rn) mov.b @rm,rn mov.w r0,@(disp,gbr) fmov drm,@-rn mov.b @rm+,rn mov.w r0,@(disp,rn) fmov drm,@rn mov.b r0,@(disp,gbr) mov.w rm,@(r0,rn) fmov drm,drn mov.b r0,@(disp,rn) mov.w rm,@-rn fmov drm,xdn mov.b rm,@(r0,rn) mov.w rm,@rn fmov frm,frn mov.b rm,@-rn movca.l r0,@rn fmov xdm,@(r0,rn) mov.b rm,@rn ocbi @rn fmov xdm,@-rn mov.l @(disp,gbr),r0 ocbp @rn fmov xdm,@rn mov.l @(disp,pc),rn ocbwb @rn fmov xdm,drn mov.l @(disp,rm),rn pref @rn fmov xdm,xdn mov.l @(r0,rm),rn sts fpul,rn fmov.s @(r0,rm),frn mov.l @rm,rn fmov.s @rm,frn mov.l @rm+,rn
section 8 pipelining SH7750, SH7750s, SH7750r group page 240 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 5. fe group fadd drm,drn fipr fvm,fvn fsqrt drn fadd frm,frn float fpul,drn fsqrt frn fcmp/eq frm,frn float fpul,frn fsub drm,drn fcmp/gt frm,frn fmac fr0,frm,frn fsub frm,frn fcnvds drm,fpul fmul drm,drn ftrc drm,fpul fcnvsd fpul,drn fmul frm,frn ftrc frm,fpul fdiv drm,drn frchg ftrv xmtrx,fvn fdiv frm,frn fschg
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 241 of 1076 sep 24, 2013 6. co group and.b #imm,@(r0,gbr) lds rm,fpscr stc sr,rn braf rm lds rm,mach stc ssr,rn bsrf rm lds rm,macl stc vbr,rn clrmac lds rm,pr stc.l dbr,@-rn clrs lds.l @rm+,fpscr stc.l gbr,@-rn dmuls.l rm,rn lds.l @rm+,f pul stc.l rp_bank,@-rn dmulu.l rm,rn lds.l @rm+ ,mach stc.l sgr,@-rn fcmp/eq drm,drn lds.l @rm+,macl stc.l spc,@-rn fcmp/gt drm,drn lds.l @rm+,pr stc.l sr,@-rn jmp @rn ldtlb stc.l ssr,@-rn jsr @rn mac.l @rm+,@rn+ stc.l vbr,@-rn ldc rm,dbr mac.w @rm+,@rn+ sts fpscr,rn ldc rm,gbr mul.l rm,rn sts mach,rn ldc rm,rp_bank muls.w rm,rn sts macl,rn ldc rm,spc mulu.w rm,rn sts pr,rn ldc rm,sr or.b #imm,@(r0,gbr) sts.l fpscr,@-rn ldc rm,ssr rte sts.l fpul,@-rn ldc rm,vbr rts sts.l mach,@-rn ldc.l @rm+,dbr sets sts.l macl,@-rn ldc.l @rm+,gbr sleep sts.l pr,@-rn ldc.l @rm+,rp_bank stc dbr,rn tas.b @rn ldc.l @rm+,spc stc gbr,rn trapa #imm ldc.l @rm+,sr stc rp_bank,rn tst.b #imm,@(r0,gbr) ldc.l @rm+,ssr stc sgr, rn xor.b #imm,@(r0,gbr) ldc.l @rm+,vbr stc spc,rn
section 8 pipelining SH7750, SH7750s, SH7750r group page 242 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 8.2 parallel-executability 2nd instruction mt ex br ls fe co mt o o o o o x ex o x o o o x br o o x o o x ls o o o x o x fe o o o o x x 1st instruction co x x x x x x legend: o: can be executed in parallel x: cannot be executed in parallel 8.3 execution cycles and pipeline stalling there are three basic clocks in th is processor: the i-clock, b-clock, and p-clock. each hardware unit operates on one of these clocks, as follows: ? i-clock: cpu, fpu, mmu, caches ? b-clock: external bus controller ? p-clock: peripheral units the frequency ratios of the three clocks are de termined with the frequency control register (frqcr). in this section, machine cycles are ba sed on the i-clock unless otherwise specified. for details of frqcr, see section 10, clock oscillation circuits. instruction execution cycles are su mmarized in table 8.3. penalty cycles due to a pipeline stall or freeze are not considered in this table. ? issue rate: interval between the issue of an instruction and that of the next instruction ? latency: interval between the issue of an instruction and the generation of its result (completion) ? instruction execution pattern (see figure 8.2) ? locked pipeline stages (see table 8.3) ? interval between the issue of an instructio n and the start of lock ing (see table 8.3) ? lock time: period of locking in machine cycle units (see table 8.3)
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 243 of 1076 sep 24, 2013 the instruction exec ution sequence is expressed as a comb ination of the execution patterns shown in figure 8.2. one instruction is separated from the next by the number of machine cycles for its issue rate. normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction; the only ex ception is when two instru ctions are executed in parallel under parallel-executability conditions. refer to (a) through (d) in figure 8.3 for some simple examples. latency is the interval between issue and completion of an instruction, and is also the interval between the execution of two instructions with an interdependent relationship. when there is interdependency between two instructions fetched simultaneously, the latter of the two is stalled for the following number of cycles: ? (latency) cycles when there is fl ow dependency (read-after-write) ? (latency - 1) or (latency - 2) cycles when there is output dependency (write-after-write) ? single/double-precision fdn, fs qrt is the preceding instruct ion (latency ? 1) cycles ? the other fe group is the preceding instruction (latency ? 2) cycles ? 5 or 2 cycles when there is anti-flow dependency (write-after-read), as in the following cases: ? ftrv is the preceding in struction (5 cycle) ? a double-precision fa dd, fsub, or fmul is the pr eceding instruction (2 cycles) in the case of flow dependency, latency may be exceptionally increased or decreased, depending on the combination of sequential instructions (figure 8.3 (e)). ? when a floating-point (fp) computation is followed by an fp register store, the latency of the fp computation may be decreased by 1 cycle. ? if there is a load of the shift amount immedi ately before an shad/shld instruction, the latency of the load is increased by 1 cycle. ? if an instruction with a latency of less than 2 cycl es, including write-back to an fp register, is followed by a double-precision fp instruction, fipr, or ftrv, the latency of the first instruction is increased to 2 cycles. the number of cycles in a pipeline stall due to flow dependency will vary depending on the combination of interdependent instructions or the fetch timing (see figure 8.3. (e)). output dependency occurs when the destination operands are the same in a preceding fe group instruction and a following ls group instruction. for the stall cycles of an instru ction with output dependency, the longest latency to the last write- back among all the destination oper ands must be applied instead of ?latency? (see fi gure 8.3 (f)). a stall due to output dependency with respect to fpscr, which reflects the result of an fp
section 8 pipelining SH7750, SH7750s, SH7750r group page 244 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 operation, never occurs. for example, when fadd follows fdiv with no dependency between fp registers, fadd is not stalled even if both instructions update the cause field of fpscr. anti-flow dependency can occur only betwee n a preceding double-pr ecision fadd, fmul, fsub, or ftrv and a following fmov, fldi0, fldi1, fabs, fneg, or fsts. see figure 8.3 (g). if an executing instruction locks any resource?i.e. a function block that performs a basic operation?a following instruction that happens to attempt to use the locked resource must be stalled (figure 8.3 (h)). this kind of stall can be compensated by inserting one or more instructions independent of the locked resource to separate th e interfering instructions . for example, when a load instruction and an add instruction that refe rences the loaded value are consecutive, the 2- cycle stall of the add is eliminat ed by inserting three instructions without dependency. software performance can be improved by such instruction scheduling. other penalties arise in the event of exceptio ns or external data accesses, as follows. ? instruction tlb miss ? instruction access to external me mory (instruction cache miss, etc.) ? data access to external memory (operand cach e miss, etc.) ? data access to a memory-mapped control register. during the penalty cycles of an instruction tlb miss or external instruc tion access, no instruction is issued, but execution of instructions that have already been issued continues. the penalty for a data access is a pipeline freeze: that is, the execu tion of uncompleted instru ctions is interrupted until the arrival of the requested data. the number of penalty cycles for instruction and data accesses is largely dependent on the user's memory subsystems.
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 245 of 1076 sep 24, 2013 (a) serial execution: non-parallel-executable instructions add r2,r1 mov.l @r4,r5 mov r1,r2 next shad r0,r1 add r2,r3 next i d ex na s i d ex na s id ... 1 stall cycle (b) parallel execution: parallel-executable and no dependency i d ex na s i d ex ma s (c) issue rate: multi-step instruction and.b#1,@(r0,gbr) i d sx ma s d sx ma s d sx na s d sx na s i i (d) branch 1 issue cycle 1 issue cycle 4 issue cycles ... i d ex na s i d ex na s 2-cycle latency for i-sta g e of branch destination 1 stall cycle i d i d ex na s i d ex na s i d ex na s bt/s l_far add r0,r1 sub r2,r3 bt/s l_far add r0,r1 l_far i d ex na s i d i d ? ?? ... no stall bt l_skip add #1,r0 l_skip: ... i d e a s 4 stall cycles ex- g roup shad and ex- g roup add cannot be executed in parallel. therefore, shad is issued first, and the followin g add is recombined with the next instruction. ex- g roup add and ls- g roup mov.l can be executed in parallel. overlappin g of sta g es in the 2nd instruction is possible. and.b and mov are fetched simultaneously, but mov is stalled due to resource lockin g . after the lock is released, mov is refetched to g ether with the next instruction. no stall occurs if the branch is not taken. if the branch is taken, the i-sta g e of the branch destination is stalled for the period of latency. this stall can be covered with a delay slot instruction which is not parallel- executable with the branch instruction. even if the bt/bf branch is taken, the i- sta g e of the branch destination is not stalled if the displacement is zero. figure 8.3 examples of pipelined execution
section 8 pipelining SH7750, SH7750s, SH7750r group page 246 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (e) flow dependency i d ex na s i d ex na s mov r0,r1 add r2,r1 add r2,r1 mov.l @r1,r1 next i d ex na s i d ex ma s i i ... ... ... zero-cycle latency 1-cycle latency 1 stall cycle mov.l @r1,r1 add r0,r1 next i d ex ma s i d i ex na s d ex na s 2-cycle latency 1 stall cycle mov.l @r1,r1 shad r1,r2 next fadd fr1,fr2 sts fpul,r1 sts fpscr,r2 i d ex na s i 4-cycle latency for fpscr 2 stall cycles i d f1 f2 fs i d ex ma s i d i 2-cycle latency 2 stall cycles ex na s d 1-cycle increase i i i d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 f2 fs d f1 f2 fs ex na s d ex na s d fadd dr0,dr2 7-cycle latency for lower fr 8-cycle latency for upper fr fmov fr3,fr5 fmov fr2,fr4 float fpul,dr0 fmov.s fr0,@-r15 fr3 write fr2 write i d f1 f2 fs d f1 f2 fs i d ex ma s 3-cycle latency for upper/lower fr fr1 write fr0 write fldi1 fr3 fipr fv0,fv4 fmov @r1,xd14 ftrv xmtrx,fv0 i d ex na s i d d f0 f1 f2 fs zero-cycle latency 3-cycle increase 3 stall cycles i d ex ma s i d d f0 f1 f2 fs d f0 f1 fs f2 d f0 f2 f1 fs d f1 f0 f2 fs 2-cycle latency 1-cycle increase 3 stall cycles the followin g instruction, add, is not stalled when executed after an instruction with zero-cycle latency, even if there is dependency. add and mov.l are not executed in parallel, since mov.l references the result of add as its destination address. because mov.l and add are not fetched simultaneously in this example, add is stalled for only 1 cycle even thou g h the latency of mov.l is 2 cycles. due to the flow dependency between the load and the shad/shld shift amount, the latency of the load is increased to 3 cycles. figure 8.3 examples of pipelined execution (cont)
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 247 of 1076 sep 24, 2013 i d ex na s i d ex na s d f1 f2 fs d f1 f2 fs (e) flow dependency (cont) i i lds r0,fpul float fpul,fr0 lds r1,fpul float fpul,r1 effectively 1-cycle latency for consecutive lds/float instructions i d ex na s d f1 f2 fs i d f1 f2 fs i i d ex na s effectively 1-cycle latency for consecutive ftrc/sts instructions ftrc fr0,fpul sts fpul,r0 ftrc fr1,fpul sts fpul,r1 (f) output dependency d f1 f2 fs i i d f1 f2 fs f1 f2 fs 11-cycle latency 10 stall cycles = latency (11) - 1 the re g isters are written-back in pro g ram order. d f1 f2 fs i d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 f2 fs ex na s i d 7-cycle latency for lower fr 8-cycle latency for upper fr 6 stall cycles = lon g est latency (8) - 2 fr2 write fr3 write d f1 f2 fs i d f1 f2 fs d f1 f2 fs d f1 f0 f0 f0 f0 f2 fs ( g ) anti-flow dependency ex ma s i d 5 stall cycles d f1 f2 fs i d f1 f2 fs d f1 f2 fs d f1 f2 fs ex na s i d 2 stall cycles d f1 f2 fs f1 f2 fs fsqrt fr4 fmov fr0,fr4 fadd dr0,dr2 fmov fr0,fr3 ftrv xmtrx,fv0 fmov @r1,xd0 fadd dr0,dr2 fmov fr4,fr1 f3 figure 8.3 examples of pipelined execution (cont)
section 8 pipelining SH7750, SH7750s, SH7750r group page 248 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (h) resource conflict f1 sta g e locked for 1 cycle latency 1 cycle/issue 1 stall cycle (f1 sta g e resource conflict) fdiv fr6,fr7 fmac fr0,fr8,fr9 fmac fr0,fr10,fr11 fmac fr0,fr12,fr13 fipr fv8,fv0 fadd fr15,fr4 i d f1 f0 f2 fs i d f1 f2 fs 1 stall cycle lds.l @r15+,pr i d ex ma fs dsx sx sx na s sx na s d i 3 stall cycles stc gbr,r2 fadd dr0,dr2 i d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 f2 fs ex ma s f1 ex ma s d f1 f1 f2 fs f1 f2 fs i d 5 stall cycles mac.w @r1+,@r2+ i d ex ma s f1 f1 f1 f2 fs f1 f2 fs i f1 d ex ma s f1 d ex ma s f1 f2 fs f1 f2 fs f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs d f1 f2 fs f1 ... i d 3 stall cycles 1 stall cycle 2 stall cycles mac.w @r1+,@r2+ mac.w @r1+,@r2+ fadd dr4,dr6 f1 sta g e can overlap precedin g f1, but f1 cannot overlap f1. d ex ma s d i d f1 f2 fs i d f1 f2 fs f1 f2 fs f1 f2 i dfs f3 i d f1 f2 fs #1 #2 #3 .................................................. #10 #11 #8 #9 #12 ... : figure 8.3 examples of pipelined execution (cont)
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 249 of 1076 sep 24, 2013 table 8.3 execution cycles lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 1 exts.b rm,rn ex 1 1 #1 ? ? ? 2 exts.w rm,rn ex 1 1 #1 ? ? ? 3 extu.b rm,rn ex 1 1 #1 ? ? ? 4 extu.w rm,rn ex 1 1 #1 ? ? ? 5 mov rm,rn mt 1 0 #1 ? ? ? 6 mov #imm,rn ex 1 1 #1 ? ? ? 7 mova @(disp,pc),r0 ex 1 1 #1 ? ? ? 8 mov.w @(disp,pc),rn ls 1 2 #2 ? ? ? 9 mov.l @(disp,pc),rn ls 1 2 #2 ? ? ? 10 mov.b @rm,rn ls 1 2 #2 ? ? ? 11 mov.w @rm,rn ls 1 2 #2 ? ? ? 12 mov.l @rm,rn ls 1 2 #2 ? ? ? 13 mov.b @rm+,rn ls 1 1/2 #2 ? ? ? 14 mov.w @rm+,rn ls 1 1/2 #2 ? ? ? 15 mov.l @rm+,rn ls 1 1/2 #2 ? ? ? 16 mov.b @(disp,rm),r0 ls 1 2 #2 ? ? ? 17 mov.w @(disp,rm),r0 ls 1 2 #2 ? ? ? 18 mov.l @(disp,rm),rn ls 1 2 #2 ? ? ? 19 mov.b @(r0,rm),rn ls 1 2 #2 ? ? ? 20 mov.w @(r0,rm),rn ls 1 2 #2 ? ? ? 21 mov.l @(r0,rm),rn ls 1 2 #2 ? ? ? 22 mov.b @(disp,gbr),r0 ls 1 2 #3 ? ? ? 23 mov.w @(disp,gbr),r0 ls 1 2 #3 ? ? ? 24 mov.l @(disp,gbr),r0 ls 1 2 #3 ? ? ? 25 mov.b rm,@rn ls 1 1 #2 ? ? ? 26 mov.w rm,@rn ls 1 1 #2 ? ? ? 27 mov.l rm,@rn ls 1 1 #2 ? ? ? 28 mov.b rm,@-rn ls 1 1/1 #2 ? ? ? 29 mov.w rm,@-rn ls 1 1/1 #2 ? ? ? 30 mov.l rm,@-rn ls 1 1/1 #2 ? ? ? data transfer instructions 31 mov.b r0,@(disp,rn) ls 1 1 #2 ? ? ?
section 8 pipelining SH7750, SH7750s, SH7750r group page 250 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 32 mov.w r0,@(disp,rn) ls 1 1 #2 ? ? ? 33 mov.l rm,@(disp,rn) ls 1 1 #2 ? ? ? 34 mov.b rm,@(r0,rn) ls 1 1 #2 ? ? ? 35 mov.w rm,@(r0,rn) ls 1 1 #2 ? ? ? 36 mov.l rm,@(r0,rn) ls 1 1 #2 ? ? ? 37 mov.b r0,@(disp,gbr) ls 1 1 #3 ? ? ? 38 mov.w r0,@(disp,gbr) ls 1 1 #3 ? ? ? 39 mov.l r0,@(disp,gbr) ls 1 1 #3 ? ? ? 40 movca.l r0,@rn ls 1 3?7 #12 ma 4 3?7 41 movt rn ex 1 1 #1 ? ? ? 42 ocbi @rn ls 1 1?2 #10 ma 4 1?2 43 ocbp @rn ls 1 1?5 #11 ma 4 1?5 44 ocbwb @rn ls 1 1?5 #11 ma 4 1?5 45 pref @rn ls 1 1 #2 ? ? ? 46 swap.b rm,rn ex 1 1 #1 ? ? ? 47 swap.w rm,rn ex 1 1 #1 ? ? ? data transfer instructions 48 xtrct rm,rn ex 1 1 #1 ? ? ? 49 add rm,rn ex 1 1 #1 ? ? ? 50 add #imm,rn ex 1 1 #1 ? ? ? 51 addc rm,rn ex 1 1 #1 ? ? ? 52 addv rm,rn ex 1 1 #1 ? ? ? 53 cmp/eq #imm,r0 mt 1 1 #1 ? ? ? 54 cmp/eq rm,rn mt 1 1 #1 ? ? ? 55 cmp/ge rm,rn mt 1 1 #1 ? ? ? 56 cmp/gt rm,rn mt 1 1 #1 ? ? ? 57 cmp/hi rm,rn mt 1 1 #1 ? ? ? 58 cmp/hs rm,rn mt 1 1 #1 ? ? ? 59 cmp/pl rn mt 1 1 #1 ? ? ? 60 cmp/pz rn mt 1 1 #1 ? ? ? 61 cmp/str rm,rn mt 1 1 #1 ? ? ? fixed-point arithmetic instructions 62 div0s rm,rn ex 1 1 #1 ? ? ?
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 251 of 1076 sep 24, 2013 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 63 div0u ex 1 1 #1 ? ? ? 64 div1 rm,rn ex 1 1 #1 ? ? ? 65 dmuls.l rm,rn co 2 4/4 #34 f1 4 2 66 dmulu.l rm,rn co 2 4/4 #34 f1 4 2 67 dt rn ex 1 1 #1 ? ? ? 68 mac.l @rm+,@rn+ co 2 2/2/4/4 #35 f1 4 2 69 mac.w @rm+,@rn+ co 2 2/2/4/4 #35 f1 4 2 70 mul.l rm,rn co 2 4/4 #34 f1 4 2 71 muls.w rm,rn co 2 4/4 #34 f1 4 2 72 mulu.w rm,rn co 2 4/4 #34 f1 4 2 73 neg rm,rn ex 1 1 #1 ? ? ? 74 negc rm,rn ex 1 1 #1 ? ? ? 75 sub rm,rn ex 1 1 #1 ? ? ? 76 subc rm,rn ex 1 1 #1 ? ? ? fixed-point arithmetic instructions 77 subv rm,rn ex 1 1 #1 ? ? ? 78 and rm,rn ex 1 1 #1 ? ? ? 79 and #imm,r0 ex 1 1 #1 ? ? ? 80 and.b #imm,@(r0,gbr) co 4 4 #6 ? ? ? 81 not rm,rn ex 1 1 #1 ? ? ? 82 or rm,rn ex 1 1 #1 ? ? ? 83 or #imm,r0 ex 1 1 #1 ? ? ? 84 or.b #imm,@(r0,gbr) co 4 4 #6 ? ? ? 85 tas.b @rn co 5 5 #7 ? ? ? 86 tst rm,rn mt 1 1 #1 ? ? ? 87 tst #imm,r0 mt 1 1 #1 ? ? ? 88 tst.b #imm,@(r0,gbr) co 3 3 #5 ? ? ? 89 xor rm,rn ex 1 1 #1 ? ? ? 90 xor #imm,r0 ex 1 1 #1 ? ? ? logical instructions 91 xor.b #imm,@(r0,gbr) co 4 4 #6 ? ? ?
section 8 pipelining SH7750, SH7750s, SH7750r group page 252 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 92 rotl rn ex 1 1 #1 ? ? ? 93 rotr rn ex 1 1 #1 ? ? ? 94 rotcl rn ex 1 1 #1 ? ? ? 95 rotcr rn ex 1 1 #1 ? ? ? 96 shad rm,rn ex 1 1 #1 ? ? ? 97 shal rn ex 1 1 #1 ? ? ? 98 shar rn ex 1 1 #1 ? ? ? 99 shld rm,rn ex 1 1 #1 ? ? ? 100 shll rn ex 1 1 #1 ? ? ? 101 shll2 rn ex 1 1 #1 ? ? ? 102 shll8 rn ex 1 1 #1 ? ? ? 103 shll16 rn ex 1 1 #1 ? ? ? 104 shlr rn ex 1 1 #1 ? ? ? 105 shlr2 rn ex 1 1 #1 ? ? ? 106 shlr8 rn ex 1 1 #1 ? ? ? shift instructions 107 shlr16 rn ex 1 1 #1 ? ? ? 108 bf disp br 1 2 (or 1) #1 ? ? ? 109 bf/s disp br 1 2 (or 1) #1 ? ? ? 110 bt disp br 1 2 (or 1) #1 ? ? ? 111 bt/s disp br 1 2 (or 1) #1 ? ? ? 112 bra disp br 1 2 #1 ? ? ? 113 braf rn co 2 3 #4 ? ? ? 114 bsr disp br 1 2 #14 sx 3 2 115 bsrf rn co 2 3 #24 sx 3 2 116 jmp @rn co 2 3 #4 ? ? ? 117 jsr @rn co 2 3 #24 sx 3 2 branch instructions 118 rts co 2 3 #4 ? ? ?
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 253 of 1076 sep 24, 2013 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 119 nop mt 1 0 #1 ? ? ? 120 clrmac co 1 3 #28 f1 3 2 121 clrs co 1 1 #1 ? ? ? 122 clrt mt 1 1 #1 ? ? ? 123 sets co 1 1 #1 ? ? ? 124 sett mt 1 1 #1 ? ? ? 125 trapa #imm co 7 7 #13 ? ? ? 126 rte co 5 5 #8 ? ? ? 127 sleep co 4 4 #9 ? ? ? 128 ldtlb co 1 1 #2 ? ? ? 129 ldc rm,dbr co 1 3 #14 sx 3 2 130 ldc rm,gbr co 3 3 #15 sx 3 2 131 ldc rm,rp_bank co 1 3 #14 sx 3 2 132 ldc rm,sr co 4 4 #16 sx 3 2 133 ldc rm,ssr co 1 3 #14 sx 3 2 134 ldc rm,spc co 1 3 #14 sx 3 2 135 ldc rm,vbr co 1 3 #14 sx 3 2 136 ldc.l @rm+,dbr co 1 1/3 #17 sx 3 2 137 ldc.l @rm+,gbr co 3 3/3 #18 sx 3 2 138 ldc.l @rm+,rp_bank co 1 1/3 #17 sx 3 2 139 ldc.l @rm+,sr co 4 4/4 #19 sx 3 2 140 ldc.l @rm+,ssr co 1 1/3 #17 sx 3 2 141 ldc.l @rm+,spc co 1 1/3 #17 sx 3 2 142 ldc.l @rm+,vbr co 1 1/3 #17 sx 3 2 143 lds rm,mach co 1 3 #28 f1 3 2 144 lds rm,macl co 1 3 #28 f1 3 2 145 lds rm,pr co 2 3 #24 sx 3 2 146 lds.l @rm+,mach co 1 1/3 #29 f1 3 2 147 lds.l @rm+,macl co 1 1/3 #29 f1 3 2 148 lds.l @rm+,pr co 2 2/3 #25 sx 3 2 149 stc dbr,rn co 2 2 #20 ? ? ? system control instructions 150 stc sgr,rn co 3 3 #21 ? ? ?
section 8 pipelining SH7750, SH7750s, SH7750r group page 254 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 151 stc gbr,rn co 2 2 #20 ? ? ? 152 stc rp_bank,rn co 2 2 #20 ? ? ? 153 stc sr,rn co 2 2 #20 ? ? ? 154 stc ssr,rn co 2 2 #20 ? ? ? 155 stc spc,rn co 2 2 #20 ? ? ? 156 stc vbr,rn co 2 2 #20 ? ? ? 157 stc.l dbr,@-rn co 2 2/2 #22 ? ? ? 158 stc.l sgr,@-rn co 3 3/3 #23 ? ? ? 159 stc.l gbr,@-rn co 2 2/2 #22 ? ? ? 160 stc.l rp_bank,@-rn co 2 2/2 #22 ? ? ? 161 stc.l sr,@-rn co 2 2/2 #22 ? ? ? 162 stc.l ssr,@-rn co 2 2/2 #22 ? ? ? 163 stc.l spc,@-rn co 2 2/2 #22 ? ? ? 164 stc.l vbr,@-rn co 2 2/2 #22 ? ? ? 165 sts mach,rn co 1 3 #30 ? ? ? 166 sts macl,rn co 1 3 #30 ? ? ? 167 sts pr,rn co 2 2 #26 ? ? ? 168 sts.l mach,@-rn co 1 1/1 #31 ? ? ? 169 sts.l macl,@-rn co 1 1/1 #31 ? ? ? system control instructions 170 sts.l pr,@-rn co 2 2/2 #27 ? ? ? 171 fldi0 frn ls 1 0 #1 ? ? ? 172 fldi1 frn ls 1 0 #1 ? ? ? 173 fmov frm,frn ls 1 0 #1 ? ? ? 174 fmov.s @rm,frn ls 1 2 #2 ? ? ? 175 fmov.s @rm+,frn ls 1 1/2 #2 ? ? ? 176 fmov.s @(r0,rm),frn ls 1 2 #2 ? ? ? 177 fmov.s frm,@rn ls 1 1 #2 ? ? ? 178 fmov.s frm,@-rn ls 1 1/1 #2 ? ? ? 179 fmov.s frm,@(r0,rn) ls 1 1 #2 ? ? ? 180 flds frm,fpul ls 1 0 #1 ? ? ? single- precision floating- point instructions 181 fsts fpul,frn ls 1 0 #1 ? ? ?
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 255 of 1076 sep 24, 2013 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 182 fabs frn ls 1 0 #1 ? ? ? 183 fadd frm,frn fe 1 3/4 #36 ? ? ? 184 fcmp/eq frm,frn fe 1 2/4 #36 ? ? ? 185 fcmp/gt frm,frn fe 1 2/4 #36 ? ? ? 186 fdiv frm,frn fe 1 12/13 #37 f3 2 10 f1 11 1 187 float fpul,frn fe 1 3/4 #36 ? ? ? 188 fmac fr0,frm,frn fe 1 3/4 #36 ? ? ? 189 fmul frm,frn fe 1 3/4 #36 ? ? ? 190 fneg frn ls 1 0 #1 ? ? ? 191 fsqrt frn fe 1 11/12 #37 f3 2 9 f1 10 1 192 fsub frm,frn fe 1 3/4 #36 ? ? ? 193 ftrc frm,fpul fe 1 3/4 #36 ? ? ? 194 fmov drm,drn ls 1 0 #1 ? ? ? 195 fmov @rm,drn ls 1 2 #2 ? ? ? 196 fmov @rm+,drn ls 1 1/2 #2 ? ? ? 197 fmov @(r0,rm),drn ls 1 2 #2 ? ? ? 198 fmov drm,@rn ls 1 1 #2 ? ? ? 199 fmov drm,@-rn ls 1 1/1 #2 ? ? ? single- precision floating- point instructions 200 fmov drm,@(r0,rn) ls 1 1 #2 ? ? ? 201 fabs drn ls 1 0 #1 ? ? ? 202 fadd drm,drn fe 1 (7, 8)/9 #39 f1 2 6 203 fcmp/eq drm,drn co 2 3/5 #40 f1 2 2 204 fcmp/gt drm,drn co 2 3/5 #40 f1 2 2 205 fcnvds drm,fpul fe 1 4/5 #38 f1 2 2 206 fcnvsd fpul,drn fe 1 (3, 4)/5 #38 f1 2 2 f3 2 23 f1 22 3 207 fdiv drm,drn fe 1 (24, 25)/ 26 #41 f1 2 2 208 float fpul,drn fe 1 (3, 4)/5 #38 f1 2 2 double- precision floating- point instructions 209 fmul drm,drn fe 1 (7, 8)/9 #39 f1 2 6
section 8 pipelining SH7750, SH7750s, SH7750r group page 256 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 lock functional category no. instruction instruc- tion group issue rate latency execu- tion pattern stage start cycles 210 fneg drn ls 1 0 #1 ? ? ? f3 2 22 f1 21 3 211 fsqrt drn fe 1 (23, 24)/ 25 #41 f1 2 2 212 fsub drm,drn fe 1 (7, 8)/9 #39 f1 2 6 double- precision floating- point instructions 213 ftrc drm,fpul fe 1 4/5 #38 f1 2 2 214 lds rm,fpul ls 1 1 #1 ? ? ? 215 lds rm,fpscr co 1 4 #32 f1 3 3 216 lds.l @rm+,fpul co 1 1/2 #2 ? ? ? 217 lds.l @rm+,fpscr co 1 1/4 #33 f1 3 3 218 sts fpul,rn ls 1 3 #1 ? ? ? 219 sts fpscr,rn co 1 3 #1 ? ? ? 220 sts.l fpul,@-rn co 1 1/1 #2 ? ? ? fpu system control instructions 221 sts.l fpscr,@-rn co 1 1/1 #2 ? ? ? 222 fmov drm,xdn ls 1 0 #1 ? ? ? 223 fmov xdm,drn ls 1 0 #1 ? ? ? 224 fmov xdm,xdn ls 1 0 #1 ? ? ? 225 fmov @rm,xdn ls 1 2 #2 ? ? ? 226 fmov @rm+,xdn ls 1 1/2 #2 ? ? ? 227 fmov @(r0,rm),xdn ls 1 2 #2 ? ? ? 228 fmov xdm,@rn ls 1 1 #2 ? ? ? 229 fmov xdm,@-rm ls 1 1/1 #2 ? ? ? 230 fmov xdm,@(r0,rn) ls 1 1 #2 ? ? ? 231 fipr fvm,fvn fe 1 4/5 #42 f1 3 1 232 frchg fe 1 1/4 #36 ? ? ? 233 fschg fe 1 1/4 #36 ? ? ? f0 2 4 graphics acceleration instructions 234 ftrv xmtrx,fvn fe 1 (5, 5, 6, 7)/8 #43 f1 3 4 notes: 1. see table 8.1 fo r the instruction groups. 2. latency ?l1/l2...?: latency corresponding to a write to each register , including mach/macl/fpscr. example: mov.b @rm+, rn ?1/2?: the lat ency for rm is 1 cycle, and the latency for rn is 2 cycles. 3. branch latency: interval until the branch destination instruction is fetched
SH7750, SH7750s, SH7750r group section 8 pipelining r01uh0456ej0702 rev. 7.02 page 257 of 1076 sep 24, 2013 4. conditional branch latency ?2 (or 1)?: the latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. double-precision floating-point instruction latency ?(l1, l2)/l3?: l1 is the latency for fr [n+1], l2 that for fr [n], and l3 that for fpscr. 6. ftrv latency ?(l1, l2, l3, l4)/l5?: l1 is t he latency for fr [n], l2 that for fr [n+1], l3 that for fr [n+2], l4 that for fr [n+3], and l5 that for fpscr. 7. latency ?l1/l2/l3/l4? of mac.l and mac.w instructions: l1 is the latency for rm, l2 that for rn, l3 that for mach, and l4 that for macl. 8. latency ?l1/l2? of mul.l, muls.w, mu lu.w, dmuls.l, and dmulu.l instructions: l1 is the latency for mach, and l2 that for macl. 9. execution pattern: the instruction execution pattern number (see figure 8.2) 10. lock/stage: stage lock ed by the instruction 11. lock/start: locking start cycle; 1 is the first d-stage of the instruction. 12. lock/cycles: number of cycles locked exceptions: 1. when a floating-point computation instru ction is followed by an fmov store, an sts fpul, rn instruction, or an sts.l fpul, @-rn instruction, the la tency of the floating- point computation is decreased by 1 cycle. 2. when the preceding instruction loads the shift amount of the following shad/shld, the latency of the load is increased by 1 cycle. 3. when an ls group instruction with a laten cy of less than 3 cycles is followed by a double-precision floating-point instruction, fipr, or ftrv, the latency of the first instruction is increased to 3 cycles. example: in the case of fmov fr4,fr0 and fipr fv0,fv4, fipr is stalled for 2 cycles. 4. when mac/mul/dmul is followed by an st s.l mac, @-rn instruct ion, the latency of mac/mul/dmul is 5 cycles. 5. in the case of consecutive executions of mac/mul/dmul, the latency is decreased to 2 cycles. 6. when an lds to mac is followed by an st s.l mac, @-rn instruct ion, the latency of the lds to mac is 4 cycles. 7. when an lds to mac is followed by mac/ mul/dmul, the latency of the lds to mac is 1 cycle. 8. when an fschg or frchg instruction is followed by an ls group instruction that reads or writes to a floating-point register , the aforementioned ls group instruction[s] cannot be executed in parallel. 9. when a single-precision ftrc instruction is followed by an ?sts fpul, rn? instruction, the latency of the single-precision ftrc instruction is 1 cycle.
section 8 pipelining SH7750, SH7750s, SH7750r group page 258 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 8.4 usage notes the following are additional notes on pipeline operation and the method of calculating the number of clock cycles. the number of states (i clock cy cles) required for stages where an external bus access, etc., occurs may include an increased number of cycles, in a ddition to the number of memory access cycles set by the bus state controller (bsc), etc. for example, the occurrence of th e following may result in idle cycles as observed from the external bus. 1. transfer of data from the logical address bus to the physical address bus 2. transfer of data between buses using different operation clocks the stages where external memory access occurs include some instruction fetch (i) and some memory access (ma) stages.
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 259 of 1076 sep 24, 2013 section 9 power-down modes 9.1 overview in the power-down modes, some of the on-chip peripheral modules and the cpu functions are halted, enabling power consumption to be reduced. 9.1.1 types of power-down modes the following power-down modes and functions are provided: ? sleep mode ? deep sleep mode ? standby mode ? hardware standby mode* ? module standby function (tmu, rtc, sci/scif, dmac, sq*, and ubc*) note: * SH7750s, SH7750r only table 9.1 shows the conditions for entering thes e modes from the progra m execution state, the status of the cpu and peripheral modules in each mode, and the method of exiting each mode.
section 9 power-down modes SH7750, SH7750s, SH7750r group page 260 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 9.1 status of cpu and peripheral modules in power-down modes status power- down mode entering conditions cpg cpu on-chip memory on-chip peripheral modules pins external memory exiting method sleep sleep instruction executed while stby bit is 0 in stbcr operating halted (registers held) held operating held refreshing ? interrupt ? reset deep sleep sleep instruction executed while stby bit is 0 in stbcr, and dslp bit is 1 in stbcr2 operating halted (registers held) held operating (dma halted) held self- refreshing ? interrupt ? reset standby sleep instruction executed while stby bit is 1 in stbcr halted halted (registers held) held halted * held self- refreshing ? interrupt ? reset hardware standby (SH7750s, SH7750r) setting ca pin low halted halted undefined halted * high impedance undefined ? power-on reset module standby setting mstp bit to 1 in stbcr/ stbcr2 operating operating held specified modules halted * held refreshing ? clearing mstp bit to 0 ? reset note: * the rtc operates when the start bit in rcr2 is 1 (see section 11, realtime clock (rtc)).
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 261 of 1076 sep 24, 2013 9.1.2 register configuration table 9.2 shows the registers used for power-down mode control. table 9.2 power-down mode registers name abbreviation r/w initial value p4 address area 7 address access size standby control register stbcr r/w h'00 h 'ffc00004 h'1fc00004 8 standby control register 2 stbcr2 r/w h'00 h 'ffc00010 h'1fc00010 8 clock stop register 00 * clkstp00 r/w h'00000000 h 'fe0a0000 h'1e0a0000 32 clock release register 00 * clkstpclr00 w h'00000000 h'fe0a0008 h'1e0a0008 32 note: * SH7750r only 9.1.3 pin configuration table 9.3 shows the pins used for power-down mode control. table 9.3 power-down mode pins pin name abbreviation i/o function processor status 1 processor status 0 status1 status0 output indicate the proc essor's operating status. (status1, status0) hh: reset hl: sleep mode lh: standby mode ll: normal operation hardware standby request (SH7750s and SH7750r only) ca input transits to har dware standby mode by a low-level input to the pin. legend: h: high level l: low level
section 9 power-down modes SH7750, SH7750s, SH7750r group page 262 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 9.2 register descriptions 9.2.1 standby control register (stbcr) the standby control register (stbcr) is an 8-b it readable/writable register that specifies the power-down mode status. it is initialized to h'00 by a power-on reset via the reset pin or due to watchdog timer overflow. bit: 7 6 5 4 3 2 1 0 stby phz ppu mstp4 mstp3 mstp2 mstp1 mstp0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?standby (stby): specifies a transition to standby mode. bit 7: stby description 0 transition to sleep mode on execution of sleep instruction (initial value) 1 transition to standby mode on execution of sleep instruction bit 6?peripheral module pin high impedance control (phz): controls the state of peripheral module related pins in standby mode. when the phz bit is set to 1, peripheral module related pins go to the high-impedance state in standby mode. for the relevant pins, see section 9.2.2, peripheral module pin high impedance control. bit 6: phz description 0 peripheral module related pins are in normal state (initial value) 1 peripheral module related pins go to high-impedance state bit 5?peripheral module pin pull-up control (ppu): controls the state of peripheral module related pins. when the ppu bit is cleared to 0, the pull-up resistor is turned on for peripheral module related pins in the inpu t or high-impedance state. for the relevant pins, see section 9.2.3, peripheral module pin pull-up control. bit 5: ppu description 0 peripheral module related pin pull-up resistors are on (initial value) 1 peripheral module related pin pull-up resistors are off
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 263 of 1076 sep 24, 2013 bit 4?module stop 4 (mstp4): specifies stopping of the clock supply to the dmac among the on-chip peripheral modules. the clock supply to the dmac is stopped when the mstp4 bit is set to 1. when dma transfer is used, stop the transf er before setting the mstp4 bit to 1. when dma transfer is performed after clearing the mstp4 bit to 0, dmac settings must be made again. bit 4: mstp4 description 0 dmac operates (initial value) 1 dmac clock supply is stopped bit 3?module stop 3 (mstp3): specifies stopping of the clock supply to serial communication interface channel 2 (scif) among the on-chip periphe ral modules. the clock supply to the scif is stopped when the mstp3 bit is set to 1. bit 3: mstp3 description 0 scif operates (initial value) 1 scif clock supply is stopped bit 2?module stop 2 (mstp2): specifies stopping of the clock supply to the timer unit (tmu) among the on-chip peripheral modules. the clock supply to the tmu is stopped when the mstp2 bit is set to 1. bit 2: mstp2 description 0 tmu operates (initial value) 1 tmu clock supply is stopped bit 1?module stop 1 (mstp1): specifies stopping of the clock supply to the realtime clock (rtc) among the on-chip peripheral modules. the clock supply to the rtc is stopped when the mstp1 bit is set to 1. when the clock supply is stopped, rtc re gisters cannot be accessed but the counters continue to operate. bit 1: mstp1 description 0 rtc operates (initial value) 1 rtc clock supply is stopped
section 9 power-down modes SH7750, SH7750s, SH7750r group page 264 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 0?module stop 0 (mstp0): specifies stopping of the clock supply to serial communication interface channel 1 (sci) among the on-chip periphe ral modules. the clock supply to the sci is stopped when the mstp0 bit is set to 1. bit 0: mstp0 description 0 sci operates (initial value) 1 sci clock supply is stopped 9.2.2 peripheral module pin high impedance control when bit 6 in the standby control register (stbcr) is set to 1, peripheral module related pins go to the high-impedance st ate in standby mode. ? relevant pins sci related pins md0/sck md1/txd2 md7/txd md8/rts2 cts2 dma related pins dack0 drak0 dack1 drak1 ? other information the setting in this register is invalid when the above pins are used as port output pins. for details of pin states, see appendix e, pin functions.
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 265 of 1076 sep 24, 2013 9.2.3 peripheral module pin pull-up control when bit 5 in the standby control register (stbcr) is cleared to 0, peripheral module related pins are pulled up when in the in put or high-impedance state. ? relevant pins sci related pins md0/sck md1/txd2 md2/rxd2 md7/txd md8/rts2 sck2/ mreset rxd cts2 dma related pins dreq0 dack0 drak0 dreq1 dack1 drak1 tmu related pin tclk ? other information the setting in this register is invalid in the hardware standby mode. for details of pin states, see appendix e, pin functions. 9.2.4 standby control register 2 (stbcr2) standby control register 2 (stbcr2) is an 8-bit re adable/writable register that specifies the sleep mode and deep sleep mode transition conditions. it is initialized to h'00 by a power-on reset via the reset pin or due to watchdog timer overflow. bit: 7 6 5 4 3 2 1 0 dslp sthz ? ? ? ? mstp6 * mstp5 * initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r r r/w r/w note: * reserved bit in the SH7750.
section 9 power-down modes SH7750, SH7750s, SH7750r group page 266 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 7?deep sleep (dslp): specifies a transition to deep sleep mode bit 7: dslp description 0 transition to sleep mode or stand by mode on execution of sleep instruction, according to setting of stby bit in stbcr register (initial value) 1 transition to deep sleep mode on execution of sleep instruction * note: * when the stby bit in the stbcr register is 0 bit 6?status pin high-impedance control (sthz): this bit selects whether the status0 and status1 pins are set to high-impedance when in hardware standby mode. bit 6: sthz description 0 sets status0, 1 pins to high-impedance when in hardware standby mode (initial value) 1 drives status0, 1 pins to lh when in hardware standby mode bits 5 to 2?reserved: only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. these bits are always read as 0. bits 1 and 0 (SH7750)?reserved: only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. these bits are always read as 0. bit 1 (SH7750s and SH7750r)?module stop 6 (mstp6): specifies that the clock supply to the store queue (sq) in the cache controller (ccn) is stopped. setting the mstp6 bit to 1 stops the clock supply to the sq, and the sq functions are therefore unavailable. bit 1: mstp6 description 0 sq operating (initial value) 1 clock supply to sq stopped bit 0 (SH7750s and SH7750r)?module stop 5 (mstp5): specifies stopping of the clock supply to the user break controller (ubc) among the on-chip peripheral modules. see section 20.6, user break controller stop function, for how to set the clock supply. bit 0: mstp5 description 0 ubc operating (initial value) 1 clock supply to ubc stopped
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 267 of 1076 sep 24, 2013 9.2.5 clock-stop register 00 (clkstp00) (SH7750r only) clock-stop register 00 (clkstp00) controls the operation clock for peripheral modules. to resume supply of the clock signal, write a 1 to the corresponding bit in the clkstpclr00 register. writing a 0 to the clkstp00 register does not affect the register's value. the clkstp00 register is a 32-bit register that can be read from or written to. it is initialized to h'0000 0000 by a power-on reset, but not by a manual reset or when the device enters standby mode. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? cstp1 cstp0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r/w r/w bits 31 to 2?reserved: any data written to these bits should always be 0. these bits are always read as 0. bit 1?clock stop 1 (cstp1): this bit specifies stopping of the peripheral clock supply to channels 3 and 4 of the timer unit (tmu). bit 1: cstp1 description 0 peripheral clock is supplied to tmu channels 3 and 4 (initial value) 1 peripheral clock supply to tmu channels 3 and 4 is stopped bit 0 ? clock stop 0 (cstp0): specifies stopping of the peripheral clock supply to the interrupt controller (intc). if this bit is set, intc does not detect interrupts on the tmu's channels 3 and 4. bit 0: cstp0 description 0 intc detects interrupts on channels 3 and 4 of the tmu (initial value) 1 intc does not detect interrupt s on channels 3 and 4 of the tmu
section 9 power-down modes SH7750, SH7750s, SH7750r group page 268 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 9.2.6 clock-stop clear register 00 (clkstpclr00) (SH7750r only) the clock-stop clear register 00 (clkstpclr00) is a 32-bit write-only register that clears the corresponding bits of the clkstp00 register. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: w w w w w w w w w w w w w w w w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: w w w w w w w w w w w w w w w w bits 31 to 0 ? clock-stop clear: specify whether or not to clear the corresponding bit of the clock-stop setting. see section 9.2.5, clock-stop register 00 (clkstp00) (SH7750r only), for the correspondence between the bits and the clocks that are stopped. bits 31 to 0 description 0 does not change the clock-stop setting for the corresponding clock 1 clears the clock-stop setting for the corresponding clock 9.3 sleep mode 9.3.1 transition to sleep mode if a sleep instruction is executed when the stby bit in stbcr is cleared to 0, the chip switches from the program execution state to sleep mode. after execution of the sleep instruction, the cpu halts but its register contents are retained. the on-chip peripheral modules continue to operate, and the clock continues to be output from the ckio pin. in sleep mode, a high-level signal is output at the status1 pin, and a low-level signal at the status0 pin.
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 269 of 1076 sep 24, 2013 9.3.2 exit from sleep mode sleep mode is exited by means of an interrupt (nmi, irl, or on-chip peripheral module) or a reset. in sleep mode, interrupts are accepted even if the bl bit in the sr register is 1. if necessary, spc and ssr should be saved to the stack before executing the sleep instruction. exit by interrupt: when an nmi, irl, or on-chip peripheral module interrupt is generated, sleep mode is exited and interrupt exception handling is executed. the code corresponding to the interrupt source is set in the intevt register. exit by reset: sleep mode is exited by means of a power-on or manual reset via the reset pin, or a power-on or manual reset executed when the watchdog timer overflows. 9.4 deep sleep mode 9.4.1 transition to deep sleep mode if a sleep instruction is executed when the stby bit in stbcr is cleared to 0 and the dslp bit in stbcr2 is set to 1, the chip switches from the program execution state to deep sleep mode. after execution of the sleep inst ruction, the cpu halts but its register contents are retained. except for the dmac*, on-chip peripheral modules continue to operate. the clock continues to be output to the ckio pin, but all bus access (inc luding auto refresh) st ops. when using memory that requires refreshing, set the self-refresh function prior to making the transition to deep sleep mode. in deep sleep mode, a high-level signal is output at the status1 pin, and a low-level signal at the status0 pin. note: * terminate dma transfers prior to making the transition to deep sleep mode. if you make a transition to deep sleep mode while dma transfers are in progress, the results of those transfers cannot be guaranteed. 9.4.2 exit from deep sleep mode as with sleep mode, deep sleep mode is exited by means of an interrupt (nmi, irl, or on-chip peripheral module) or a reset.
section 9 power-down modes SH7750, SH7750s, SH7750r group page 270 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 9.5 standby mode 9.5.1 transition to standby mode if a sleep instruction is executed when the stby bit in stbcr is set to 1, the chip switches from the program execution state to standby mode. in standby mode, the on-chip peripheral modules halt as well as the cpu. clock output from the ckio pin is also stopped. the cpu and cache register contents are retained . some on-chip peripheral module registers are initialized. the state of the peri pheral module registers in standby mode is shown in table 9.4. table 9.4 state of registers in standby mode module initialized registers registers that retain their contents interrupt controller ? all registers user break controller ? all registers bus state controller ? all registers on-chip oscillation circuits ? all registers timer unit tstr register * all registers except tstr realtime clock ? all registers direct memory access controller ? all registers serial communication interface see appendix a, address list see appendix a, address list notes: dma transfer should be terminated before making a transition to standby mode. transfer results are not guaranteed if standby mode is entered during transfer. * not initialized when the realtime clock (rtc) is in use (see section 12, timer unit (tmu)). the procedure for a transition to standby mode is shown below. 1. clear the tme bit in the wdt timer contro l register (wtcsr) to 0, and stop the wdt. set the initial value for the up-count in the wdt timer counter (wtcnt), and set the clock to be used for the up-count in bits cks2?cks0 in the wtcsr register. 2. set the stby bit in the stbcr register to 1, then execute a sleep instruction. 3. when standby mode is entered and the chip's internal clock stops, a low-level signal is output at the status1 pin, and a high-lev el signal at the status0 pin.
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 271 of 1076 sep 24, 2013 9.5.2 exit from standby mode standby mode is exited by means of an interrupt (nmi, irl, or on-chip peripheral module) or a reset via the reset pin. exit by interrupt: a hot start can be performed by means of the on-chip wdt. when an nmi, irl* 1 , rtc, or gpio* 2 interrupt is detected, the wdt starts counting. after the count overflows, clocks are supplied to the entire chip, standby mode is exited, and the status1 and status0 pins both go low. interrupt exception handling is then executed, and the code corresponding to the interrupt source is set in the intevt register. in standby mode, interrupts are accepted even if the bl bit in the sr register is 1, and so, if necessary, spc and ssr should be saved to the stack before executing the sleep instruction. the phase of the ckio pin clock output may be unstable immediately after an interrupt is detected, until standby mode is exited. notes: 1. only when the rtc clock (32.768 khz) is operating (see section 19.2.2, irl interrupts), standby mode can be exited by means of irl3?irl0 (when the irl3? irl0 level is higher than the sr register imask mask level). 2. gpio can be used to cancel standby mode when th e rtc clock (32.768 khz) is operating (when the gpio level is higher than the sr register imask mask level). exit by reset: standby mode is exited by means of a reset (power-on or manual) via the reset pin. the reset pin should be held low until clock oscillation stabilizes. the internal clock continues to be output at the ckio pin. 9.5.3 clock pause function in standby mode, it is possible to stop or change the frequency of the clock input from the extal pin. this function is used as follows. 1. enter standby mode following the transition procedure described above. 2. when standby mode is entered and the chip's internal clock stops, a low-level signal is output at the status1 pin, and a high-lev el signal at the status0 pin. 3. the input clock is stopped, or its frequency changed, after the status1 pin goes low and the status0 pin high. 4. when the frequency is changed, input an nm i or irl interrupt after the change. when the clock is stopped, input an nmi or irl interrupt after applying the clock. 5. after the time set in the wdt, clock supply begins inside the chip, the status1 and status0 pins both go low, and operation is resumed from interrupt exception handling.
section 9 power-down modes SH7750, SH7750s, SH7750r group page 272 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 9.6 module standby function 9.6.1 transition to module standby function setting the mstp6?mstp0, cstp1, and cstp0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. use of this function allows power consumption in sleep mode to be further reduced. in the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules.
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 273 of 1076 sep 24, 2013 bit description cstp1 * 6 0 peripheral clock is supplied to tmu channels 3 and 4 1 peripheral clock supplied to tmu channels 3 and 4 is stopped cstp0 * 6 0 intc detects interrupts on tmu channels 3 and 4 1 intc does not detect interrupts on tmu channels 3 and 4 mstp6 * 4 0 sq operates 1 clock supplied to sq is stopped mstp5 * 4 0 ubc operates 1 clock supplied to ubc is stopped * 5 mstp4 0 dmac operates 1 clock supplied to dmac is stopped * 3 mstp3 0 scif operates 1 clock supplied to scif is stopped mstp2 0 tmu operates 1 clock supplied to tmu is stopped, and register is initialized * 1 mstp1 0 rtc operates 1 clock supplied to rtc is stopped * 2 mstp0 0 sci operates 1 clock supplied to sci is stopped notes: 1. the register initialized is the same as in standby mode, but initialization is not performed if the rtc clock is not in us e (see section 12, timer unit (tmu)). 2. the counter operates when the start bi t in rcr2 is 1 (see section 11, realtime clock (rtc)). 3. terminate dma transfers prior to making the transition to module standby mode. if you make a transition to module standby mode while dma transfers are in progress, the results of those transfe rs cannot be guaranteed. 4. SH7750s, SH7750r only 5. for details, see section 20.6, user break controller stop function. 6. SH7750r only 9.6.2 exit from module standby function the module standby function is exited by clear ing the mstp6?mstp0, cs tp1, and cstp0 bits to 0, or by a power-on reset via the reset pin or a power-on reset caused by watchdog timer overflow.
section 9 power-down modes SH7750, SH7750s, SH7750r group page 274 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 9.7 hardware standby mode (SH7750s, SH7750r only) 9.7.1 transition to hardware standby mode setting the ca pin level low effects a transition to hardware standby mode. in this mode, all modules other than the rtc stop, as in the st andby mode selected using the sleep command. hardware standby mode differs from standby mode as follows: 1. interrupts and manual resets are not available; 2. all output pins other than the status pin are in the high-impedance state and the pull-up resistance is off. 3. on the SH7750s, the rtc continues to operate even when no power is supplied to power pins other than the rtc power supply pin. the status of the status pin is determined by the sthz bit of stbcr2. see appendix e, pin functions, for details of output pin states. operation when a low-level is input to the ca pin when in the standby mode depends on the cpg status, as follows: 1. in standby mode the clock remains stopped and a transition is made to the hardware standby state. 2. when wdt is operating when standby mode is exited by interrupt standby mode is momentarily exited, the cpu restarts, and then a transition is made to hardware standby mode. note that the level of the ca pin must be kept low while in hardware standby mode. 9.7.2 exit from hardware standby mode hardware standby mode can only be exited by effecting a power-on reset. setting the ca pin level high after the reset pin level has been set low and the sck2 pin high starts the clock to oscillate. the reset pin level should be kept low until the clock has stabilized, then set high so that the cpu starts the power-on reset exiting procedure. note that hardware standby mode cannot be exited using interrupts or a manual reset.
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 275 of 1076 sep 24, 2013 9.7.3 usage notes 1. the ca pin level must be kept high when the rtc power supply is started (figure 9.15). 2. on the SH7750r, power must be supplied to the other power supply pins (v dd , v ddq , v dd ? cpg , v dd ? pll1 , and v dd ? pll2 ), in addition to the rtc power supply pin, in hardware standby mode. 9.8 status pin change timing the status1 and status0 pin change timing is shown below. the meaning of the status pin settings is as follows: reset: hh (status1 high, status0 high) sleep: hl (status1 high, status0 low) standby: lh (status1 low, status0 high) normal: ll (status1 low, status0 low) the meaning of the clock units is as follows: bcyc: bus clock cycle pcyc: peripheral clock cycle
section 9 power-down modes SH7750, SH7750s, SH7750r group page 276 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 9.8.1 in reset power-on reset ckio reset status sck2 normal reset normal 0?5 bcyc 0?30 bcyc pll stabilization time figure 9.1 status output in power-on reset manual reset ckio reset * status normal reset normal sck2 0?30 bcyc 0 bcyc note: * in a manual reset, status = hh (reset) is set and an internal reset started after waitin g until the end of the currently executin g bus cycle. must be asserted for t resw or lon g er figure 9.2 status output in manual reset
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 277 of 1076 sep 24, 2013 9.8.2 in exit from standby mode standby interrupt ckio status normal standby normal wdt count oscillation stops interrupt request wdt overflow figure 9.3 status output in standby interrupt sequence standby power-on reset reset ckio r eset * 1 status normal reset normal 0?10 bcyc standby oscillation stops sck2 * 2 0?30 bcyc notes: 1. when standby mode is exited by means of a power-on reset, a wdt count is not performed. hold reset low for the pll oscillation stabilization time. 2. undefined figure 9.4 status output in standby power-on reset sequence
section 9 power-down modes SH7750, SH7750s, SH7750r group page 278 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 standby manual reset reset ckio r eset * 1 status normal reset normal 0?10 bcyc standby oscillation stops sck2 * 2 0?30 bcyc notes: 1. when standby mode is exited by means of a manual reset, a wdt count is not performed. hold reset low for the pll oscillation stabilization time. 2. undefined figure 9.5 status output in standby manual reset sequence
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 279 of 1076 sep 24, 2013 9.8.3 in exit from sleep mode sleep interrupt ckio status normal sleep normal interrupt request figure 9.6 status output in sleep interrupt sequence sleep power-on reset reset ckio status normal reset sleep normal 0?10 bcyc 0?30 bcyc r eset * 1 sck2 * 2 notes: 1. when sleep mode is exited by means of a power-on reset, hold reset low for the oscillation stabilization time. 2. undefined figure 9.7 status output in sleep power-on reset sequence
section 9 power-down modes SH7750, SH7750s, SH7750r group page 280 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 sleep manual reset reset reset * status normal reset sleep normal ckio 0?30 bcyc 0?30 bcyc note: * hold reset low until status = reset. sck2 figure 9.8 status output in sleep manual reset sequence
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 281 of 1076 sep 24, 2013 9.8.4 in exit from deep sleep mode deep sleep interrupt ckio status normal sleep normal interrupt request figure 9.9 status output in deep sleep interrupt sequence deep sleep power-on reset reset ckio status normal sleep reset normal 0?10 bcyc 0?30 bcyc reset * 1 sck2 * 2 notes: 1. when deep sleep mode is exited by means of a power-on reset, hold reset low for the oscillation stabilization time. 2. undefined figure 9.10 status output in deep sleep power-on reset sequence
section 9 power-down modes SH7750, SH7750s, SH7750r group page 282 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 deep sleep manual reset reset reset * status normal sleep reset normal ckio 0?30 bcyc 0?30 bcyc note: * hold reset low until status = reset. sck2 figure 9.11 status output in deep sleep manual reset sequence
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 283 of 1076 sep 24, 2013 9.8.5 hardware standby mode timing (SH7750s, SH7750r only) figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. the ca pin level must be kept low while in hardware standby mode. after setting the reset pin level low, the clock starts when the ca pin level is switched to high. ckio ca sck2 (hi g h) status reset 0?10 bcyc 0?10 bcyc reset waitin g for end of bus cycle * 2 notes: 1. same at sleep and reset. 2. undefined 3. hi g h impedance when stbcr2. sthz = 0 normal * 1 standby * 3 figure 9.12 hardware standby mode timing (when ca = low in normal operation)
section 9 power-down modes SH7750, SH7750s, SH7750r group page 284 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio (hi g h) ca status standby 0?10 bcyc normal reset (hi g h) sck2 wdt count wdt overflow interrupt request note: * hi g h impedance when stbcr2. sthz = 0 standby * figure 9.13 hardware standby mode timing (when ca = low in wdt operation)
SH7750, SH7750s, SH7750r group section 9 power-down modes r01uh0456ej0702 rev. 7.02 page 285 of 1076 sep 24, 2013 v ddq * v dd sck2 ca min 0s min 0s max 50 s r eset note: * v ddq , v dd-cpg , v dd-pll1 , v dd-pll2 v dd min figure 9.14 timing when po wer other than vdd-rtc is off ca v dd-rtc sck2 reset v dd , v ddq * min 0s note: * v dd , v dd-pll1/2 , v ddq , v dd-cpg power-on oscillation settin g time figure 9.15 timing when vdd-rtc power is off on
section 9 power-down modes SH7750, SH7750s, SH7750r group page 286 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 9.9 usage notes 9.9.1 note on current consumption after a power-on reset, the current consumption may exceed the maximum value for sleep mode or standby mode during the period until one or more of the arithmetic operation or floating-point operation instructions listed below is executed. 1. arithmetic operation instructions mac.w, mac.l 2. floating-point operation instructions ? when fpscr.pr = 0 fadd, fsub, fmul, fmac, float, ftrc, fdiv, fsqrt, fipr, ftrv ? when fpscr.pr = 1 fadd, fsub, fmul, float, ftrc, fdiv, fsqrt, fcnvsd, fcnvds workaround: after a power-on reset, execute one or more of the above instructions before transitioning to sleep mode or standby mode. example: to reduce the effect on fpscr, arrange the following two instructions starting at h'a0000000. address instruction string h'a0000000 fldi1 fr0 h'a0000002 fadd fr0, fr0 ; fldi1 fr0 loads 1 into fr0, : : ; so the cause and flag bits of fpscr are not set to 1.
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 287 of 1076 sep 24, 2013 section 10 clock os cillation circuits 10.1 overview the on-chip oscillation circuits comprise a cl ock pulse generator (cpg) and a watchdog timer (wdt). the cpg generates the clocks supplied inside the processor and performs power-down mode control. the wdt is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed. it can be used as a normal watchdog timer or an interval timer. 10.1.1 features the cpg has the following features: ? three clocks the cpg can generate the cpu clock (ick) us ed by the cpu, fpu, caches, and tlb, the peripheral module clock (pck) used by the peripheral modules, and the bus clock (bck) used by the external bus interface. ? six clock modes any of six clock operating modes can be selected, with different combinations of cpu clock, bus clock, and peripheral module clock division ratios after a power-on reset. ? frequency change function pll (phase-locked loop) circuits and a frequency divider in the cpg enable the cpu clock, bus clock, and peripheral module clock frequencies to be changed independently. frequency changes are performed by software in accordance with the settings in the frequency control register (frqcr). ? pll on/off control power consumption can be reduced by stopping the pll circuits during low-frequency operation. ? power-down mode control it is possible to stop the clock in sleep mode and standby mode, and to stop specific modules with the module standby function.
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 288 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 the wdt has the following features ? can be used to secure clock stabilization time used when exiting standby mode or a temporary standby state when the clock frequency is changed. ? can be switched between watchdog timer mode and interval timer mode ? internal reset generation in watchdog timer mode an internal reset is executed on counter overflow. power-on reset or manual reset can be selected. ? interrupt generation in interval timer mode an interval timer interrupt is generated on counter overflow. ? selection of eight counter input clocks any of eight clocks can be selected, scaled from the 1 clock of frequency divider 2 shown in figure 10.1. the cpg is described in sections 10.2 to 10.6, and the wdt in sections 10.7 to 10.9.
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 289 of 1076 sep 24, 2013 10.2 overview of cpg 10.2.1 block diagram of cpg figure 10.1 (1) shows a block diagram of the cpg in the SH7750 and SH7750s, and figure 10.1 (2) a block diagram of the cpg in the SH7750r. legend: frqcr: frequency control register stbcr: standby control register stbcr2: standby control register 2 oscillator circuit pll circuit 1 frequency divider 2 crystal oscillation circuit frequency divider 1 pll circuit 2 cpu clock (ick) cycle icyc peripheral module clock (pck) cycle pcyc bus clock (bck) cycle bcyc cpg control unit clock frequency control circuit standby control circuit bus interface internal bus xtal extal md8 ckio md2 md1 md0 frqcr stbcr2 1 1/2 1/3 1/4 1/6 1/8 6 1/2 1 stbcr figure 10.1 (1) block diagram of cpg (SH7750, SH7750s)
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 290 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 legend: frqcr: stbcr: stbcr2: frequency control register standby control register standby control register 2 oscillator circuit pll circuit 1 frequency divider 2 crystal oscillation circuit cpu clock (ick) cycle icyc peripheral module clock (pck) cycle pcyc bus clock (bck) cycle bcyc cpg control unit clock frequency control circuit standby control circuit bus interface internal bus xtal extal md8 ckio md2 md1 md0 frqcr stbcr2 1 1/2 1/3 1/4 1/6 1/8 6 12 pll circuit 2 1 stbcr figure 10.1 (2) block diagram of cpg (SH7750r)
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 291 of 1076 sep 24, 2013 the function of each of the cpg blocks is described below. pll circuit 1: pll circuit 1 has a function for multiplying the clock frequency from the extal pin or crystal oscillation circuit by 6 with the SH7750 and SH7750s, and by 6 or 12 with the SH7750r. starting and stopping is controlled by a frequency control register setting. control is performed so that the internal clock rising edge phase matches the input clock rising edge phase. pll circuit 2: pll circuit 2 coordinates the phases of the bus clock and the ckio pin output clock. starting and stopping is controlled by a frequency control register setting. crystal oscillation circuit: this is the oscillator circuit used when a crystal resonator is connected to the xtal and extal pins. use of th e crystal oscillation circuit can be selected with the md8 pin. frequency divider 1 (SH7750 and SH7750s only): frequency divider 1 has a function for adjusting the clock waveform duty to 50 % by halving the input clock frequency when clock input from the extal pin is supplied internally without using pll circuit 1. frequency divider 2: frequency divider 2 generates the cpu clock (ick), bus clock (bck), and peripheral module clock (pck). the division ratio is set in the frequency control register. clock frequency control circuit: the clock frequency control circuit controls the clock frequency by means of the md pins and frequency control register. standby control circuit: the standby control circuit controls the state of the on-chip oscillation circuits and other modules when the clock is switched and in sleep and standby modes. frequency control register (frqcr): the frequency control register contains control bits for clock output from the ckio pin, pll circuit 1 and 2 on/off control, and the cpu clock, bus clock, and peripheral module clock frequency division ratios. standby control register (stbcr): the standby control register contains power save mode control bits. for further information on the standby control register, see section 9, power-down modes. standby control register 2 (stbcr2): standby control register 2 contains a power save mode control bit. for further information on standby control register 2, see section 9, power-down modes.
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 292 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 10.2.2 cpg pin configuration table 10.1 shows the cpg pins and their functions. table 10.1 cpg pins pin name abbreviation i/o function mode control pins md0 input set clock operating mode md1 md2 xtal output connects crystal resonator extal input connects crystal resonator, or used as external clock input pin crystal i/o pins (clock input pins) md8 input selects use/non-u se of crystal resonator when md8 = 0, external clock is input from extal when md8 = 1, crystal resonator is connected directly to extal and xtal clock output pin ckio output used as external clock output pin level can also be fixed ckio enable pin cke output 0 when ckio output clock is unstable and in case of synchronous dram self-refreshing * note: * set to 1 in a power-on reset. for details of synchronous dram self-re freshing, see section 13.3.5, synchronous dram interface. 10.2.3 cpg register configuration table 10.2 shows the cpg register configuration. table 10.2 cpg register name abbreviation r/w initial value p4 address area 7 address access size frequency control register frqcr r/w undefined * h'ffc00000 h'1fc00000 16 note: * depends on the clock operating mode set by pins md2?md0.
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 293 of 1076 sep 24, 2013 10.3 clock operating modes tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various combinations of mode control pin (md2?md0) settings (initial settings such as the frequency division ratio). table 10.4 shows frqcr settings and internal clock frequencies. table 10.3 (1) clock operating modes (SH7750, SH7750s) external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 1/2 frequency divider pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 0 off on on 6 3/2 3/2 h'0e1a 1 0 1 off on on 6 1 1 h'0e23 2 0 on on on 3 1 1/2 h'0e13 3 0 1 1 off on on 6 2 1 h'0e13 4 0 on on on 3 3/2 3/4 h'0e0a 5 1 0 1 off on on 6 3 3/2 h'0e0a notes: 1. turning on/off of the ? frequency divi der is solely determined by the clock operating mode. 2. for the ranges of input clock frequency, see the descriptions of the extal clock input frequency (f ex ) and ckio clock output (f op ) in section 22.3.1, clock and control signal timing. table 10.3 (2) clock operating modes (SH7750r) external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 0 on ( 12) on 12 3 3 h'0e1a 1 0 1 on ( 12) on 12 3/2 3/2 h'0e2c 2 0 on ( 6) on 6 2 1 h'0e13 3 0 1 1 on ( 12) on 12 4 2 h'0e13 4 0 on ( 6) on 6 3 3/2 h'0e0a 5 0 1 on ( 12) on 12 6 3 h'0e0a 6 1 1 0 off ( 6) off 1 1/2 1/2 h'0808 notes: 1. the multiplication factor of pll 1 is solely determined by the clock operating mode.
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 294 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 2. for the ranges of input clock frequency, see the descriptions of the extal clock input frequency (f ex ) and ckio clock output (f op ) in section 22.3.1, clock and control signal timing. table 10.4 frqcr settings and internal clock frequencies frequency division ratio of frequency divider 2 frqcr (lower 9 bits) cpu clock bus clock pe ripheral module clock h'008 1/2 h'00a 1/4 h'00c 1/2 1/8 h'011 1/3 h'013 1/3 1/6 h'01a 1/4 h'01c 1/4 1/8 h'023 1/6 1/6 h'02c 1 1/8 1/8 h'05a 1/4 h'05c 1/4 1/8 h'063 1/6 1/6 h'06c 1/2 1/8 1/8 h'0a3 1/3 1/6 1/6 h'0ec 1/4 1/8 1/8 note: for the lower 9 bits of frqcr, do not set values other than those shown in the table.
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 295 of 1076 sep 24, 2013 10.4 cpg register description 10.4.1 frequency control register (frqcr) the frequency control register (frqcr) is a 16-b it readable/writable register that specifies use/non-use of clock output from the ckio pin, pll circuit 1 and 2 on/off control, and the cpu clock, bus clock, and periphera l module clock frequency division ratios. only word access can be used on frqcr. frqcr is initialized only by a power-on reset via the reset pin. the initial value of each bit is determined by the clock operating mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ckoen pll1en pll2en ifc2 initial value: 0 0 0 0 1 1 1 ? r/w: r/w r/w r/w r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ifc1 ifc0 bfc2 bfc1 bfc0 pfc2 pfc1 pfc0 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 12?reserved: these bits are always read as 0, and should only be written with 0. bit 11?clock output enable (ckoen): specifies whether a clock is output from the ckio pin or the ckio pin is placed in the high-impedance state. when the ckio pin goes to the high- impedance state, operation conti nues at the operating frequency be fore this state was entered. when the ckio pin becomes high-impedance, it is pulled up. bit 11: ckoen description 0 ckio pin goes to high-impedance state (pulled up * ) 1 clock is output from ckio pin (initial value) note: * it is not pulled up in hardware standby mode.
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 296 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 10?pll circuit 1 enable (pll1en): specifies whether pll circ uit 1 is on or off. bit 10: pll1en description 0 pll circuit 1 is not used 1 pll circuit 1 is used (initial value) bit 9?pll circuit 2 enable (pll2en): specifies whether pll circuit 2 is on or off. bit 9: pll2en description 0 pll circuit 2 is not used 1 pll circuit 2 is used (initial value) bits 8 to 6?cpu clock frequency division ratio (ifc): these bits specify the cpu clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or pll circuit 1 output frequency. bit 8: ifc2 bit 7: ifc1 bit 6: ifc0 description 0 0 0 1 1 1/2 1 0 1/3 1 1/4 1 0 0 1/6 1 1/8 other than the above setting prohibited (do not set)
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 297 of 1076 sep 24, 2013 bits 5 to 3?bus clock frequency division ratio (bfc): these bits specify the bus clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or pll circuit 1 output frequency. bit 5: bfc2 bit 4: bfc1 bit 3: bfc0 description 0 0 0 1 1 1/2 1 0 1/3 1 1/4 1 0 0 1/6 1 1/8 other than the above setting prohibited (do not set) bits 2 to 0?peripheral module clock frequency division ratio (pfc): these bits specify the peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or pll circuit 1 output frequency. bit 2: pfc2 bit 1: pfc1 bit 0: pfc0 description 0 0 0 1/2 1 1/3 1 0 1/4 1 1/6 1 0 0 1/8 other than the above setting prohibited (do not set)
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 298 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 10.5 changing the frequency there are two methods of changing the internal clock frequency: by changing stopping and starting of pll circuit 1, and by changing the frequency division ratio of each clock. in both cases, control is performed by software by means of the frequency control register. these methods are described below. 10.5.1 changing pll circuit 1 starting/stopping (when pll circuit 2 is off) when pll circuit 1 is changed from the stopped to started state, a pll stabilization time is required. the oscillation stabilization time count is performed by the on-chip wdt. 1. set a value in wdt to provide the specified oscillation stabilization time, and stop the wdt. the following settings are necessary: wtcsr register tme bit = 0: wdt stopped wtcsr register cks2?cks0 bits: wdt count clock division ratio wtcnt counter: initial counter value 2. set the pll1en bit to 1. 3. internal processor operation stops temporarily , and the wdt starts counting up. the internal clock stops and an unstable clock is output to the ckio pin. 4. after the wdt count overflows, clock supply begins within the chip and the processor resumes operation. the wdt stops after overflowing. 10.5.2 changing pll circuit 1 starting/stopping (when pll circuit 2 is on) when pll circuit 2 is on, a pll circuit 1 and pll circuit 2 oscillation stabilization time is required. 1. make wdt settings as in section 10.5.1. 2. set the pll1en bit to 1. 3. internal processor operation stops temporarily, pll circuit 1 oscillates, and the wdt starts counting up. the internal clock stops and an unstable clock is output to the ckio pin. 4. after the wdt count overflows, pll circuit 2 starts oscillating. the wdt resumes its up- count from the value set in step 1 above. during this time, also, the internal clock is stopped and an unstable clock is output to the ckio pin. 5. after the wdt count overflows, clock supply begins within the chip and the processor resumes operation. the wdt stops after overflowing.
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 299 of 1076 sep 24, 2013 10.5.3 changing bus clock division ratio (when pll circuit 2 is on) if pll circuit 2 is on when the bus clock frequency division ratio is changed, a pll circuit 2 oscillation stabilization time is required. 1. make wdt settings as in section 10.5.1. 2. set the bfc2?bfc0 bits to the desired value. 3. internal processor operation stops temporarily , and the wdt starts counting up. the internal clock stops and an unstable clock is output to the ckio pin. 4. after the wdt count overflows, clock supply begins within the chip and the processor resumes operation. the wdt stops after overflowing. 10.5.4 changing bus clock division ratio (when pll circuit 2 is off) if pll circuit 2 is off when the bus clock frequency division ratio is changed, a wdt count is not performed. 1. set the bfc2?bfc0 bits to the desired value. 2. the set clock is switched to immediately. 10.5.5 changing cpu or peripheral module clock division ratio when the cpu or peripheral module clock frequency division ratio is changed, a wdt count is not performed. 1. set the ifc2?ifc0 or pfc2?pfc0 bits to the desired value. 2. the set clock is switched to immediately. 10.6 output clock control the ckio pin can be switched between clock output and a fixed level setting by means of the ckoen bit in the frqcr register . when the ckio pin goes to th e high-impedance state, it is pulled up.
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 300 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 10.7 overview of watchdog timer 10.7.1 block diagram figure 10.2 shows a block diagram of the wdt. standby release internal reset request interrupt request standby control reset control interrupt control wtcsr wtcnt bus interface clock selection overflow frequency divider clock selector clock wdt le g end: wtcsr: watchdo g timer control/status re g ister wtcnt: watchdo g timer counter standby mode frequency divider 2 1 clock figure 10.2 block diagram of wdt
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 301 of 1076 sep 24, 2013 10.7.2 register configuration the wdt has the two registers summarized in tabl e 10.5. these registers control clock selection and timer mode switching. table 10.5 wdt registers name abbreviation r/w initial value p4 address area 7 address access size watchdog timer counter wtcnt r/w * h'00 h'ffc00008 h'1f c00008 r: 8, w: 16 * watchdog timer control/status register wtcsr r/w * h'00 h'ffc0000c h'1fc0000c r: 8, w: 16 * note: * use word-size access when writing. perform t he write with the upper byte set to h'5a or h'a5, respectively. byte- and longword-size writes cannot be used. use byte access when reading. 10.8 wdt register descriptions 10.8.1 watchdog timer counter (wtcnt) the watchdog timer counter (wtcnt) is an 8-bit re adable/writable counter that counts up on the selected clock. when wtcnt overflows, a reset is generated in watchdog timer mode, or an interrupt in interval timer mode. wtcnt is initialized to h'00 only by a power-on reset via the reset pin. to write to the wtcnt counter, use a word-size access with the upper byte set to h'5a. to read wtcnt, use a byte-size access. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 302 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 10.8.2 watchdog timer control/status register (wtcsr) the watchdog timer control/status register (wtc sr) is an 8-bit readable/writable register containing bits for selecting the count cl ock and timer mode, and overflow flags. wtcsr is initialized to h'00 only by a power-on reset via the reset pin. it retains its value in an internal reset due to wdt overflow. when used to count the clock stabilization time when exiting standby mode, wtcsr retains its value after the counter overflows. to write to the wtcsr register, use a word-size access with the upper byte set to h'a5. to read wtcsr, use a byte-size access. bit: 7 6 5 4 3 2 1 0 tme wt/ it rsts wovf iovf cks2 cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?timer enable (tme): specifies starting and stopping of timer operation. clear this bit to 0 when using the wdt in standby mode or to change a clock frequency. bit 7: tme description 0 up-count stopped, wtcnt value retained (initial value) 1 up-count started bit 6?timer mode select (wt/ it ): specifies whether the wdt is used as a watchdog timer or interval timer. bit 6: wt/ it description 0 interval timer mode (initial value) 1 watchdog timer mode note: the up-count may not be performed correctly if wt/ it is modified while the wdt is running.
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 303 of 1076 sep 24, 2013 bit 5?reset select (rsts): specifies the kind of reset to be performed when wtcnt overflows in watchdog timer mode. this se tting is ignored in in terval timer mode. bit 5: rsts description 0 power-on reset (initial value) 1 manual reset bit 4?watchdog timer overflow flag (wovf): indicates that wtcnt has overflowed in watchdog timer mode. this flag is not set in interval timer mode. bit 4: wovf description 0 no overflow (initial value) 1 wtcnt has overflowed in watchdog timer mode bit 3?interval timer overflow flag (iovf): indicates that wtcnt has overflowed in interval timer mode. this flag is not set in watchdog timer mode. bit 3: iovf description 0 no overflow (initial value) 1 wtcnt has overflowed in interval timer mode
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 304 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 2 to 0?clock select 2 to 0 (cks2?cks0): these bits select the clock used for the wtcnt count from eight clocks obtained by dividing the frequency divider 2 input clock*. the overflow periods shown in the following table are for use of a 33 mhz input clock, with frequency divider 1 off, and pll circuit 1 on ( 6). note: * when pll1 is switched on or off, the clock following the switch is used. description bit 2: cks2 bit 1: cks1 bit 0: cks0 clock division ratio overflow period 0 0 0 1/32 (initial value) 41 s 1 1/64 82 s 1 0 1/128 164 s 1 1/256 328 s 1 0 0 1/512 656 s 1 1/1024 1.31 ms 1 0 1/2048 2.62 ms 1 1/4096 5.25 ms note: the up-count may not be performed correctly if bits cks2?cks0 are modified while the wdt is running. always stop the wdt before modifying these bits.
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 305 of 1076 sep 24, 2013 10.8.3 notes on register access the watchdog timer counter (wtcnt) and watchd og timer control/status register (wtcsr) differ from other registers in being more difficult to write to. the procedure for writing to these registers is given below. writing to wtcnt and wtcsr: these registers mu st be written to with a word transfer instruction. they cannot be written to with a byte or longword transfer instruction. when writing to wtcnt, perform the transfer with the upper byte set to h'5a and the lower byte containing the write data. when writing to wtcsr, perform the tr ansfer with the upper byte set to h'a5 and the lower byte containing the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. the write form ats are shown in figure 10.3. 15 8 7 0 h'5a write data address: h'ffc00008 (h'1fc00008) 15 8 7 0 h'a5 write data address: h'ffc0000c (h'1fc0000c) wtcsr write wtcnt write figure 10.3 writing to wtcnt and wtcsr 10.9 using the wdt 10.9.1 standby clearing procedure the wdt is used when clearing standby mode by means of an nmi or other interrupt. the procedure is shown below. (as the wdt does not operate when standby mode is cleared with a reset, the reset pin should be held low until the clock stabilizes.) 1. be sure to clear the tme bit in the wtcsr register to 0 before making a transition to standby mode. if the tme bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. select the count clock to be used with bits cks2?cks0 in the wtcsr register, and set the initial value in the wtcnt counter. make these settings so that the time until the count overflows is at least as long as the clock oscill ation stabilization time. for details of the clock oscillation stabilization time, see section 22.3.1, clock and control signal timing.
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 306 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3. make a transition to standby mode, and stop the clock, by executing a sleep instruction. 4. the wdt starts counting on detection of an nmi signal transition edge or an interrupt. 5. when the wdt count overflows, the cpg st arts clock supply and the processor resumes operation. the wovf flag in the wtcsr register is not set at this time. 6. the counter stops at a value of h'00?h'01. the value at which the counter stops depends on the clock ratio. 10.9.2 frequency changing procedure the wdt is used in a frequency change using the pll. it is not used when the frequency is changed simply by making a frequency divider switch. 1. be sure to clear the tme bit in the wtcsr register to 0 before making a frequency change. if the tme bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. select the count clock to be used with bits cks2?cks0 in the wtcsr register, and set the initial value in the wtcnt counter. make these settings so that the time until the count overflows is at least as long as the clock oscill ation stabilization time. for details of the clock oscillation stabilization time, see section 22.3.1, clock and control signal timing. 3. when the frequency control register (frqcr) is modified, the clock stops, and the standby state is entered temporarily. the wdt starts counting. 4. when the wdt count overflows, the cpg st arts clock supply and the processor resumes operation. the wovf flag in the wtcsr register is not set at this time. 5. the counter stops at a value of h'00?h'01. the value at which the counter stops depends on the clock ratio. 6. when re-setting wtcnt immediately after modifying the frequency control register (frqcr), first read the counter and confirm that its value is as described in step 5 above. 10.9.3 using watchdog timer mode 1. set the wt/ it bit in the wtcsr register to 1, select the type of reset with the rsts bit, and the count clock with bits cks2?cks0, and set the initial value in the wtcnt counter. 2. when the tme bit in the wtcsr register is set to 1, the count starts in watchdog timer mode. 3. during operation in watchdog timer mode, write h'00 to the counter periodically so that it does not overflow. 4. when the counter overflows, the wdt sets th e wovf flag in the wtcs r register to 1, and generates a reset of the type specified by the rsts bit. the counter then continues counting.
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 307 of 1076 sep 24, 2013 10.9.4 using interval timer mode when the wdt is operating in interval timer mode , an interval timer interrupt is generated each time the counter overflows. this enables interrupts to be generated at fixed intervals. 1. clear the wt/ it bit in the wtcsr register to 0, select the count clock with bits cks2?cks0, and set the initial value in the wtcnt counter. 2. when the tme bit in the wtcsr register is set to 1, the count starts in interval timer mode. 3. when the counter overflows, the wdt sets th e iovf flag in the wtcsr register to 1, and sends an interval timer interrupt request to intc. the counter continues counting. 10.10 notes on board design when using a crystal resonator: place the crystal resonator and capacitors close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins. extal xtal SH7750 SH7750s SH7750r cl1 cl2 r avoid crossin g si g nal lines recommended values cl1 = cl2 = 0?33 pf r = 0 note: the values for cl1, cl2, and the dampin g resistance should be determined after consultation with the crystal resonator manufacturer. figure 10.4 points for attention when using crystal resonator when inputting external clock from extal pin: make no connection to the xtal pin.
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 308 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 when using a pll oscillator circuit: separate vdd-cpg and vss-cpg from the other vdd and vss lines at the board power supply sour ce, and insert resistors rcb and rb and bypass capacitors cpb and cb close to the pins as noise filters. vdd-pll1 cpb1 cpb2 cb rcb1 recommended values rcb1 = rcb2 = 10 cpb1 = cpb2 = 10 f rb = 10 cb = 10 f rcb2 rb 3.3 v vss-pll1 vdd-pll2 SH7750 SH7750s SH7750r vss-pll2 vdd-cpg vss-cpg figure 10.5 points for attentio n when using pll oscillator circuit
SH7750, SH7750s, SH7750r group section 10 clock oscillation circuits r01uh0456ej0702 rev. 7.02 page 309 of 1076 sep 24, 2013 10.11 usage notes 10.11.1 invalid manual reset triggered by watchdog timer (SH7750 and SH7750s) under certain conditions the watchdog timer (wdt) may trigger an invalid manual reset. conditions under which problem occurs: the internal wdt triggers an invalid manual reset when all of the following four conditions are satisfied. 1. after the wdt overflows, regardless of the values of the wt/ it and rsts bits in wtcsr. 2. before the counter (wtcnt) is incremented by the clock specified by the wtcsr.cks bit. 3. the value of at least one of the tme, wt/ it , and rsts bits in wtcsr is 0. 4. a value of 1 is written to the tme, wt/ it , and rsts bits in wtcsr. workaround: a workaround for this problem is to use software to increment wtcnt before writing 1 to the tme, wt/ it , and rsts bits in wtcsr. specifi c lines of code for this purpose are listed below. example: add the following lines of code before the instructions for writing 1 to the tme, wt/ it , and rsts bits in wtcsr. mov.l #wtcnt,r7 mov.w #h'5a00,r8 mov.w r8,@r7 mov.l #wtcsr,r9 mov.w #h'a580,r10 mov.w r10,@r9 loop_wdt: mov.b @r7,r0 cmp/eq #h'00, r0 bt loop_wdt
section 10 clock oscillation circuits SH7750, SH7750s, SH7750r group page 310 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 311 of 1076 sep 24, 2013 section 11 realtime clock (rtc) 11.1 overview this lsi includes an on-chip realtime clock (rtc) and a 32.768 khz crystal oscillation circuit for use by the rtc. 11.1.1 features the rtc has the following features. ? clock and calendar functions (bcd display) counts seconds, minutes, hours, day- of-week, days, months, and years. ? 1 to 64 hz timer (binary display) the 64 hz counter register indicat es a state of 64 hz to 1 hz within the rtc frequency divider ? start/stop function ? 30-second adjustment function ? alarm interrupts comparison with second, minute, hour, day-of-week, day, month, or year (year is available only with the SH7750r) can be select ed as the alarm interrupt condition ? periodic interrupts an interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds can be selected ? carry interrupt carry interrupt function indicating a second counter carry, or a 64 hz counter carry when the 64 hz counter is read ? automatic leap year adjustment
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 312 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 11.1.2 block diagram figure 11.1 shows a block diagram of the rtc. r64cnt rtcclk 16.384 khz 32.768 khz 128 hz at i pri cui rcr1 rcr2 rcr3 * ryrcnt rmoncnt rwkcnt rdaycnt rhrcnt rmincnt rseccnt rsecar rminar rhrar rdayar rwkar rmonar prescaler rtc crystal oscillation circuit rtc operation control unit reset, stby, etc counter unit interrupt control unit to registers bus interface ryrar * internal peripheral module bus note: * SH7750r only figure 11.1 block diagram of rtc
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 313 of 1076 sep 24, 2013 11.1.3 pin configuration table 11.1 shows the rtc pins. table 11.1 rtc pins pin name abbreviation i/o function rtc oscillation circuit crystal pin extal2 i nput connects crystal to rtc oscillation circuit rtc oscillation circuit crystal pin xtal2 ou tput connects crystal to rtc oscillation circuit clock input/clock output tclk i/o exter nal clock input pin/input capture control input pin/rt c output pin (shared with tmu) dedicated rtc power supply v dd-rtc ? rtc oscillation circuit power supply pin * dedicated rtc gnd pin v ss-rtc ? rtc oscillation circuit gnd pin * note: * power must be supplied to the rtc power supply pins even when the rtc is not used. 11.1.4 register configuration table 11.2 summarizes the rtc registers. table 11.2 rtc registers initialization name abbrevia- tion r/w power- on reset manual reset standby mode initial value p4 address area 7 address access size 64 hz counter r64cnt r counts counts counts undefined h'ffc80000 h'1fc80000 8 second counter rseccnt r/w counts counts counts undefined h'ffc80004 h'1fc80004 8 minute counter rmincnt r/w counts c ounts counts undefined h'ffc80008 h'1fc80008 8 hour counter rhrcnt r/w counts counts counts undefined h'ffc 8000c h'1fc 8000c 8 day-of- week counter rwkcnt r/w counts counts counts undefined h'ffc80010 h'1fc80010 8 day counter rdaycnt r/w counts counts counts undefined h'ffc80014 h'1fc80014 8
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 314 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 initialization name abbrevia- tion r/w power-on reset manual reset standby mode initial value p4 address area 7 address access size month counter rmoncnt r/w counts coun ts counts u ndefined h'ffc80018 h' 1fc80018 8 year counter ryrcnt r/w counts counts counts undefined h'ffc8001c h'1fc8001c 16 second alarm register rsecar r/w initialized * 1 held held undefined * 1 h'ffc80020 h'1fc80020 8 minute alarm register rminar r/w initialized * 1 held held undefined * 1 h'ffc80024 h'1fc80024 8 hour alarm register rhrar r/w initialized * 1 held held undefined * 1 h'ffc80028 h'1fc80028 8 day-of- week alarm register rwkar r/w initialized * 1 held held undefined * 1 h'ffc8002c h'1fc8002c 8 day alarm register rdayar r/w initialized * 1 held held undefined * 1 h'ffc80030 h'1fc80030 8 month alarm register rmonar r/w initialized * 1 held held undefined * 1 h'ffc80034 h'1fc80034 8 rtc control register 1 rcr1 r/w initialized initialized held h'00 * 3 h'ffc80038 h'1fc80038 8 rtc control register 2 rcr2 r/w initialized initialized * 2 held h'09 * 4 h'ffc8003c h'1fc8003c 8 rtc control register 3 * 5 rcr3 r/w initialized held he ld h'00 h'ffc80050 h'1fc80050 8 year alarm register * 5 ryrar r/w held held held undefined h'ffc80054 h'1fc80054 16 notes: 1. the enb bit in eac h register is initialized. 2. bits other than the rtcen bit and start bit are initialized. 3. the value of the cf bit and af bit is undefined. 4. the value of t he pef bit is undefined. 5. SH7750r only
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 315 of 1076 sep 24, 2013 11.2 register descriptions 11.2.1 64 hz counter (r64cnt) r64cnt is an 8-bit read-only register that indi cates a state of 64 hz to 1 hz within the rtc frequency divider. if this register is read when a carry is generated from the 128 khz frequency division stage, bit 7 (cf) in rtc control register 1 (rcr1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 hz counte r read. in this case, the read value is not valid, and so r64cnt must be read again after first writing 0 to the cf bit in rcr1 to clear it. when the reset bit or adj bit in rtc control re gister 2 (rcr2) is set to 1, the rtc frequency divider is initialized and r64cnt is initialized to h'00. r64cnt is not initialized by a power-on or manual reset, or in standby mode. bit 7 is always read as 0 and cannot be modified. bit: 7 6 5 4 3 2 1 0 ? 1 hz 2 hz 4 hz 8 hz 16 hz 32 hz 64 hz initial value: 0 undefined undefined undefined undef ined undefined undefined undefined r/w: r r r r r r r r
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 316 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 11.2.2 second counter (rseccnt) rseccnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded second value in the rtc. it counts on the carry (transition of the r64cnt.1hz bit from 0 to 1) generated once per second by the 64 hz counter. the setting range is decimal 00 to 59. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rseccnt is not initialized by a power-on or manual reset, or in standby mode. bit 7 is always read as 0. a write to this bit is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? 10-second units 1-second units initial value: 0 undefined undefined undefined undef ined undefined undefined undefined r/w: r r/w r/w r/w r/w r/w r/w r/w 11.2.3 minute counter (rmincnt) rmincnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded minute value in the rtc. it counts on the carry generated once per minute by the second counter. the setting range is decimal 00 to 59. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rmincnt is not initialized by a power-on or manual reset, or in standby mode. bit 7 is always read as 0. a write to this bit is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? 10-minute units 1-minute units initial value: 0 undefined undefined undefined undef ined undefined undefined undefined r/w: r r/w r/w r/w r/w r/w r/w r/w
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 317 of 1076 sep 24, 2013 11.2.4 hour counter (rhrcnt) rhrcnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded hour value in the rtc. it counts on the carry generated once per hour by the minute counter. the setting range is decimal 00 to 23. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rhrcnt is not initialized by a power-on or manual reset, or in standby mode. bits 7 and 6 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? ? 10-hour units 1-hour units initial value: 0 0 undefined undefined undefined undefined undefined undefined r/w: r r r/w r/w r/w r/w r/w r/w 11.2.5 day-of-week coun ter (rwkcnt) rwkcnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded day-of-week value in the rtc. it counts on the carry generated once per day by the hour counter. the setting range is decimal 0 to 6. the rtc will no t operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rwkcnt is not initialized by a power-on or manual reset, or in standby mode. bits 7 to 3 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? day of week code initial value: 0 0 0 0 0 undefined undefined undefined r/w: r r r r r r/w r/w r/w
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 318 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 day-of-week code 0 1 2 3 4 5 6 day of week sun mon tue wed thu fri sat 11.2.6 day counter (rdaycnt) rdaycnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded day value in the rtc. it counts on the carry generated once per day by the hour counter. the setting range is decimal 01 to 31. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rdaycnt is not initialized by a power-on or manual reset, or in standby mode. the setting range for rdaycnt depends on the month and whether the year is a leap year, so care is required when making th e setting. taking the year counter (ryrcnt) value as the year, leap year calculation is performed according to whether or not the value is divisible by 400, 100, and 4. bits 7 and 6 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? ? 10-day units 1-day units initial value: 0 0 undefined undefined undefined undefined undefined undefined r/w: r r r/w r/w r/w r/w r/w r/w 11.2.7 month counter (rmoncnt) rmoncnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded month value in the rtc. it counts on the carry generated once per month by the day counter. the setting range is decimal 01 to 12. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rmoncnt is not initialized by a power-on or manual reset, or in standby mode.
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 319 of 1076 sep 24, 2013 bits 7 to 5 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 ? ? ? 10-month unit 1-month units initial value: 0 0 0 undefined undefined undefined undefined undefined r/w: r r r r/w r/w r/w r/w r/w 11.2.8 year counter (ryrcnt) ryrcnt is a 16-bit readable/writable register us ed as a counter for setting and counting the bcd-coded year value in the rtc. it counts on the carry generated once per year by the month counter. the setting range is decimal 0000 to 9999. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. ryrcnt is not initialized by a power-on or manual reset, or in standby mode. bit: 15 14 13 12 11 10 9 8 1000-year units 100-year units initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 10-year units 1-year units initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 320 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 11.2.9 second alarm register (rsecar) rsecar is an 8-bit readable/writable register us ed as an alarm register for the rtc's bcd-coded second value counter, rseccnt. when the enb bi t is set to 1, the rsecar value is compared with the rseccnt value. comparison between th e counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the resp ective values all match. the setting range is decimal 00 to 59 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rsecar is initialized to 0 by a power-on reset. the other fields in rsecar are not initialized by a power-on or ma nual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 enb 10-second units 1-second units initial value: 0 undefined undefined undefined undef ined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w 11.2.10 minute alarm register (rminar) rminar is an 8-bit readable/writable register us ed as an alarm register for the rtc's bcd-coded minute value counter, rmincnt. when the enb bit is set to 1, the rminar value is compared with the rmincnt value. comparison between the counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the resp ective values all match. the setting range is decimal 00 to 59 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rminar is initialized by a power-on reset. the other fields in rminar are not initialized by a power-on or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 enb 10-minute units 1-minute units initial value: 0 undefined undefined undefined undef ined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 321 of 1076 sep 24, 2013 11.2.11 hour alarm register (rhrar) rhrar is an 8-bit readable/writable register used as an alarm register for the rtc's bcd-coded hour value counter, rhrcnt. when the enb bit is set to 1, the rhrar value is compared with the rhrcnt value. comparison between the coun ter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the respective values all match. the setting range is decimal 00 to 23 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rhrar is initialized by a power-on reset. the other fields in rhrar are not initialized by a power-on or manual reset, or in standby mode. bit 6 is always read as 0. a write to this bit is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 enb ? 10-hour units 1-hour units initial value: 0 0 undefined undefined undefined undefined undefined undefined r/w: r/w r r/w r/w r/w r/w r/w r/w 11.2.12 day-of-week alarm register (rwkar) rwkar is an 8-bit readable/writable register used as an alarm register for the rtc's bcd-coded day-of-week value counter, rwkcnt. when the enb bit is set to 1, the rwkar value is compared with the rwkcnt value. comparison between the counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 0 to 6 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rwkar is initialized by a power-on reset. the other fields in rwkar are not initialized by a power-on or manual reset, or in standby mode. bits 6 to 3 are always read as 0. a write to these bits is invalid, but the write value should always be 0.
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 322 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit: 7 6 5 4 3 2 1 0 enb ? ? ? ? day of week code initial value: 0 0 0 0 0 undefined undefined undefined r/w: r/w r r r r r/w r/w r/w day-of-week code 0 1 2 3 4 5 6 day of week sun mon tue wed thu fri sat 11.2.13 day alarm register (rdayar) rdayar is an 8-bit readable/writable register used as an alarm regi ster for the rtc's bcd- coded day value counter, rdaycnt. when the enb bit is set to 1, the rdayar value is compared with the rday cnt value. comparison between the counter and the alarm register is performed for those registers among rsec ar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 01 to 31 + enb bit. the rtc will not operate normally if any other value is set. the setting range for rdayar depends on the month and whether the year is a leap year, so care is required when making the setting. the enb bit in rdayar is initialized by a power-on reset. the other fields in rdayar are not initialized by a power-on or manual reset, or in standby mode. bit 6 is always read as 0. a write to this bit is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 enb ? 10-day units 1-day units initial value: 0 0 undefined undefined undefined undefined undefined undefined r/w: r/w r r/w r/w r/w r/w r/w r/w
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 323 of 1076 sep 24, 2013 11.2.14 month alarm register (rmonar) rmonar is an 8-bit readable/writable register used as an alarm regi ster for the rtc's bcd- coded month value counter, rmoncnt. when the enb bit is set to 1, the rmonar value is compared with the rmon cnt value. comparison between the counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 01 to 12 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rmonar is initialized by a power-on reset. the other fields in rmonar are not initialized by a power-on or ma nual reset, or in standby mode. bits 6 and 5 are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit: 7 6 5 4 3 2 1 0 enb ? ? 10-month unit 1-month units initial value: 0 0 0 undefined undefined undefined undefined undefined r/w: r/w r r r/w r/w r/w r/w r/w 11.2.15 rtc control register 1 (rcr1) rcr1 is an 8-bit readable/writable register contai ning a carry flag and alarm flag, plus flags to enable or disable interrupts for these flags. the cie and aie bits are initialized to 0 by a power-on or manual reset; the value of bits other than cie and aie is undefined. in standby mode rcr1 is not initialized, and retains its current value. bit: 7 6 5 4 3 2 1 0 cf ? ? cie aie ? ? af initial value: undefined undefined undefined 0 0 undefined undefined undefined r/w: r/w r r r/w r/w r r r/w
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 324 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 7?carry flag (cf): this flag is set to 1 on generation of a second counter carry, or a 64 hz counter carry when the 64 hz counter is read. the count register value read at this time is not guaranteed, and so the count regi ster must be read again. bit 7: cf description 0 no second counter carry, or 64 hz counter carry when 64 hz counter is read [clearing condition] when 0 is written to cf 1 second counter carry, or 64 hz counter carry when 64 hz counter is read [setting conditions] ? generation of a second counter carry, or a 64 hz counter carry when the 64 hz counter is read ? when 1 is written to cf bit 4?carry interrupt enable flag (cie): enables or disables interrupt generation when the carry flag (cf) is set to 1. bit 4: cie description 0 carry interrupt is not generated when cf flag is set to 1 (initial value) 1 carry interrupt is generated when cf flag is set to 1 bit 3?alarm interrupt enable flag (aie): enables or disables interrupt generation when the alarm flag (af) is set to 1. bit 3: aie description 0 alarm interrupt is not generated when af flag is set to 1 (initial value) 1 alarm interrupt is generated when af flag is set to 1
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 325 of 1076 sep 24, 2013 bit 0?alarm flag (af): set to 1 when the alarm time set in those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1 matches the respective counter values. bit 0: af description 0 alarm registers and counter values do not match (initial value) [clearing condition] when 0 is written to af 1 alarm registers and counter values match * [setting condition] when alarm registers in which the enb bit is set to 1 and counter values match * note: * writing 1 does not change the value. bits 6, 5, 2, and 1?reserved. the initial value of these bits is undefined. a write to these bits is invalid, but the write value should always be 0. 11.2.16 rtc control register 2 (rcr2) rcr2 is an 8-bit readable/writable register us ed for periodic interrupt control, 30-second adjustment, and frequency divider reset and rtc count control. rcr2 is basically initialized to h'09 by a power-on reset, except that the value of the pef bit is undefined. in a manual reset, bits other than rtcen and start are initialized, while the value of the pef bit is undefined. in standby mode rcr2 is not initialized, and retains its current value. bit: 7 6 5 4 3 2 1 0 pef pes2 pes1 pes0 rtcen adj reset start initial value: undefined 0 0 0 1 0 0 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 326 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 7?periodic interrupt flag (pef): indicates interrupt generation at the interval specified by bits pes2?pes0. when this flag is set to 1, a periodic interrupt is generated. bit 7: pef description 0 interrupt is not gener ated at interval specified by bits pes2?pes0 [clearing condition] when 0 is written to pef 1 interrupt is generated at interv al specified by bits pes2?pes0 [setting conditions] ? generation of interrupt at interv al specified by bits pes2?pes0 ? when 1 is written to pef bits 6 to 4?periodic int errupt enable (pes2?pes0): these bits specify the period for periodic interrupts. bit 6: pes2 bit 5: pes1 bit 4: pes0 description 0 0 0 no periodic interrupt generation (initial value) 1 periodic interrupt generated at 1/256-second intervals 1 0 periodic interrupt generated at 1/64-second intervals 1 periodic interrupt generated at 1/16-second intervals 1 0 0 periodic interrupt generated at 1/4-second intervals 1 periodic interrupt generated at 1/2-second intervals 1 0 periodic interrupt generated at 1-second intervals 1 periodic interrupt generated at 2-second intervals bit 3? oscillation circuit enable (rtcen): controls the operation of the rtc crystal oscillation circuit. bit 3: rtcen description 0 rtc crystal oscillation circuit halted 1 rtc crystal oscillation circuit operating (initial value)
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 327 of 1076 sep 24, 2013 bit 2?30-second adjustment (adj): used for 30-second adjustment. when 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. the frequency divider circuits (rtc prescaler and r64cnt) are also reset at this time. this bit always returns 0 if read. bit 2: adj description 0 normal clock operation (initial value) 1 30-second adjustment performed bit 1?reset (reset): the frequency divider circuits are initialized by writing 1 to this bit. when 1 is written to the reset bit, the frequency divider circuits (rtc prescaler and r64cnt) are reset and the reset bit is auto matically cleared to 0 (i.e. does not need to be written with 0). bit 1: reset description 0 normal clock operation (initial value) 1 frequency divider circuits are reset bit 0?start bit (start): stops and restarts coun ter (clock) operation. bit 0: start description 0 second, minute, hour, day, day-of-w eek, month, and year counters are stopped * 1 second, minute, hour, day, day-of-week , month, and year counters operate normally * (initial value) note: * the 64 hz counter continues to operate unless stopped by means of the rtcen bit. 11.2.17 rtc control register 3 (rcr3) and year-alarm register (ryrar) (SH7750r only) rcr3 and ryrar are readab le/writable registers. ryrar is the alarm register for the rtc's bcd-coded year-value counter ryrcnt. when the yenb bit of rcr3 is set to 1, the ryrcnt value is compared with the ryra r value. comparison between the counter and the alarm register only takes place with the alarm registers in which the enb and yenb bits are set to 1. the alarm flag of rcr1 is only set to 1 when the respective values all match. the setting range of ryrar is decimal 0000 to 999 9, and normal operation is not obtained if a value beyond this range is set here.
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 328 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 rcr3 is initialized by a power-on reset, but ryra r will not be initialized by a power-on or manual reset, or by the device entering standby mode. bits 6 to 0 of rcr3 are always read as 0. writing to these bits is invalid. if a value is written to these bits, it should always be 0. rcr3 bit: 7 6 5 4 3 2 1 0 yenb ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r r r r ryrar bit: 15 14 13 12 11 10 9 8 1000 years 100 years initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 10 years 1 year initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w: r/w r/w r/w r/w r/w r/w r/w r/w
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 329 of 1076 sep 24, 2013 11.3 operation examples of the use of the rtc are shown below. 11.3.1 time setting procedures figure 11.2 shows examples of the time setting procedures. stop clock reset frequency divider set second/minute/hour/day/ day-of-week/month/year start clock operation set rcr2.reset to 1 clear rcr2.start to 0 in any order set rcr2.start to 1 (a) settin g time after stoppin g clock clear carry fla g write to counter re g ister carry fla g = 1? no ye s clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm fla g is not cleared) set ryrcnt first and rseccnt last read rcr1 re g ister and check cf bit (b) settin g time while clock is runnin g figure 11.2 examples of time setting procedures the procedure for setting the time after stopping the clock is shown in (a). the programming for this method is simple, and it is useful for setting all the counters, from second to year.
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 330 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 the procedure for setting the time while the clock is running is shown in (b). this method is useful for modifying only certain counter values (for example, only the second data or hour data). if a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data. the carry flag should th erefore be used to check the write status. if the carry flag (rcr1.cf) is set to 1, the write must be repeated. the interrupt function can also be used to determine the carry flag status. 11.3.2 time reading procedures figure 11.3 shows examples of the time reading procedures.
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 331 of 1076 sep 24, 2013 disable carry interrupts clear carry fla g read counter re g ister carry fla g = 1? clear rcr1.cie to 0 clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm fla g is not cleared) read rcr1 re g ister and check cf bit (a) readin g time without usin g interrupts no ye s clear carry fla g enable carry interrupts clear carry fla g read counter re g ister interrupt g enerated? ye s disable carry interrupts no (b) readin g time usin g interrupts set rcr1.cie to 1 clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm fla g is not cleared) clear rcr1.cie to 0 figure 11.3 examples of time reading procedures if a carry occurs while the time is being read, the correct time will not be obtained and the read must be repeated. the procedure for reading the time without using interrupts is shown in (a), and the procedure using carry interrupts in (b). the method without using interrupts is normally used to keep the program simple.
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 332 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 11.3.3 alarm function the use of the alarm function is illustrated in figure 11.4. clock runnin g disable alarm interrupts set alarm time clear alarm fla g enable alarm interrupts monitor alarm time (wait for interrupt or check alarm fla g ) clear rcr1.aie to prevent erroneous interrupts be sure to reset the fla g as it may have been set durin g alarm time settin g set rcr1.aie to 1 figure 11.4 example of use of alarm function an alarm can be generated by the second, minute, hour, day-of-week, day, month, or year (year is available only with the SH7750r) value, or a combination of these. write 1 to the enb bit in the alarm registers involved in the al arm setting, and set the alarm time in the lower bits. write 0 to the enb bit in registers not involved in the alarm setting. when the counter and the alarm time match, rcr1.af is set to 1. alarm detection can be confirmed by reading this bit, but normally an interrupt is used. if 1 has been written to rcr1.aie, an alarm interrupt is generated in th e event of alarm, enabling the alarm to be detected. the alarm flag remains set while the counter and al arm time match. if the alarm flag is cleared by writing 0 during this period, it will therefore be set again immediately afterward. this needs to be taken into consideration when writing the program.
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 333 of 1076 sep 24, 2013 11.4 interrupts there are three kinds of rtc interrupt: alarm interr upts, periodic interrupts, and carry interrupts. an alarm interrupt request (ati) is generated when the alarm flag (af) in rcr1 is set to 1 while the alarm interrupt enable bit (aie) is also set to 1. a periodic interrupt request (pri) is generated when the periodic interrupt enable bits (pes2? pes0) in rcr2 are set to a value other than 000 and the periodic interrupt flag (pef) is set to 1. a carry interrupt request (cui) is generated when the carry flag (cf) in rcr1 is set to 1 while the carry interrupt enable bit (cie) is also set to 1. 11.5 usage notes 11.5.1 register initialization after powering on and making the rcr1 register settings, reset the frequency divider (by setting rcr2.reset to 1) and make initial se ttings for all the other registers. 11.5.2 carry flag and interrupt flag in standby mode when the carry flag or interrupt fl ag is set to 1 at the same time this lsi transits to normal mode from standby mode by a reset or interrupt, the flag may not be set to 1. after exiting standby mode, check the counters to judge the flag states if necessary. 11.5.3 crystal oscillator circuit crystal oscillator circuit constants (recommended values) are shown in table 11.3, and the rtc crystal oscillator circuit in figure 11.5. table 11.3 crystal oscillator circuit constants (recommended values) f osc c in c out 32.768 khz 10?22 pf 10?22 pf
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 334 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 SH7750 SH7750s SH7750r extal2 xtal2 xtal c in c out r f r d noise filter c rtc r rtc 3.3 v vdd-rtc vss-rtc notes: 1. select either the c in or c out side for the frequency adjustment variable capacitor accordin g to requirements such as the adjustment ran g e, de g ree of stability, etc. 2. built-in resistance value r f (typ. value) = 10 m , r d (typ. value) = 400 k 3. c in and c out values include floatin g capacitance due to the wirin g . take care when usin g a solid- earth board. 4. the crystal oscillation stabilization time depends on the mounted circuit constants, floatin g capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors c in and c out as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal2 and xtal2 pins.) 6. ensure that the crystal resonator connection pin (extal2 and xtal2) wirin g is routed as far away as possible from other power lines (except gnd) and si g nal lines. 7. insert a noise filter in the rtc power supply. figure 11.5 example of crys tal oscillator ci rcuit connection 11.5.4 rtc register settings (SH7750 only) description: when setting values are written to an rtc re gister, values may change in writable rtc counter registers other than that to which the settings are written. the rtc registers are r64cnt, rseccnt, rmincnt, rhrcnt, rwkcnt, rdaycnt, rmoncnt, ryrcnt, rsecar, rminar, rhrar, rdayar, rwkar, rmonar, rcr1, and rcr2. of these, rseccnt, rmincnt, rhrcnt, rwkcnt, rdaycnt, rmoncnt, and ryrcnt are writ eable registers. workarounds: to avoid the problem, use one of methods 1. to 3. below to write settings to the rtc registers. 1. disable the dmac channels used to access pe ripheral registers before writing to an rtc register, and write to the rtc register while th e exception/interrupt block bit (sr.bl) in the status register is set to 1. then use the next instruction to read from the same register.
SH7750, SH7750s, SH7750r group section 11 realtime clock (rtc) r01uh0456ej0702 rev. 7.02 page 335 of 1076 sep 24, 2013 2. use the following method to write to an rtc register. read all writeable counter re g isters (1) write to the re g ister whose value is to be chan g ed read all writeable counter re g isters (2) compare the values of (1) and (2) are the compared values valid? no write operation complete ye s
section 11 realtime clock (rtc) SH7750, SH7750s, SH7750r group page 336 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3. use the following method to write to an rtc register. read all writeable counter re g isters (1) write 0 to rcr2.rtcen read all writeable counter re g isters (2) compare the values of (1) and (2) no write to the re g ister whose value is to be chan g ed ye s write 1 to rcr2.rtcen write operation complete write the valid value are the compared values valid? note: the operation of the rtc counter is stopped when rcr2.rtcen is cleared to 0. therefore, usin g the above method will cause the rtc counter value to fall behind the actual time by the amount of time that rcr2.rtcen was cleared to 0, and the cycle duration for cycle interrupt g eneration will be len g thened as well.
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 337 of 1076 sep 24, 2013 section 12 timer unit (tmu) 12.1 overview this lsi of microprocessors includes an on-chip 32-bit timer unit (tmu). the tmu of the SH7750 or SH7750s has three 32-bit timer channels (channels 0 to 2), and the tmu of the SH7750r has five channels (channels 0 to 4). 12.1.1 features the tmu has the following features. ? auto-reload type 32-bit down-coun ter provided for each channel ? input capture function provided in channel 2 ? selection of rising edge or falling edge as external clock input edge when external clock is selected or input capture function is used ? 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit down-counter provided for each channel ? for channels 0 to 2, selection of seven counter input clocks for each channel external clock (tclk), on-chip rtc output clock, five internal clocks (pck/4, pck/16, pck/64, pck/256, pck/1024) (pck is the peripheral module clock) ? for channels 3 and 4, selection is made among five internal clocks (SH7750r only). ? channels 0 to 2 can also operate in module standby mode when the on-chip rtc output clock is selected as the counter input clock; that is , timer operation continue s even when the clock has been stopped for the tmu. timer count operations using an external or internal clock are only possible when a clock is supplied to the timer unit. ? two interrupt sources one underflow source (each channel) and one input capture source (channel 2) ? dmac data transfer request capability on channel 2, a data transfer request is sent to the dmac when an input capture interrupt is generated.
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 338 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 12.1.2 block diagram figure 12.1 shows a block diagram of the tmu. reset, stby, etc. tune0,tune1 pck/4,16, 64 * 1 tuni2 icpi2 tclk rtcclk tuni3, 4 * 2 tmu control unit prescaler to each channel to channels 0 to 2 tclk control unit tocr tstr tstr2 * 2 interrupt contrun unit counter unit interrupt contrun unit counter unit interrupt contrun unit counter unit ch 0, 1 ch 2 ch 3, 4 * 2 bus interface internal peripheral module bus tcr tcor tcnt tcr tcor tcnt tcr2 tcor2 tcnt2 tcpr2 notes: 1. signals with 1/4, 1/16, and 1/64 the pck frequency, supplied to the on-chip peripheral functions. 2. SH7750r only figure 12.1 block diagram of tmu 12.1.3 pin configuration table 12.1 shows the tmu pins. table 12.1 tmu pins pin name abbreviation i/o function clock input/clock output tclk i/o exter nal clock input pin/input capture control input pin/rtc output pin (shared with rtc)
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 339 of 1076 sep 24, 2013 12.1.4 register configuration table 12.2 summarizes the tmu registers. table 12.2 tmu registers initialization chan- nel name abbre- viation r/w power- on reset manual reset stand- by mode initial value p4 address area 7 address access size com- mon timer output control register tocr r/w ini- tialized ini- tialized held h'00 h'ffd80000 h'1fd80000 8 timer start register tstr r/w ini- tialized ini- tialized ini- tialized * 1 h'00 h'ffd80004 h'1fd80004 8 timer start register 2 tstr2 * 3 r/w ini- tialized held held h'00 h'fe100004 h'1e100004 8 0 timer constant register 0 tcor0 r/w ini- tialized ini- tialized held h'ffffffff h'ffd80008 h'1fd80008 32 timer counter 0 tcnt0 r/w ini- tialized ini- tialized held * 2 h'ffffffff h'ffd8000c h'1fd8000c 32 timer control register 0 tcr0 r/w ini- tialized ini- tialized held h'0000 h'ffd80010 h'1fd80010 16 1 timer constant register 1 tcor1 r/w ini- tialized ini- tialized held h'ffffffff h'ffd80014 h'1fd80014 32 timer counter 1 tcnt1 r/w ini- tialized ini- tialized held * 2 h'ffffffff h'ffd80018 h'1fd80018 32 timer control register 1 tcr1 r/w ini- tialized ini- tialized held h'0000 h'ffd8001c h'1fd8001c 16
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 340 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 initialization chan- nel name abbre- viation r/w power- on reset manual reset stand- by mode initial value p4 address area 7 address access size 2 timer constant register 2 tcor2 r/w ini- tialized ini- tialized held h'ffffffff h'ffd80020 h'1fd80020 32 timer counter 2 tcnt2 r/w ini- tialized ini- tialized held * 2 h'ffffffff h'ffd80024 h'1fd80024 32 timer control register 2 tcr2 r/w ini- tialized ini- tialized held h'0000 h'ffd80028 h'1fd80028 16 input capture register tcpr2 r held held held undefined h'ffd8002c h'1fd8002c 32 3 * 3 timer constant register 3 tcor3 r/w ini- tialized held held h'ffffffff h'fe100008 h'1e100008 32 timer counter 3 tcnt3 r/w ini- tialized held held h'ffffffff h'fe10000c h'1e10000c 32 timer control register 3 tcr3 r/w ini- tialized held held h'0000 h'fe100010 h'1e100010 16 4 * 3 timer constant register 4 tcor4 r/w ini- tialized held held h'ffffffff h'fe100014 h'1e100014 32 timer counter 4 tcnt4 r/w ini- tialized held held h'ffffffff h'fe100018 h'1e100018 32 timer control register 4 tcr4 r/w ini- tialized held held h'0000 h'fe10001c h'1e10001c 16 notes: 1. not initialized in module standby mode when the input clock is the on-chip rtc output clock. 2. counts in module standby mode when the in put clock is the on-chip rtc output clock. 3. h7750r only
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 341 of 1076 sep 24, 2013 12.2 register descriptions 12.2.1 timer output control register (tocr) tocr is an 8-bit readable/writable register that specifies whether external pin tclk is used as the external clock or input capture control input pin, or as the on-chip rtc output clock output pin. tocr is initialized to h'00 by a power-on or manual reset, but is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? tcoe initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bits 7 to 1?reserved: these bits are always read as 0. a wr ite to these bits is invalid, but the write value should always be 0. bit 0?timer clock pin control (tcoe): specifies whether timer cloc k pin tclk is used as the external clock or input capture control input pin, or as the on-chip rtc output clock output pin. bit 0: tcoe description 0 timer clock pin (tclk) is used as external clock input or input capture control input pin (initial value) 1 timer clock pin (tclk) is used as on-chip rtc output clock output pin * note: * low level output in standby mode.
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 342 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 12.2.2 timer start register (tstr) tstr is an 8-bit readable/writable register that specifies whether the channel 0?2 timer counters (tcnt) are operated or stopped. tstr is initialized to h'00 by a power-on or manual reset, or standby mode. in module standby mode, tstr is not initialized when the input cl ock selected by each channel is the on-chip rtc output clock (rtcclk), and is initialized only when the input clock is the external clock (tclk) or internal clock (pck). bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? str2 str1 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bits 7 to 3?reserved : these bits are always read as 0. a wr ite to these bits is invalid, but the write value should always be 0. bit 2?counter start 2 (str2): specifies whether timer counter 2 (tcnt2) is operated or stopped. bit 2: str2 description 0 tcnt2 count operation is stopped (initial value) 1 tcnt2 performs count operation bit 1?counter start 1 (str1): specifies whether timer counter 1 (tcnt1) is operated or stopped. bit 1: str1 description 0 tcnt1 count operation is stopped (initial value) 1 tcnt1 performs count operation bit 0?counter start 0 (str0): specifies whether timer counter 0 (tcnt0) is operated or stopped. bit 0: str0 description 0 tcnt0 count operation is stopped (initial value) 1 tcnt0 performs count operation
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 343 of 1076 sep 24, 2013 12.2.3 timer start register 2 (tstr2) (SH7750r only) tstr2 is an 8-bit readable/writable regist er that specifies whether the channels 3 ? 4 timer counters (tstr2) run or are stopped. tstr2 is initialized to h'00 by a power-on reset and retains its value in standby mode. if standby mode is entered when the str3 or str4 bit is set to 1, counting is halted at the same time as the peripheral module clock is stopped. counting is restarted on resumption of the clock-signal supply. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? str4 str3 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bits 7 to 2?reserved: these bits are always read as 0. wri ting to these bits is invalid. if a value is written to these bits, it should always be 0. bit 1?counter start 4 (str4): specifies whether timer counter 4 (tcnt4) runs or is stopped. bit 1: str4 description 0 counting by tcnt4 is stopped (initial value) 1 counting by tcnt4 proceeds bit 0?counter start 3 (str3): specifies whether timer counter 3 (tcnt3) runs or is stopped. bit 0: str3 description 0 counting by tcnt3 is stopped (initial value) 1 counting by tcnt3 proceeds
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 344 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 12.2.4 timer constant registers (tcor) the tcor registers are 32-bit r eadable/writable registers. there are tcor registers, one for each channel. when a tcnt counter underflows while counting down, the tcor value is set in that tcnt, which continues counting down from the set value. the tcor registers for channels 0 to 2 are in itialized to h'ffffffff by a power-on or manual reset, but are not initialized and retain their contents in standby mode. the tcor registers for channels 3 and 4 of the SH7750r are initialized to h'ffffffff by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode. bit: 31 30 29 2 1 0 initial value: 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w 12.2.5 timer counters (tcnt) the tcnt registers are 32-bit r eadable/writable registers. there are tcnt registers, one for each channel. each tcnt counts down on the input clock sel ected by tpsc2?tpsc0 in the timer control register (tcr). when a tcnt counter underflows while counting down, the underflow flag (unf) is set in the corresponding timer contro l register (tcr). at the same time, the timer constant register (tcor) value is set in tcnt, and the count-down operation continues from the set value.
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 345 of 1076 sep 24, 2013 the tcnt registers for channels 0 to 2 are init ialized to h'ffffffff by a power-on or manual reset, but are not initialized and retain their c ontents in standby mode. the tcnt registers for channels 3 and 4 of the SH7750r are initialized to h'ffffffff by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode. bit: 31 30 29 2 1 0 initial value: 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w when the input clock is the on-chip rtc output clock (rtcclk) in channels 0 to 2, tcnt counts even in module standby mode (that is, when the clock for the tmu is stopped). when the input clock is the external clock (tclk) or intern al clock (pck), tcnt contents are retained in standby mode. 12.2.6 timer control registers (tcr) the tcr registers are 16-bit readab le/writable registers. there are five tcr registers, one for each channel. each tcr selects the count clock, specifies the edge when an external clock is selected in channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (tcnt) underflow is set to 1. tcr2 is also used for channel 2 input capture control, and control of interrupt generation in the event of input capture. the tcr registers for channels 0 to 2 are initialized to h'0000 by a power-on or manual reset, but are not initialized and retain their contents in st andby mode. the tcr registers for channels 3 and 4 of the SH7750r are initialized to h'0000 by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode.
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 346 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1. channel 0 and 1 tcr bit configuration bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 ? ? unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w 2. channel 2 tcr bit configuration bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? icpf unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 3. tcr bit configuration for channels 3 and 4 (SH7750r only) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 ? ? unie ? ? tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r r r/w r/w r/w
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 347 of 1076 sep 24, 2013 bits 15 to 9, 7, and 6 (channels 0 and 1); bits 15 to 10 (channel 2)?reserved: these bits are always read as 0. a write to these bits is invalid, but the write value should always be 0. bit 9?input capture interrupt flag (icpf) (channel 2 only): status flag, provided in channel 2 only, that indicates th e occurrence of input capture. bit 9: icpf description 0 input capture has not occurred (initial value) [clearing condition] when 0 is written to icpf 1 input capture has occurred [setting condition] when input capture occurs * note: * writing 1 does not change the value. bit 8?underflow flag (unf): status flag that indicates the occurrence of underflow. bit 8: unf description 0 tcnt has not underflowed (initial value) [clearing condition] when 0 is written to unf 1 tcnt has underflowed [setting condition] when tcnt underflows * note: * writing 1 does not change the value.
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 348 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 7 and 6?input capture control (icpe1, icpe0) (channel 2 only): these bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. when the input capture function is used, a data transfer request is sent to the dmac in the event of input capture. when using the input capture function, the tclk pin must be designated as an input pin with the tcoe bit in the tocr register. the ckeg bits speci fy whether the rising edge or falling edge of the tclk signal is used to set the tcnt2 value in the input capture register (tcpr2). the tcnt2 value is set in tcpr2 only when the tcr2.icpf bit is 0. when the tcr2.icpf bit is 1, tcpr2 is not set in the event of input captur e. when input capture oc curs, a dmac transfer request is generated regardless of the value of the tcr2.icpf bit. however, a new dmac transfer request is not generated until proces sing of the previous request is finished. bit 7: icpe1 bit 6: icpe0 description 0 0 input capture function is not used (initial value) 1 reserved (do not set) 1 0 input capture function is used, but interrupt due to input capture (ticpi2) is not enabled data transfer request is sent to dmac in the event of input capture 1 input capture function is used, and interrupt due to input capture (ticpi2) is enabled data transfer request is sent to dmac in the event of input capture bit 5?underflow interrupt control (unie): controls enabling or disabling of interrupt generation when the unf status flag is set to 1, indicating tcnt underflow. bit 5: unie description 0 interrupt due to underflow (tuni) is not enabled (initial value) 1 interrupt due to underflow (tuni) is enabled
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 349 of 1076 sep 24, 2013 bits 4 and 3?clock edge 1 and 0 (ckeg1, ckeg0): these bits select the external clock input edge when an external clock is selected or the i nput capture function is used in channels 0 to 2. bit 4: ckeg1 bit 3: ckeg0 description 0 0 count/input capture register set on rising edge (initial value) 1 count/input capture register set on falling edge 1 x count/input capture register set on both rising and falling edges note: x: 0 or 1 (don't care) bits 2 to 0?timer prescaler 2 to 0 (tpsc2?tpsc0): these bits select the tcnt count clock. with channels 0 to 2, when the on-chip rtc outp ut clock is selected as the count clock for a channel, that channel can operate even in module standby mode. when another clock is selected, the channel does not operate in standby mode. bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 counts on pck/4 (initial value) 1 counts on pck/16 1 0 counts on pck/64 1 counts on pck/256 1 0 0 counts on pck/1024 1 reserved (do not set) 1 0 counts on on-chip rtc output clock (do not set this pattern for channel 3 or 4) 1 counts on external clock (do not set this pattern for channel 3 or 4)
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 350 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 12.2.7 input capture register 2 (tcpr2) tcpr2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. the input capture function is controlled by means of the input capture control bits (icpe) and clock edge bits (ckeg) in tcr2. when input capture occurs, the tcnt2 value is copied into tcpr2. the value is set in tcpr2 only when the icpf bit in tcr2 is 0. tcpr2 is not initialized by a power-on or manual reset, or in standby mode. bit: 31 30 29 2 1 0 initial value: undefined r/w: r r r r r r 12.3 operation each channel has a 32-bit timer counter (tcnt) th at performs count-down operations, and a 32- bit timer constant register (tcor). the channels have an auto-reload function that allows cyclic count operations, and can also pe rform external event counting. channel 2 also has an input capture function. 12.3.1 counter operation when one of bits str0?str4 is set to 1 in the timer start register (tstr, tstr2), the timer counter (tcnt) for the corresponding channel starts counting. when tcnt underflows, the unf flag is set in the corresponding timer control register (tcr). if the unie bit in tcr is set to 1 at this time, an interrupt request is sent to the cpu. at the same time, the value is copied from tcor into tcnt, and the count-down continues (auto-reload function).
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 351 of 1076 sep 24, 2013 example of count operation setting procedure: figure 12.2 shows an example of the count operation setting procedure. 1. select the count clock, for channel 0, 1, or 2, with bits tpsc2?tpsc0 in the timer control register (tcr). when an external clock is selected, set the tclk pin to input mode with the tcoe bit in tocr, and select the external clock edge with bits ckeg1 and ckeg0 in tcr. 2. specify whether an interrupt is to be generated on tcnt underflow with the unie bit in tcr. 3. when the input capture function is used, set the icpe bits in tcr, including specification of whether the interrupt function is to be used. 4. set a value in the timer constant register (tcor). 5. set the initial value in the timer counter (tcnt). 6. set the str bit to 1 in the timer start re gister (tstr, tstr2) to start the count. 1 2 operation selection select count clock underflow interrupt g eneration settin g when input capture function is used 3 4 5 6 input capture interrupt g eneration settin g timer constant re g ister settin g set initial timer counter value start count note: when an interrupt is g enerated, clear the source fla g in the interrupt handler. if the interrupt enabled state is set without clearin g the fla g , another interrupt will be g enerated. figure 12.2 example of coun t operation setting procedure
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 352 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 auto-reload count operation: figure 12.3 shows the tcnt auto-reload operation. tcor h'00000000 str0?str2 unf tcnt value tcor value set in tcnt on underflow time figure 12.3 tcnt auto-reload operation tcnt count timing: ? operating on internal clock any of five count clocks (pck/4, pck/16, pck/64, pck/256, or pck/1024) scaled from the peripheral module clock can be selected as the count clock by means of the tpsc2?tpsc0 bits in tcr. figure 12.4 shows the timing in this case. pck internal clock tcnt n + 1 n n ? 1 figure 12.4 count timing when operating on internal clock
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 353 of 1076 sep 24, 2013 ? operating on external clock for channels 0 to 2, external clock pin (tclk) input can be selected as the timer clock by means of the tpsc2?tpsc0 bits in tcr. the rising edge, falling edge, or both edges can be selected as the detected edge of the external clock with the ckeg1 and ckeg0 bits in tcr. figure 12.5 shows the timing for both-edge detection. n + 1 n ? 1 n pck external clock input pin tcnt figure 12.5 count timing when operating on external clock ? operating on on-chip rtc output clock the on-chip rtc output clock can be selected as the timer clock in channels 0 to 2 by means of the tpsc2?tpsc0 bits in tcr. figure 12.6 shows the timing in this case. n + 1 n n ? 1 rtc output clock tcnt figure 12.6 count timing when op erating on on-chip rtc output clock 12.3.2 input capture function channel 2 has an input capture function. the procedure for using the input capture function is as follows: 1. use the tcoe bit in the timer output control register (tocr) to set the tclk pin to input mode. 2. use bits tpsc2?tpsc0 in the timer control register (tcr) to set an internal clock or the on- chip rtc output clock as the timer operating clock. 3. use bits ipce1 and ipce0 in tcr to specify use of the input capture function, and whether interrupts are to generated when this function is used.
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 354 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 4. use bits ckeg1 and ckeg0 in tcr to specify whether the rising or falling edge of the tclk signal is to be used to set the timer counter (tcnt) value in the input capture register (tcpr2). this function cannot be used in standby mode. when input capture occurs, the tcnt2 value is set in tcpr2 only when the icpf bit in tcr2 is 0. also, a new dmac transfer request is not generated until processing of the previous request is finished. figure 12.7 shows the operation timing when the input capture function is used (with tclk rising edge detection). tcor h'00000000 tclk tcpr2 ticpi2 tcnt value tcor value set in tcnt on underflow tcnt value set time figure 12.7 operation timing wh en using input capture function
SH7750, SH7750s, SH7750r group section 12 timer unit (tmu) r01uh0456ej0702 rev. 7.02 page 355 of 1076 sep 24, 2013 12.4 interrupts there are four tmu interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. an underflow interrupt request is generated (for each channel) when the unf bit in tcr is 1 and the interrupt enable bit for the corresponding channel is 1. when the input capture function is used and an input capture request is generated, an interrupt is requested if the input capture input flag (icpf) in tcr2 is 1 and the input capture control bits (icpe1, icpe0) in tcr2 are 11. the tmu interrupt sources ar e summarized in table 12.3. table 12.3 tmu interrupt sources channel interrupt source description priority 0 tuni0 underflow interrupt 0 high 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 ticpi2 input capture interrupt 2 3 * tuni3 underflow interrupt 3 4 * tuni4 underflow interrupt 4 low note: * SH7750r only 12.5 usage notes 12.5.1 register writes when performing a register write, timer count operation must be stopped by clearing the start bit (str0?str4) for the relevant channel in the timer start register (tstr, tstr2). note that the timer start register (tstr, tstr2) can be written to, and the underflow flag (unf) and input capture flag (icpf) of the timer co ntrol registers (trcr0 to tcr4) can be cleared while the count is in progress. when the flags (unf, icpf) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared.
section 12 timer unit (tmu) SH7750, SH7750s, SH7750r group page 356 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 12.5.2 underflow flag writes (SH7750 only) if 1 is written to the unf bit in tcr when the unf bit is already set to 1, the unf bit may be cleared to 0. the following workarounds can be used to avoid this problem. 1. stopping channel counter operation use steps (i) to (iii) below to write 1 to unf. (i) stop counter operation for the channel used to write to unf. (ii) disable the dmac channels used to access peripheral modules. (iii) while sr.bl is set to 1, write (the same value as that written to tcr and using the same access size (word)) to address h'ff d80080, then write 1 to unf with the next instruction. 2. not stopping channel counter operation make sure to write 0 to unf. if it is necessary to monitor for underflows, use software to read tcnt before and after writing to unf and determine if an underflow has occurred. 12.5.3 tcnt register reads when performing a tcnt register read, processing for synchronization with the timer count operation is performed. if a timer count operation and register read processing are performed simultaneously, the tcnt counter value prior to the count-down operation is read by means of the synchronization processing. 12.5.4 resetting the rtc frequency divider when the on-chip rtc output clock is selected as the count clock, the rtc frequency divider should be reset. 12.5.5 external clock frequency ensure that the external clock frequency for any channel does not exceed pck/8.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 357 of 1076 sep 24, 2013 section 13 bus state controller (bsc) 13.1 overview the functions of the bus state co ntroller (bsc) include division of the external me mory space, and output of control signals in accordance with various types of me mory and bus interface specifications. the bsc functions allow dram, synchronous dram, sram, rom, etc., to be connected to this lsi, and also support the pcmcia interface protocol, enabling system design to be simplified and data transfers to be carri ed out at high speed by a compact system. 13.1.1 features the bsc has the following features: ? external memory space is managed as 7 independent areas ? maximum 64 mbytes for each of areas 0 to 6 ? bus width of each area can be set in a register (except area 0, which uses an external pin setting) ? wait state insertion by rdy pin ? wait state insertion can be controlled by program ? specification of types of memo ry connectable to each area ? output the control signals of memory to each area ? automatic wait cycle insertion to prevent da ta bus collisions in case of consecutive memory accesses to different areas , or a read access followed by a write access to the same area ? write strobe setup time and hold time periods can be inserted in a write cycle to enable connection to low-speed memory ? sram interface ? wait state insertion can be controlled by program ? wait state insertion by rdy pin connectable areas: 0 to 6 settable bus widths: 64, 32, 16, 8 ? dram interface ? row address/column address multiplexing according to dram capacity ? burst operation (fast page mode, edo mode) ? cas-before-ras refresh and self-refresh ? 8-cas byte control for power-down operation
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 358 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? dram control signal timing can be controlled by register settings ? consecutive accesses to the same row address connectable areas: 2, 3 settable bus widths: 64, 32, 16 ? synchronous dram interface ? row address/column address multiplexing according to synchronous dram capacity ? burst operation ? auto-refresh and self-refresh ? synchronous dram control signal timing can be controlled by register settings ? consecutive accesses to the same row address connectable areas: 2, 3 settable bus widths: 64, 32 ? burst rom interface ? wait state insertion can be controlled by program ? burst operation, executing the number of transfers set in a register connectable areas: 0, 5, 6 settable bus widths: 64*, 32, 16, 8 ? mpx interface ? address/data multiplexing connectable areas: 0 to 6 settable bus widths: 64, 32 ? byte control sram interface ? sram interface with byte control connectable areas: 1, 4 settable bus widths: 64, 32, 16 ? pcmcia interface ? wait state insertion can be controlled by program ? bus sizing function for i/o bus width ? fine refreshing control ? supports refresh operation immediately after self-refresh operation in low-power dram by means of refresh counter overflow interrupt function ? refresh counter can be used as interval timer ? interrupt request generated by compare-match ? interrupt request generated by refresh counter overflow note: * SH7750r only
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 359 of 1076 sep 24, 2013 13.1.2 block diagram figure 13.1 shows a block diagram of the bsc. cs6 ? cs0 ce2a ? ce2b bs rd / frame rd/ wr we7 ? we0 ras cas7 ? cas0 , cass cke iciord , iciowr reg iois16 internal bus bus interface wcr1 wcr2 wcr3 bcr1 bcr2 bcr3 * bcr4 * pcr rfcr rtcnt rtcor rtcsr comparator refresh control unit memory control unit area control unit wait control unit interrupt controller bsc peripheral bus legend: wcr: wait control register bcr: bus control register mcr: memory control register pcr: pcmcia control register note: * SH7750r only mcr rdy module bus rfcr: refresh count register rtcnt: refresh timer count register rtcor: refresh time constant register rtcsr: refresh timer control/status register figure 13.1 block diagram of bsc
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 360 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.1.3 pin configuration table 13.1 shows the bsc pin configuration. table 13.1 bsc pins name signals i/o description address bus a25 ? a0 o address output data bus d63 ? d52 , d31 ? d0 i/o data input/output when port functions are used and ddt mode is selected, input the dtr format. otherwise, when port functions are used, d63 ? d52 cannot be used and should be left open. data bus/port d51 ? d32/ port19 ? port0 i/o when port functions are no t used: data input/output when port functions are used: input/output port (input or output set for each bit by register) bus cycle start bs o signal that indicates the start of a bus cycle when setting synchronous dram interface: asserted once for a burst transfer for other burst transfers: asserted each data cycle chip select 6 ? 0 cs6 ? cs0 o chip select signals that indicate the area being accessed cs5 and cs6 are also used as pcmcia ce1a and ce1b read/write rd/ wr o data bus input/output direction designation signal also used as the dram/synchronous dram/pcmcia interface write designation signal row address strobe ras o ras signal when setting dram/synchronous dram interface read/column address strobe/ cycle frame rd / cass / frame o strobe signal that indicates a read cycle when setting synchronous dram interface: cas signal when setting mpx interface: frame signal
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 361 of 1076 sep 24, 2013 name signals i/o description data enable 0 we0 / cas0 / dqm0 o when setting synchronous dram interface: selection signal for d7?d0 when setting dram interface: cas signal for d7?d0 when setting mpx interface: high-level output in other cases: write strobe signal for d7?d0 data enable 1 we1 / cas1 / dqm1 o when setting synchronous dram interface: selection signal for d15?d8 when setting dram interface: cas signal for d15?d8 when setting pcmcia interface: write strobe signal when setting mpx interface: high-level output in other cases: write strobe signal for d15?d8 data enable 2 we2 / cas2 / dqm2/ iciord o when setting synchronous dram interface: selection signal for d23?d16 when setting dram interface: cas signal for d23?d16 when setting pcmcia interface: iciord signal when setting mpx interface: high-level output in other cases: write strobe signal for d23?d16 data enable 3 we3 / cas3 / dqm3/ iciowr o when setting synchronous dram interface: selection signal for d31?d24 when setting dram interface: cas signal for d31?d24 when setting pcmcia interface: iciowr signal when setting mpx interface: high-level output in other cases: write strobe signal for d31?d24 data enable 4 we4 / cas4 / dqm4 o when setting synchronous dram interface: selection signal for d39?d32 when setting dram interface: cas signal for d39?d32 when setting mpx interface: high-level output in other cases: write strobe signal for d39?d32
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 362 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 name signals i/o description data enable 5 we5 / cas5 / dqm5 o when setting synchronous dram interface: selection signal for d47?d40 when setting dram interface: cas signal for d47?d40 when setting mpx interface: high-level output in other cases: write strobe signal for d47?d40 data enable 6 we6 / cas6 / dqm6 o when setting synchronous dram interface: selection signal for d55?d48 when setting dram interface: cas signal for d55?d48 when setting mpx interface: high-level output in other cases: write strobe signal for d55?d48 data enable 7 we7 / cas7 / dqm7/ reg o when setting synchronous dram interface: selection signal for d63?d56 when setting dram interface: cas signal for d63?d56 when setting pcmcia interface: reg signal when setting mpx interface: high-level output in other cases: write strobe signal for d63?d56 ready rdy i wait state request signal area 0 mpx interface specification/ 16-bit i/o md6/ iois16 i in power-on reset: designates area 0 bus as mpx interface (1: sram, 0: mpx) when setting pcmcia interface: 16-bit i/o designation signal. valid only in little-endian mode. clock enable cke o synchronous dram clock enable control signal bus release request breq / bsack i bus release request signal/bus acknowledge signal bus use permission back / bsreq o bus use permission signal/bus request area 0 bus width/pcmcia card select md3/ ce2a * 1 md4/ ce2b * 2 i/o in power-on reset * 4 : external space area 0 bus width specification signal when setting pcmcia interface: ce2a , ce2b endian switchover/ row address strobe md5/ ras2 * 3 i/o endian specif ication in a power-on reset. * 4 ras2 when dram is connected to area 2
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 363 of 1076 sep 24, 2013 name signals i/o description master/slave switchover md7/txd i/o indicates master/slave status in a power-on reset. * 4 serial interface txd dmac0 acknowledge signal dack0 o dmac channel 0 data acknowledge dmac1 acknowledge signal dack1 o dmac channel 1 data acknowledge read/column address strobe/ cycle frame 2 rd2 o same signal as rd / cass / frame this signal is used when the rd / cass / frame signal load is heavy. read/write 2 rd/ wr2 o same signal as rd/ wr this signal is used when the rd/ wr signal load is heavy. notes: 1. md3/ ce2a input/output switching is performed by bcr1.a56pcm. output is selected when bcr1.a56pcm = 1. 2. md4/ ce2b input/output switching is performed by bcr1.a56pcm. output is selected when bcr1.a56pcm = 1. 3. md5/ ras2 input/output switching is performed by bcr1.dramtp. output is selected when bcr1.dramtp (2?0) = 101. 4. in a power-on reset by means of the reset pin.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 364 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.1.4 register configuration the bsc has the 11 registers shown in table 13.2. in addition, the synchronous dram mode register incorporated in synchronous dram can also be accessed as this lsi's register. the functions of these registers incl ude control of interfaces to vari ous types of memory, wait states, and refreshing. table 13.2 bsc registers name abbrevia- tion r/w initial value p4 address area 7 address access size bus control register 1 bcr1 r/ w h'0000 0000 h'ff80 0000 h'1f80 0000 32 bus control register 2 bcr2 r/ w h'3ffc h'ff80 0004 h'1f80 0004 16 bus control register 3 * 2 bcr3 r/w h'0000 h 'ff80 0050 h'1f80 0050 16 bus control register 4 * 2 bcr4 r/w h'0000 0000 h'fe0a 00f0 h'1e0a 00f0 32 wait state control register 1 wcr1 r/w h'7777 7777 h'ff80 0008 h'1f80 0008 32 wait state control register 2 wcr2 r/w h'fffe efff h'ff80 000c h'1f80 000c 32 wait state control register 3 wcr3 r/w h'0777 7777 h'ff80 0010 h'1f80 0010 32 memory control register mcr r/ w h'0000 0000 h'ff80 0014 h'1f80 0014 32 pcmcia control register pcr r/w h'0000 h'ff80 0018 h'1f80 0018 16 refresh timer control/status register rtcsr r/w h'0000 h'ff 80 001c h'1f80 001c 16 refresh timer counter rtcnt r/ w h'0000 h'ff80 0020 h'1f80 0020 16 refresh time constant counter rtcor r/w h'0000 h 'ff80 0024 h'1f80 0024 16 refresh count register rfcr r/ w h'0000 h'ff80 0028 h'1f80 0028 16 for area 2 sdmr2 w ? h'ff90 xxxx * 1 h'1f90 xxxx 8 synchronous dram mode registers for area 3 sdmr3 h'ff94 xxxx * 1 h'1f94 xxxx notes: 1. for details, see section 13.2.10, synchronous dram mode register (sdmr). 2. settable only for SH7750r.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 365 of 1076 sep 24, 2013 13.1.5 overview of areas space divisions: the architecture of this lsi provides a 32-bit virtual address space. the virtual address is divided into five areas according to the upper address value. external memory space comprises a 29-bit address space, divided into eight areas. the virtual address can be allocated to any external address by means of the memory management unit (mmu). details are given in section 3, memory management unit (mmu). this section describes the areas into which the external address is divided. with this lsi, various kinds of memory or pc cards can be connected to the seven areas of external address as shown in tabl e 13.3, and chip select signals ( cs0 ? cs6 , ce2a , ce2b ) are output for each of these areas. cs0 is asserted when accessing area 0, and cs6 when accessing area 6. when dram or synchronous dram is connected to area 2 or 3, signals such as ras , cas , rd/ wr , and dqm are also asserted. when the pcmc ia interface is selected for area 5 or 6, ce2a , ce2b is asserted in addition to cs5 , cs6 for the byte to be accessed. h'0000 0000 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff h'e400 0000 h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1fff ffff h'1c00 0000 area 0 ( cs0 ) area 1 ( cs 1 ) area 2 ( cs2 ) area 3 ( cs 3 ) area 4 ( cs 4 ) area 5 ( cs 5 ) area 6 ( cs6 ) area 7 (reserved area) p0 and u0 areas p1 area p2 area p3 area physical address space (mmu off) virtual address space (mmu on) external memory space store queue area p4 area p0 and u0 areas 256 p1 area p2 area p3 area store queue area p4 area notes: 1. when the mmu is off (mmucr.at = 0), the top 3 bits of the 32-bit address are i g nored, and memory is mapped onto a fixed 29-bit external address. 2. when the mmu is on (mmucr.at = 1), the p0, u0, p3, and store queue areas can be mapped onto any external address usin g the tlb. for details, see section 3, memory mana g ement unit (mmu). figure 13.2 correspondence between virtual address space and external memory space
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 366 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.3 external memory space map area external addresses size connectable memory settable bus widths access size sram 8, 16, 32, 64 * 1 burst rom 8, 16, 32 * 1 , 64 * 7 0 h'00000000 ? h'03ffffff 64 mbytes mpx 32, 64 * 1 8 , 16 , 32 , 64 * 6 bits, 32 bytes sram 8, 16, 32, 64 * 2 mpx 32, 64 * 2 1 h'04000000 ? h'07ffffff 64 mbytes byte control sram 16, 32, 64 * 2 8 , 16 , 32 , 64 * 6 bits, 32 bytes sram 8, 16, 32, 64 * 2 synchronous dram 32, 64 * 2 * 3 dram 16, 32 * 2 * 3 2 h'08000000 ? h'0bffffff 64 mbytes mpx 32, 64 * 2 8 , 16 , 32 , 64 * 6 bits, 32 bytes sram 8, 16, 32, 64 * 2 synchronous dram 32, 64 * 2 * 3 dram 16, 32, 64 * 2 * 3 3 h'0c000000 ? h'0fffffff 64 mbytes mpx 32, 64 * 2 8 , 16 , 32 , 64 * 6 bits, 32 bytes sram 8, 16, 32, 64 * 2 mpx 32, 64 * 2 4 h'10000000 ? h'13ffffff 64 mbytes byte control ram 16, 32, 64 * 2 8 , 16 , 32 , 64 * 6 bits, 32 bytes sram 8, 16, 32, 64 * 2 mpx 32, 64 * 2 burst rom 8, 16, 32 * 2 , 64 * 7 5 h'14000000 ? h'17ffffff 64 mbytes pcmcia 8, 16 * 2 * 4 8 , 16 , 32 , 64 * 6 bits, 32 bytes sram 8, 16, 32, 64 * 2 mpx 32, 64 * 2 burst rom 8,16, 32 * 2 , 64 * 7 6 h'18000000 ? h'1bffffff 64 mbytes pcmcia 8,16 * 2 * 4 8 , 16 , 32 , 64 * 6 bits, 32 bytes 7 * 5 h'1c000000 ? h'1fffffff 64 mbytes ? ? notes: 1. memory bus width specified by external pins 2. memory bus width specified by register 3. with synchronous dram interface, bus width is 32 or 64 bits only. with dram interface, bus width is 16 or 32 bits only for area 2, and 16, 32, or 64 bits only for area 3. bus width of area 2 is as same as that of area 3 which is specified by mcr. 4. with pcmcia interface, bus width is 8 or 16 bits only. 5. do not access a reserved area, as operation cannot be guaranteed in this case.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 367 of 1076 sep 24, 2013 6. 64-bit access applies only to transfer by the dmac. (chcrn. ts = 000) in a transfer to an external memory by fm ov (fpscr.sz = 1), two transfer operations, each with an access size of 32 bits, are conducted. 7. settable only for SH7750r. area 0: h'00000000 area 1: h'04000000 area 2: h'08000000 area 3: h'0c000000 area 4: h'10000000 area 5: h'14000000 area 6: h'18000000 sram/burst rom/mpx sram/mpx/byte control sram sram/synchronous dram/dram/ mpx sram/synchronous dram/dram/ mpx sram/mpx/byte control sram sram/burst rom/pcmcia/mpx sram/burst rom/pcmcia/mpx the pcmcia interface is for memory and i/o card use figure 13.3 external memory space allocation memory bus width: in this lsi, the memory bus width ca n be set independently for each space. for area 0, a bus size of 8, 16, 32, or 64 bits can be selected in a power-on reset by the reset pin, using external pins. the relationship between the external pins (md4 and md3) and the bus width in a power-on reset is shown below. md4 md3 bus width 0 0 64 bits 1 8 bits 1 0 16 bits 1 32 bits when sram interface or rom is used in areas 1 to 6, a bus width of 8, 16, 32, or 64 bits can be selected with bus control register 2 (bcr2). when burst rom is used, a bus width of 8, 16, 32, or 64* bits can be selected. when byte control sram interface is used, a bus width of 16, 32, or 64 bits can be selected. when the mpx interface is used , a bus width of 32 or 64 bits can be selected. when the dram interface is used, a bus width of 16, 32, or 64 bits can be selected with the
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 368 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 memory control register (mcr). when the dram interface is used for area 2 or 3, a bus width of 16 or 32 bits should be set. for the synchronous dram interface, set a bus width of 32 or 64 bits in the mcr register. when using the pcmcia interface, se t a bus width of 8 or 16 bits. for details, see section 13.3.7, pcmcia interface. when using port functions, set a bus width of 8, 16, or 32 bits for all areas. for details, see section 13.2.2, bus control re gister 2 (bcr2), and section 13.2.8, memory control register (mcr). the area 7 address range, h'1c000000 to h'1fffff fff, is a reserved space and must not be used. note: * SH7750r only 13.1.6 pcmcia support this lsi supports pcmcia complia nt interface specifications for ex ternal memory space areas 5 and 6. the interfaces supported are the ic memory car d interface and i/o card interface stipulated in jeida specifications version 4.2 (pcmcia2.1). external memory space areas 5 and 6 support both the ic memory card interface and the i/o card interface. the pcmcia interface is supporte d only in little-endian mode. table 13.4 pcmcia interface features item features access random access data bus 8/16 bits memory type mask rom, otprom, eprom, eeprom, flash memory, sram common memory capacity max. 64 mbytes attribute memory capacity max. 64 mbytes others dynamic bus sizing for i/o bus width, access to pcmcia interface from address translation areas
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 369 of 1076 sep 24, 2013 table 13.5 pcmcia support interfaces ic memory card interface i/o card interface pin signal name i/o function signal name i/o function corresponding lsi pin 1 gnd ground gnd ground ? 2 d3 i/o data d3 i/o data d3 3 d4 i/o data d4 i/o data d4 4 d5 i/o data d5 i/o data d5 5 d6 i/o data d6 i/o data d6 6 d7 i/o data d7 i/o data d7 7 ce1 i card enable ce1 i card enable cs5 or cs6 8 a10 i address a10 i address a10 9 oe i output enable oe i output enable rd 10 a11 i address a11 i address a11 11 a9 i address a9 i address a9 12 a8 i address a8 i address a8 13 a13 i address a13 i address a13 14 a14 i address a14 i address a14 15 we / pgm i write enable we / pgm i write enable we1 16 rdy / bsy o ready/busy ireq o interrupt request sensed on port 17 vcc operating power supply vcc operating power supply ? 18 vpp1 programming power supply vpp1 programming/ peripheral power supply ? 19 a16 i address a16 i address a16 20 a15 i address a15 i address a15 21 a12 i address a12 i address a12 22 a7 i address a7 i address a7 23 a6 i address a6 i address a6 24 a5 i address a5 i address a5 25 a4 i address a4 i address a4 26 a3 i address a3 i address a3 27 a2 i address a2 i address a2
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 370 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ic memory card interface i/o card interface pin signal name i/o function signal name i/o function corresponding lsi pin 28 a1 i address a1 i address a1 29 a0 i address a0 i address a0 30 d0 i/o data d0 i/o data d0 31 d1 i/o data d1 i/o data d1 32 d2 i/o data d2 i/o data d2 33 wp * o write protect iois16 o 16-bit i/o port iois16 34 gnd ground gnd ground ? 35 gnd ground gnd ground ? 36 cd1 o card detection cd1 o card detection sensed on port 37 d11 i/o data d11 i/o data d11 38 d12 i/o data d12 i/o data d12 39 d13 i/o data d13 i/o data d13 40 d14 i/o data d14 i/o data d14 41 d15 i/o data d15 i/o data d15 42 ce2 i card enable ce2 i card enable ce2a or ce2b 43 rfsh i refresh request rfsh i refresh request output from port 44 rfu reserved iord i i/o read iciord 45 rfu reserved iowr i i/o write iciowr 46 a17 i address a17 i address a17 47 a18 i address a18 i address a18 48 a19 i address a19 i address a19 49 a20 i address a20 i address a20 50 a21 i address a21 i address a21 51 vcc power supply vcc power supply ? 52 vpp2 programming power supply vpp2 programming/ peripheral power supply ? 53 a22 i address a22 i address a22 54 a23 i address a23 i address a23 55 a24 i address a24 i address a24
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 371 of 1076 sep 24, 2013 ic memory card interface i/o card interface pin signal name i/o function signal name i/o function corresponding lsi pin 56 a25 i address a25 i address a25 57 rfu reserved rfu reserved ? 58 reset i reset reset i reset output from port 59 wait o wait request wait o wait request rdy * 2 60 rfu reserved inpack o input acknowledge ? 61 reg i attribute memory space select reg i attribute memory space select we7 62 bvd2 o battery voltage detection spkr o digital speech signal sensed on port 63 bvd1 o battery voltage detection stschg o card status change sensed on port 64 d8 i/o data d8 i/o data d8 65 d9 i/o data d9 i/o data d9 66 d10 i/o data d10 i/o data d10 67 cd2 o card detection cd2 o card detection sensed on port 68 gnd ground gnd ground ? notes: 1. wp is not supported. 2. input an external wait request with correct polarity.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 372 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.2 register descriptions 13.2.1 bus control register 1 (bcr1) bus control register 1 (bcr1) is a 32-bit readable/w ritable register that specifies the function, bus cycle status, etc., of each area. bcr1 is initialized to h'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. external memory space other th an area 0 should not be accessed until register initialization is completed. bit: 31 30 29 28 27 26 25 24 endian master a0mpx ? ? dpup * 2 ipup opup initial value: 0/1 * 1 0/1 * 1 0/1 * 1 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? ? a1mbc a4mbc breqen pshr memmpx dmabst * 2 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r bit: 15 14 13 12 11 10 9 8 hizmem hizcnt a0bst2 a0bst1 a0bst0 a5bst2 a5bst1 a5bst0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a6bst2 a6bst1 a6bst0 dramtp2 dramtp1 dramtp0 ? a56pcm initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r r/w notes: 1. these bits sample external pin values in a power-on reset by means of the reset pin. 2. SH7750r only.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 373 of 1076 sep 24, 2013 bit 31?endian flag (endian): samples the value of the endi an specification external pin (md5) in a power-on reset by the reset pin. the endian mode of all spaces is determined by this bit. endian is a read-only bit. bit 31: endian description 0 in a power-on reset, the endian setting external pin (md5) is low, designating big-endian mode 1 in a power-on reset, the endian setting external pin (md5) is high, designating little-endian mode bit 30?master/slave flag (master): samples the value of the master/slave specification external pin (md7) in a power-on reset by the reset pin. the master/slave status of all spaces is determined by this bit. master is a read-only bit. bit 30: master description 0 in a power-on reset, the master/slave setting external pin (md7) is high, designating master mode 1 in a power-on reset, the master/slave setting external pin (md7) is low, designating slave mode bit 29?area 0 memory type (a0mpx): samples the value of the area 0 memory type specification external pin (md6) in a power-on reset by the reset pin. the memory type of area 0 is determined by this bit. a0mpx is a read-only bit. bit 29: a0mpx description 0 in a power-on reset, the external pin specifying the area 0 memory type (md6) is high, designating the area 0 as sram interface 1 in a power-on reset, the external pin specifying the area 0 memory type (md6) is low, designating the area 0 as mpx interface bits 28, 27, 26*, 23, 22, 16*, and 1?reserved: these bits are always read as 0, and should only be written with 0. note: * SH7750, SH7750s only.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 374 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 26?data pin pullup resistor control (dpup) (SH7750r only): controls the pullup resistance of the data pins (d63 to d0). it is ini tialized at a power-on reset. the pins are not pulled up when access is performed or when the bus is released, even if the on setting is selected. bit 26: dpup description 0 sets pullup resistance of data pins (d63 to d0) on (initial value) 1 sets pullup resistance of data pins (d63 to d0) off bit 25?control input pin pull-up resistor control (ipup): specifies the pull-up resistor status for control input pins (nmi, irl0 ? irl3 , breq , md6/ iois16 , rdy ). ipup is initialized by a power-on reset. bit 25: ipup description 0 pull-up resistor is on for control input pins (nmi, irl0 ? irl3 , breq , md6/ iois16 , rdy ) (initial value) 1 pull-up resistor is off fo r control input pins (nmi, irl0 ? irl3 , breq , md6/ iois16 , rdy ) bit 24?control output pin pull-up resistor control (opup): specifies the pull-up resistor status for control output pins (a[25:0], bs , csn , rd , wen , rd/ wr , ras , ras2 , ce2a , ce2b , rd2 , rd/ wr2 ) when high-impedance. opup is initialized by a power-on reset. bit 24: opup description 0 pull-up resistor is on for control output pins (a[25:0], bs , csn , rd , wen , rd/ wr , ras , ras2 , ce2a , ce2b , rd2 , rd/ wr2 ) (initial value) 1 pull-up resistor is off for control output pins (a[25:0], bs , csn , rd , wen , rd/ wr , ras , ras2 , ce2a , ce2b , rd2 , rd/ wr2 ) bit 21?area 1 sram byte control mode (a1mbc): mpx interface has priority when an mpx interface is set. this bit is initialized by a power-on reset. bit 21: a1mbc description 0 area 1 sram is set to normal mode (initial value) 1 area 1 sram is set to byte control mode
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 375 of 1076 sep 24, 2013 bit 20?area 4 sram byte control mode (a4mbc): mpx interface has priority when an mpx interface is set. this bit is initialized by a power-on reset. bit 20: a4mbc description 0 area 4 sram is set to normal mode (initial value) 1 area 4 sram is set to byte control mode bit 19?breq enable (breqen): indicates whether external requests can be accepted. breqen is initialized to the extern al request acceptance disabled stat e by a power-on reset. it is ignored in the case of a slave mode startup. bit 19: breqen description 0 external requests are not accepted (initial value) 1 external requests are accepted bit 18?partial-sharing bit (pshr): sets partial-sharing mode. pshr is valid only in the case of a master mode startup. bit 18: pshr description 0 master mode (initial value) 1 partial-sharing mode bit 17?area 1 to 6 mpx interf ace specification (memmpx): sets the mpx interface when areas 1 to 6 are set as sram interface (or bur st rom interface). memmpx is initialized by a power-on reset. bit 17: memmpx description 0 sram interface (or burst rom interface) is selected when areas 1 to 6 are set as sram interface (or burst rom interface) (initial value) 1 mpx interface is selected when areas 1 to 6 are set as sram interface (or burst rom interface)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 376 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 16?dmac burst mode transfer priori ty setting (dmabst) (SH7750r only): specifies the priority of burst mo de transfers by the dmac. when of f, the priority is as follows: bus privilege released, refresh, dmac, cpu. when on, the bus privileges are released and refresh operations are not performed until the end of the dmac's burst transfer. this bit is initialized at a power-on reset. bit 16: dmabst description 0 dmac burst mode transfer priority specification off (initial value) 1 dmac burst mode transfer priority specification on bit 15?high impedance control (hizmem): specifies the state of address and other signals (a[25:0], bs , csn , rd/ wr , ce2a , ce2b ) in software standby mode. bit 15: hizmem description 0 the a[25:0], bs , csn , rd/ wr , ce2a , and ce2b signals go to high- impedance (high-z) in standby mode and when the bus is released (initial value) 1 the a[25:0], bs , csn , rd/ wr , ce2a , and ce2b signals are driven in standby mode. when the bus is released, they go to high-impedance. bit 14?high impedance control (hizcnt): specifies the state of the ras and cas signals in software standby mode and when the bus is released. bit 14: hizcnt description 0 the ras , ras2 , wen / casn /dqmn, rd / cass / frame , and rd2 signals go to high-impedance (high-z) in standby mode and when the bus is released (initial value) 1 the ras , ras2 , wen / casn /dqmn, rd / cass / frame , and rd2 signals are driven in standby mode and when the bus is released
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 377 of 1076 sep 24, 2013 bits 13 to 11?area 0 burst rom control (a0bst2?a0bst0): these bits specify whether burst rom interface is used in area 0. when burs t rom interface is used, they also specify the number of accesses in a burst. if area 0 is an mpx interface area, th ese bits are ignored. bit 13: a0bst2 bit 12: a0bst1 bit 11: a0bst0 description 0 0 0 area 0 is accessed as sram interface (initial value) 1 area 0 is accessed as burst rom interface (4 consecutive accesses) can be used with 8-, 16-, 32-, or 64 * -bit bus width 1 0 area 0 is accessed as burst rom interface (8 consecutive accesses) can only be used with 8-, 16-, or 32-bit bus width 1 area 0 is accessed as burst rom interface (16 consecutive accesses) can only be used with 8- or 16-bit bus width. do not specify for 32-bit bus width 1 0 0 area 0 is accessed as burst rom interface (32 consecutive accesses) can only be used with 8-bit bus width 1 reserved 1 0 reserved 1 reserved note: * settable only for SH7750r.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 378 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 10 to 8?area 5 burst enable (a5bst2?a5bst0): these bits specify whether burst rom interface is used in area 5. wh en burst rom interface is used, th ey also specify the number of accesses in a burst. if area 5 is an mpx interface area, these bits are ignored. bit 10: a5bst2 bit 9: a5bst1 bit 8: a5bst0 description 0 0 0 area 5 is accessed as sram interface (initial value) 1 area 5 is accessed as burst rom interface (4 consecutive accesses) can be used with 8-, 16-, 32-, or 64 * -bit bus width 1 0 area 5 is accessed as burst rom interface (8 consecutive accesses) can only be used with 8-, 16-, or 32-bit bus width 1 area 5 is accessed as burst rom interface (16 consecutive accesses) can only be used with 8- or 16-bit bus width. do not specify for 32-bit bus width 1 0 0 area 5 is accessed as burst rom interface (32 consecutive accesses) can only be used with 8-bit bus width 1 reserved 1 0 reserved 1 reserved notes: clear to 0 when pcmcia interface is set. * settable only for SH7750r.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 379 of 1076 sep 24, 2013 bits 7 to 5?area 6 burst enable (a6bst2?a6bst0): these bits specify whether burst rom interface is used in area 6. wh en burst rom interface is used, th ey also specify the number of accesses in a burst. if area 6 is an mpx interface area, these bits are ignored. bit 7: a6bst2 bit 6: a6bst1 bit 5: a6bst0 description 0 0 0 area 6 is accessed as sram interface (initial value) 1 area 6 is accessed as burst rom interface (4 consecutive accesses) can be used with 8-, 16-, 32-, or 64 * -bit bus width 1 0 area 6 is accessed as burst rom interface (8 consecutive accesses) can only be used with 8-, 16-, or 32-bit bus width 1 area 6 is accessed as burst rom interface (16 consecutive accesses) can only be used with 8- or 16-bit bus width. do not specify for 32-bit bus width 1 0 0 area 6 is accessed as burst rom interface (32 consecutive accesses) can only be used with 8-bit bus width 1 reserved 1 0 reserved 1 reserved notes: clear to 0 when pcmcia interface is set. * settable only for SH7750r.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 380 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 4 to 2?area 2 and 3 memory type (dramtp2?dramtp0): these bits specify the type of memory connected to areas 2 and 3. rom, sram, flash rom, etc., can be connected as sram interface. dram and synchronous dram can also be connected. bit 4: dramtp2 bit 3: dramtp1 bit 2: dramtp0 description 0 0 0 areas 2 and 3 are sram interface or mpx interface * 1 (initial value) 1 reserved (cannot be set) 1 0 area 2 is sram interface or mpx interface * 1 , area 3 is synchronous dram interface 1 areas 2 and 3 are synchronous dram interface 1 0 0 area 2 is sram interface or mpx interface * 1 , area 3 is dram interface 1 areas 2 and 3 are dram interface * 2 1 0 reserved (cannot be set) 1 reserved (cannot be set) notes: 1. selection of sram interface or mpx interface is determined by the setting of the memmpx bit 2. when this mode is selected, 16 or 32 bits should be specified as the bus width for areas 2 and 3. in this mode the md5 pin is designated for output as the ras2 pin. bit 0?area 5 and 6 bus type (a56pcm): specifies whether areas 5 and 6 are accessed as pcmcia interface. the setting of these bits has priority over the memmpx bit settings. bit 0: a56pcm description 0 areas 5 and 6 are accessed as sram interface (initial value) 1 areas 5 and 6 are accessed as pcmcia interface * note: * the md3 pin is desig nated for output as the ce2a pin. the md4 pin is desig nated for output as the ce2b pin.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 381 of 1076 sep 24, 2013 13.2.2 bus control register 2 (bcr2) bus control register 2 (bcr2) is a 16-bit readable/w ritable register that specifies the bus width for each area, and whether a 16-bit port is used. bcr2 is initialized to h'3ffc by a power-on reset, but is not initialized by a manual reset or in standby mode. external memory space other than area 0 should not be accessed until register initialization is completed. bit: 15 14 13 12 11 10 9 8 a0sz1 a0sz0 a6sz1 a6sz0 a5sz1 a5sz0 a4sz1 a4sz0 initial value: 0/1 * 0/1 * 1 1 1 1 1 1 r/w: r r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a3sz1 a3sz0 a2sz1 a2sz0 a1sz1 a0sz0 ? porten initial value: 1 1 1 1 1 1 0 0 r/w: r/w r/w r/w r/w r/w r/w ? r/w note: * these bits sample the values of the exte rnal pins that specify the area 0 bus size. bits 15 and 14?area 0 bus width (a0sz1, a0sz0): these bits sample the external pins, md4 and md3 that specify the bus si ze in a power-on reset by the reset pin. they are read-only bits. bit 15 bit 14 a0sz1 a0sz0 description 0 0 bus width is 64 bits 1 bus width is 8 bits 1 0 bus width is 16 bits 1 bus width is 32 bits
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 382 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 2n + 1, 2n?area n (1 to 6) bus width specification (ansz1, ansz0): these bits specify the bus width of area n (n = 1 to 6). (bit 0): porten bit 2n + 1: ansz1 bit 2n: ansz0 description 0 0 0 bus width is 64 bits 1 bus width is 8 bits 1 0 bus width is 16 bits 1 bus width is 32 bits (initial value) 1 0 0 reserved (setting prohibited) 1 bus width is 8 bits 1 0 bus width is 16 bits 1 bus width is 32 bits bit 1?reserved: this bit is always read as 0, and should only be written with 0. bit 0?port function enable (porten): specifies whether pins d51 to d32 are used as a 20- bit port. when this function is used, a bus width of 8, 16, or 32 bits should be set for all areas. bit 0: porten description 0 d51 to d32 are not used as a port (initial value) 1 d51 to d32 are used as a port
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 383 of 1076 sep 24, 2013 13.2.3 bus control register 3 (bcr3) (SH7750r only) bus control register 3 (bcr3) is a 16-bit readable/w ritable register that specifies the selection of either the mpx interface or th e sram interface and specifies the burst length when the synchronous dram interface is used. bcr3 is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. no external memory space other th an area 0 should be accessed before register initialization has been completed. bit: 15 14 13 12 11 10 9 8 memmode a1mpx a4mpx ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? sdbl initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit 15 ? a1mpx/a4mpx enable (memmode): determines whether or not the selection of either the mpx interface or th e sram interface is by a1mpx and a4mpx rather than by memmpx. bit 15: memmode description 0 mpx or sram interface is selected by memmpx (initial value) 1 mpx or sram interface is selected by a1mpx and a4mpx
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 384 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 14 and 13 ? mpx-interface specification for area 1 and 4 (a1mpx, a4mpx): these bits specify the types of memory connected to areas 1 and 4. these settings are validated by memmode. bit 14: a1mpx description 0 sram/byte control sram interface is selected for area 1 (initial value) 1 mpx interface is selected for area 1 bit 13: a4mpx description 0 sram/byte control sram interface is selected for area 4 (initial value) 1 mpx interface is selected for area 4 bits 12 to 1?reserved: these bits are always read as 0, and should only be written with 0. bit 0 ? burst length (sdbl): sets the burst length when th e synchronous dram interface is used. the burst-length setting is only valid when the bus width is 32 bits. bit 0: sdbl description 0 burst length is 8 (initial value) 1 burst length is 4 13.2.4 bus control register 4 (bcr4) (SH7750r only) bus control register 4 (bcr4) is a 32-bit readab le/writable register that enables asynchronous input to the pin corresponding to each bit. bcr4 is initialized to h'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. when asynchronous input is set (asyncn = 1), the sampling timing is one cycle earlier than when synchronous input is set (asyncn = 0)* (see figure 13.4) the timings shown in this section and section 22 , electrical characteristics, are all for the case where synchronous input is set (asyncn = 0). note: * with the synchronous input setting, ensure that setup and hold times are observed.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 385 of 1076 sep 24, 2013 t1 tw tw twe t2 ckio rdy rdy (bcr4.async0 = 0) (bcr4.async0 = 1) figure 13.4 example of rdy sampling timing at which bcr4 is set (two wait cycles are inserted by wcr2)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 386 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? async initial value: 0 0 0 0 0 0 0 0 r/w: r r r r/w r/w r/w r/w r/w
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 387 of 1076 sep 24, 2013 bits 31 to 5 ? reserved: these bits are always read as 0, and should only be written with 0. bits 4 to 0 ? asynchronous input: these bits enable asynchronous input to the corresponding pin. bits 4 to 0: asyncn description 0 input to corresponding pin is synchronous with ckio (initial value) 1 input to corresponding pin can be asynchronous with ckio bit corresponding pin 4 iois16 3 dreq1 2 dreq0 1 breq 0 rdy
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 388 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.2.5 wait control register 1 (wcr1) wait control register 1 (wcr1) is a 32-bit readable /writable register that specifies the number of idle state insertion cycles for each area. with some kinds of memory, data bus drive does not go off immediately after the read signal from off-chip goes off. as a result, there is a possibility of a data bus collision when consec utive memory accesses are perfor med on memory in different areas, or when a memory write is performed immedi ately after a read. in this lsi, the number of idle cycles set in the wcr1 register are inserted au tomatically if there is a possibility of this kind of data bus collision. wcr1 is initialized to h'77777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 31 30 29 28 27 26 25 24 ? dmaiw2 dmaiw1 dmaiw0 ? a6iw2 a6iw1 a6iw0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? a5iw2 a5iw1 a5iw0 ? a4iw2 a4iw1 a4iw0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit: 15 14 13 12 11 10 9 8 ? a3iw2 a3iw1 a3iw0 ? a2iw2 a2iw1 a2iw0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? a1iw2 a1iw1 a1iw0 ? a0iw2 a0iw1 a0iw0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 389 of 1076 sep 24, 2013 bits 31, 27, 23, 19, 15, 11, 7, and 3?reserved: these bits are always read as 0, and should only be written with 0. bits 30 to 28? dmaiw-dack device in ter-cycle idle specification (dmaiw2? dmaiw0): these bits specify the number of idle cycl es between bus cycles to be inserted when switching from a dack device to another space, or from a read access to a write access on the same device. the dmaiw bits are valid only for dma single address transfer; with dma dual address transfer, inter-area idle cycles are inserted. bits 4n + 2 to 4n?area n (6 to 0) inte r-cycle idle specification (anlw2?anlw0): these bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n (n = 6 to 0) to another sp ace, or from a read access to a write access in the same space. dmaiw2/aniw2 dmaiw1/aniw1 dmai w0/aniw0 inserted idle cycles 0 0 0 0 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 (initial value)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 390 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? idle insertion between accesses following cycle same area different area same area different area read write read write preceding cycle cpu dma cpu dma cpu dma cpu dma mpx address output mpx address output read m m m m m m m (1) m (1) write m m m m * 2 m dma read (memory device) m m m m m m ? m (1) dma write (device memory) d d d d * 1 d d d d ? d (1) ?dma? in the table indicates dma single-address tr ansfer. dma dual transfer is in accordance with the cpu. legend: m, d: idle wait always inserted by wcr1 (m(1): one cycle inserted in mpx access even if wcr1 is cleared to 0) m: idle cycles according to setting of aniw2-aniw0 (area 0 to area 6) d: idle cycles according to setting of dmaiw2-dmaiw0 notes: when synchronous dram is used in ras down mode, set bits dmaiw2-dmaiw0 to 000 and bits a3iw2-a3iw0 to 000. 1. inserted when device is switched 2. on the mpx interface, a wcr1 idle wait may be inserted before an access (either read or write) to the same area after a write a ccess. the specific conditions for idle wait insertion in accesses to the same area are shown below. (a) synchronous dram set to ras down mode (b) synchronous dram accessed by on-chip dmac apart from use under above conditions (a) and (b), an idle wait is also inserted between an mpx interface write access and a following access to the same area. even under the above conditions, an idle wait may be inserted in a same-area access following an interface write access, depending on the syn chronous dram pipeline access situation. an idle wait is not inserted when the wcr1 register setting is 0. the setting for the number of idle state cycles inserted after a power-on reset is the default value of 15 (the maximum value), so ensure that the optimum value is set.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 391 of 1076 sep 24, 2013 13.2.6 wait control register 2 (wcr2) wait control register 2 (wcr2) is a 32-bit readab le/writable register that specifies the number of wait states to be inserted for each area. it al so specifies the data acce ss pitch when performing burst memory access. this enables low-speed memo ry to be connected without using external circuitry. wcr2 is initialized to h'fffeefff by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 31 30 29 28 27 26 25 24 a6w2 a6w1 a6w0 a6b2 a6b1 a6b0 a5w2 a5w1 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 a5w0 a5b2 a5b1 a5b0 a4w2 a4w1 a4w0 ? initial value: 1 1 1 1 1 1 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r bit: 15 14 13 12 11 10 9 8 a3w2 a3w1 a3w0 ? a2 w2 a2w1 a2w0 a1w2 initial value: 1 1 1 0 1 1 1 1 r/w: r/w r/w r/w r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a1w1 a1w0 a0w2 a0w1 a0w0 a0b2 a0b1 a0b0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 392 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 31 to 29?area 6 wait control (a6w2?a6w0): these bits specify the number of wait states to be inserted for area 6. for details on mpx interface setting, s ee table 13.6, mpx interface is selected (areas 0 to 6). description first cycle bit 31: a6w2 bit 30: a6w1 bit 29: a6w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled bits 28 to 26?area 6 burst pitch (a6b2?a6b0): these bits specify the number of wait states to be inserted from the second data access onward in a burst transfer with the burst rom interface selected. description burst cycle (excluding first cycle) bit 28: a6b2 bit 27: a6b1 bit 26: a6b0 wait states inserted from second data access onward rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 4 enabled 1 5 enabled 1 0 6 enabled 1 7 (initial value) enabled
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 393 of 1076 sep 24, 2013 bits 25 to 23?area 5 wait control (a5w2?a5w0): these bits specify the number of wait states to be inserted for area 5. for details on mpx interface setting, s ee table 13.6, mpx interface is selected (areas 0 to 6). description first cycle bit 25: a5w2 bit 24: a5w1 bit 23: a5w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled bits 22 to 20?area 5 burst pitch (a5b2?a5b0): these bits specify the number of wait states to be inserted from the second data access onward in a burst transfer with the burst rom interface selected. description burst cycle (excluding first cycle) bit 22: a5b2 bit 21: a5b1 bit 20: a5b0 wait states inserted from second data access onward rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 4 enabled 1 5 enabled 1 0 6 enabled 1 7 (initial value) enabled
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 394 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 19 to 17?area 4 wait control (a4w2?a4w0): these bits specify the number of wait states to be inserted for area 4. for details on mpx interface setting, s ee table 13.6, mpx interface is selected (areas 0 to 6). description bit 19: a4w2 bit 18: a4w1 bit 17: a4w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled bits 16 and 12?reserved: these bits are always read as 0, and should only be written with 0. bits 15 to 13?area 3 wait control (a3w2?a3w0): these bits specify the number of wait states to be inserted for area 3. external wait input is only enabled when sram interface or mpx interface is used, and is ignored when dram or synchronous dram is us ed. for details on mpx interface setting, see table 13.6, mpx in terface is selected (areas 0 to 6). ? when sram interface is set description bit 15: a3w2 bit 14: a3w1 bit 13: a3w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 395 of 1076 sep 24, 2013 ? when dram or synchronous dram interface is set* 1 description bit 15: a3w2 bit 14: a3w1 bit 13: a3w0 dram cas assertion width synchronous dram cas latency cycles 0 0 0 1 inhibited 1 2 1 * 2 1 0 3 2 1 4 3 1 0 0 7 4 * 2 1 10 5 * 2 1 0 13 inhibited 1 16 inhibited notes: 1. external wait input is always ignored. 2. inhibited in ras down mode. bits 11 to 9?area 2 wait control (a2w2?a2w0): these bits specify the number of wait states to be inserted for area 2. external wait input is only enabled when the sram interface or mpx interface is used, and is ignored when dram or synchronous dram is us ed. for details on mpx interface setting, see table 13.6, mpx in terface is selected (areas 0 to 6). ? when sram interface is set description bit 11: a2w2 bit 10: a2w1 bit 9: a2w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 396 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? when dram or synchronous dram interface is set* 1 description bit 11: a2w2 bit 10: a2w1 bit 9: a2w0 dram cas assertion width synchronous dram cas latency cycles 0 0 0 1 inhibited 1 2 1 * 2 1 0 3 2 1 4 3 1 0 0 7 4 * 2 1 10 5 * 2 1 0 13 inhibited 1 16 inhibited notes: 1. external wait input is always ignored. 2. ras down mode is prohibited. bits 8 to 6?area 1 wait control (a1w2?a1w0): these bits specify the number of wait states to be inserted for area 1. for details on mpx interface setting, see table 13.6, mpx interface is selected (areas 0 to 6). description bit 8: a1w2 bit 7: a1w1 bit 6: a1w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 397 of 1076 sep 24, 2013 bits 5 to 3?area 0 wait control (a0w2 to a0w0): these bits specify th e number of wait states to be inserted for area 0. for details on mpx interface setting, s ee table 13.6, mpx interface is selected (areas 0 to 6). description first cycle bit 5: a0w2 bit 4: a0w1 bit 3: a0w0 inserted wait states rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 6 enabled 1 9 enabled 1 0 12 enabled 1 15 (initial value) enabled bits 2 to 0?area 0 burst pitch (a0b2?a0b0): these bits specify the nu mber of wait states to be inserted afterwards the second data access in a burst transfer with the burst rom interface selected. description burst cycle (excluding first cycle) bit 2: a0b2 bit 1: a0b1 bit 0: a0b0 wait states inserted from second data access onward rdy pin 0 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1 0 0 4 enabled 1 5 enabled 1 0 6 enabled 1 7 (initial value) enabled
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 398 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.6 mpx interface is selected (areas 0 to 6) description inserted wait states 1st data anw2 anw1 anw0 read write 2nd data onward rdy pin 0 0 0 1 0 0 enabled 1 1 enabled 1 0 2 2 enabled 1 3 3 enabled 1 0 0 1 0 1 enabled 1 1 enabled 1 0 2 2 enabled 1 3 3 enabled note: n = 6 to 0
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 399 of 1076 sep 24, 2013 13.2.7 wait control register 3 (wcr3) wait control register 3 (wcr3) is a 32-bit readab le/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area. this enables low-speed memory to be connected without using external circuitry. wcr3 is initialized to h'07777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? a6s0 a6h1 a6h0 initial value: 0 0 0 0 0 1 1 1 r/w: r r r r r r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? a5s0 a5h1 a5h0 a4rdh * a4s0 a4h1 a4h0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r/w * r/w r/w r/w bit: 15 14 13 12 11 10 9 8 ? a3s0 a3h1 a3h0 ? a2s0 a2h1 a2h0 initial value: 0 1 1 1 0 1 1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a1rdh * a1s0 a1h1 a0h0 ? a0s0 a0h1 a0h0 initial value: 0 1 1 1 0 1 1 1 r/w: r/w * r/w r/w r/w r r/w r/w r/w note: * SH7750r only bits 31 to 27, 23, 19*, 15, 11, 7*, and 3?reserved: these bits are always read as 0, and should only be written with 0. note: * SH7750r only
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 400 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 4n + 2?area n (6 to 0) write strobe setup time (ans0): specifies the nu mber of cycles inserted in the setup time from the address until assertion of the read/write strobe. valid only for sram interface, byte control sram interface, and burst rom interface. bit 4n + 2: ans0 waits inserted in setup 0 0 1 1 (initial value) note: n = 6 to 0 bits 4n + 1 and 4n?area n (6 to 0) data hold time (anh1, anh0): when writing, these bits specify the number of cycles to be inserted in the hold time from negation of the write strobe. when reading, they specify the nu mber of cycles to be inserted in the hold time from the data sampling timing. valid only for sram interface, byte control sram interface, and burst rom interface. bit 4n + 1: anh1 bit 4n: anh0 waits inserted in hold 0 0 0 1 1 1 0 2 1 3 (initial value) note: n = 6 to 0 bits 4n+3 ? area n (4 or 1) read-strobe negate timi ng (anrdh) (setting only possible in the SH7750r): when reading, these bits specify the timing for the negation of read strobe. these bits should be cleared to 0 when a byte control sram setting is made. valid only for the sram interface. bit 4n + 3: anrdh read-strobe negate timing 0 read strobe negated after hold wait cycles specified by wcr3.anh bits (initial value) 1 read strobe negated according to data sampling timing note: n = 4 or 1
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 401 of 1076 sep 24, 2013 13.2.8 memory control register (mcr) the memory control register (mcr) is a 32-bit readable/writable register that specifies ras and cas timing and burst control for dram and synchronous dram (areas 2 and 3), address multiplexing, and refresh control. this enables dram and synchronous dram to be connected without using external circuitry. mcr is initialized to h'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bits rasd, mrset, trc2?0, tpc2?0, rcd1?0, trwl2?0, tras2?0, be, sz1?0, amxext, amx2?0, and edomode are written in the initialization following a power- on reset, and should not be modified subsequently. when writing to bits rfsh and rmode, the same values should be written to the other bits so that they remain unchanged. when using dram or synchronous dram, areas 2 and 3 should not be accessed until register initialization is completed. bit: 31 30 29 28 27 26 25 24 rasd mrset trc2 trc1 trc0 ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r r r bit: 23 22 21 20 19 18 17 16 tcas ? tpc2 tpc1 tpc0 ? rcd1 rcd0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r/w r/w r/w r r/w r/w bit: 15 14 13 12 11 10 9 8 trwl2 trwl1 trwl0 tras2 tras1 tras0 be sz1 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 sz0 amxext amx2 amx1 amx0 rfsh rmode edo mode initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 402 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 31?ras down (rasd): sets ras down mode. when dram/ras down mode is used, set be to 1. do not set ras down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both designated as synchronous dram in terface. see connecting a 128-mbit/256-mbit synchronous dram with 64-bit bus width (SH7750r only): in section 13.3.5, synchronous dram interface. bit 31: rasd description 0 auto-precharge mode (initial value) 1 ras down mode note: when synchronous dram is used in ras down mode, set bits dmaiw2?dmaiw0 to 000 and bits a3iw2?a3iw0 to 000. bit 30?mode regi ster set (mrset): set when a synchronous dram mode register setting is used. see power-on sequence in sectio n 13.3.5, synchronous dram interface. bit 30: mrset description 0 all-bank precharge (initial value) 1 mode register setting bits 29 to 27?ras precharge time at end of refresh (trc2?trc0) (synchronous dram: auto- and self-refresh both enabled; dram: auto- and self-refresh both enabled) note: for setting values and the period during which no command is issued, see 22.3.3, bus timing. bit 29: trc2 bit 28: trc1 bit 27: trc0 ras precharge interval immediately after refresh 0 0 0 0 (initial value) 1 3 1 0 6 1 9 1 0 0 12 1 15 1 0 18 1 21
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 403 of 1076 sep 24, 2013 bits 26 to 24, 22, and 18?reserved: these bits are always read as 0, and should only be written with 0. bit 23?cas negation period (tcas): this bit is valid only when dram interface is set. bit 23: tcas cas negation period 0 1 (initial value) 1 2 bits 21 to 19?ras precharge period (tpc2?tpc0): when the dram interface is selected, these bits specify the mini mum number of cycles until ras is asserted again after being negated. when the synchronous dram interface is select ed, these bits specify the minimum number of cycles until the next bank active command after precharging. note: for setting values and the period during which no command is issued, see 22.3.3, bus timing. ras precharge interval bit 21: tpc2 bit 20: tpc1 bit 19: tpc0 dram synchronous dram 0 0 0 0 1 * (initial value) 1 1 2 1 0 2 3 1 3 4 * 1 0 0 4 5 * 1 5 6 * 1 0 6 7 * 1 7 8 * note: * inhibited in ras down mode.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 404 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 17 and 16?ras-cas delay (rcd1, rcd0): when the dram interface is set, these bits set the ras - cas assertion delay time. when the synchrono us dram interface is set, these bits set the bank active-read/write command delay time. description bit 17: rcd1 bit 16: rcd0 dram synchronous dram 0 0 2 cycles reserved (setting prohibited) 1 3 cycles 2 cycles 1 0 4 cycles 3 cycles 1 5 cycles 4 cycles * note: * inhibited in ras down mode. bits 15 to 13?write precharge delay (trwl2?trwl0): these bits set the synchronous dram write precharge delay time. in auto-precharge mode, they specify the time until the next bank active command is issued afte r a write cycle. after a write cy cle, the next active command is not issued for a period equivalent to the setting values of the tpc[2:0] and trwl[2:0] bits.* after a write cycle, the next precharge command is not issued for a period of trwl. this setting is valid only when synchron ous dram interface is set. note: * for setting values and the period during which no command is issued, see 22.3.3, bus timing. bit 15: trwl2 bit 14: trwl1 bit 13: tr wl0 write precharge act delay time 0 0 0 1 (initial value) 1 2 1 0 3 * 1 4 * 1 0 0 5 * 1 reserved (setting prohibited) 1 0 reserved (setting prohibited) 1 reserved (setting prohibited) note: * inhibited in ras down mode.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 405 of 1076 sep 24, 2013 bits 12 to 10?cas-before-ras refresh ras assertion period (tras2?tras0): when the dram interface is set, these bits set the ras assertion period in cas-before-ras refreshing. when the synchronous dram interface is set, the bank active command is not issued for the period set by the trc[2:0]* and tras[2:0] bits after an auto-refresh command is issued. note: for setting values and the period during which no command is issued, see 22.3.3, bus timing. bit 12: tras2 bit 11: tras1 bit 10: tras0 ras /dram assertion period command interval after synchronous dram refresh 0 0 0 2 4 + trc (initial value) 1 3 5 + trc 1 0 4 6 + trc 1 5 7 + trc 1 0 0 6 8 + trc 1 7 9 + trc 1 0 8 10 + trc 1 9 11 + trc note: trc (bits 29 to 27): ras precharge interval at end of refresh. bit 9?burst enable (be): specifies whether burst access is pe rformed on dram interface. in synchronous dram access, burst access is always performed regardless of the specification of this bit. the dram transfer mode depends on edomode. be edomode 8/16/32/64-bit transfer 32-byte transfer 0 0 single single 1 setting prohibited setting prohibited 1 0 single/fast page * fast page 1 edo edo note: * in fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 406 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 8 and 7?memory data size (sz1, sz0): these bits specify the bus width of dram and synchronous dram. this setting has priority over the bcr2 register setting. description bit 8: sz1 bit 7: sz0 dram sdram 0 0 64 bits 64 bits 1 reserved (setting prohibited) reserved (setting prohibited) 1 0 16 bits reserved (setting prohibited) 1 32 bits 32 bits bits 6 to 3?address multiple xing (amxext, amx2?amx0): these bits specify address multiplexing for dram and synchronous dram. th e address shift value is different for the dram interface and the synchronous dram interface. ? for dram interface: description bit 6: amxext bit 5: amx2 bit 4: amx1 bit 3: amx0 dram 0 * 0 0 0 8-bit column address product (initial value) 1 9-bit column address product 1 0 10-bit column address product 1 11-bit column address product 1 0 0 12-bit column address product 1 reserved (setting prohibited) 1 0 reserved (setting prohibited) 1 reserved (setting prohibited) note: * when the dram interface is used, clear the amxext bit to 0.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 407 of 1076 sep 24, 2013 ? for synchronous dram interface: amx amxext sz example of synchronous dram bank * 4 0 0 64 (16m: 512k 16 bits 2) 4 a[22] * 1 32 (16m: 512k 16 bits 2) 2 a[21] * 1 1 64 (16m: 512k 16 bits 2) 4 a[21] * 1 32 (16m: 512k 16 bits 2) 2 a[20] * 1 1 0 64 (16m: 1m 8 bits 2) 8 a[23] * 1 32 (16m: 1m 8 bits 2) 4 a[22] * 1 1 64 (16m: 1m 8 bits 2) 8 a[22] * 1 32 (16m: 1m 8 bits 2) 4 a[21] * 1 2 ? 64 (64m: 1m 16 bits 4) 4 a[24:23] * 1 32 (64m: 1m 16 bits 4) 2 a[23:22] * 1 3 ? 64 (64m: 2m 8 bits 4) 8 a[25:24] * 1 32 (64m: 2m 8 bits 4) 4 a[24:23] * 1 4 ? 64 (64m: 512k 32 bits 4) 2 a[23:22] * 1 32 (64m: 512k 32 bits 4) 1 a[22:21] * 1 5 ? 64 (64m: 1m 32 bits 2) 2 a[23] * 1 32 (64m: 1m 32 bits 2) 1 a[22] * 1 6 0 64 (128m: 4m 8 bits 4) 8 * 2 a[26:25] * 1 1 64 (256m: 4m 16 bits 4) 4 * 2 a[26:25] * 1 0 32 (128m: 4m 8 bits 4) 4 * 3 a[25:24] * 1 1 32 (256m: 4m 16 bits 4) 2 * 3 a[25:24] * 1 7 ? 64 (16m: 256k 32 bits 2) 2 a[21] * 1 32 (16m: 256k 32 bits 2) 1 a[20] * 1 notes: 1. a[* ] : not an address pin but an external address 2. can only be set in the SH7750r. 3. can only be set in the SH7750s/SH7750r (setting prohibited in the SH7750). 4. for details on address multiplexing, re fer to appendix f, synchronous dram address multiplexing tables.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 408 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 2?refresh control (rfsh): specifies refresh control. selects whether refreshing is performed for dram and synchronous dram. when the refresh function is not used, the refresh request cycle generation timer can be used as an interval timer. bit 2: rfsh description 0 refreshing is not performed (initial value) 1 refreshing is performed bit 1?refresh mode (rmode): specifies whether normal refres hing or self-refreshing is performed when the rfsh bit is set to 1. when the rfsh bit is 1 and this bit is cleared to 0, cas- before-ras refreshing or auto-refreshing is performed for dram and synchronous dram, using the cycle set by refresh-related registers rtcnt, rtcor, and rt csr. if a refresh request is issued during an external bus cycl e, the refresh cycle is executed when the bus cycle ends. when the rfsh bit is 1 and this bit is set to 1, the self-refresh state is set for dram and synchronous dram, after waiting for the end of any currently executing external bus cycle. all refresh requests for memory in the self-refresh state are ignored. bit 1: rmode description 0 cas-before-ras refreshing is performed (when rfsh = 1) (initial value) 1 self-refreshing is performed (when rfsh = 1) bit 0?edo mode (edomode): used to specify the data sampling timing for data reads when using edo mode dram interface. the setting of this bit does not affect the operation timing of memory other than dram. set this bit to 1 only when dram is used.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 409 of 1076 sep 24, 2013 13.2.9 pcmcia control register (pcr) the pcmcia control register (pcr) is a 16-bit readable/writable regist er that specifies the oe and we signal assertion/negation tim ing for the pcmcia interface co nnected to areas 5 and 6. the oe and we signal assertion width is set by the wait control bits in the wcr2 register. for details of access to pcmcia, see s ection 13.3.7, pc mcia interface. pcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 a5pcw1 a5pcw0 a6pcw1 a6pcw0 a5ted2 a5ted1 a5ted0 a6ted2 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a6ted1 a6ted0 a5teh2 a5teh1 a5teh0 a6teh2 a6teh1 a6teh0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14?pcmcia wait (a5pcw1, a5pcw0): these bits specify the number of waits to be added to the number of waits specified by wcr2 in a low-speed pcmcia wait cycle. the setting of these bits is selected when the pc mcia interface access tc bit is cleared to 0. bit 15: a5pcw1 bit 14: a5pcw0 waits inserted 0 0 0 (initial value) 1 15 1 0 30 1 50
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 410 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 13 and 12?pcmcia wait (a6pcw1, a6pcw0): these bits specify the number of waits to be added to the number of waits specified by wcr2 in a low-speed pc mcia wait cycle. the setting of these bits is selected when the pcmcia interface access tc bit is set to 1. bit 13: a6pcw1 bit 12: a6pcw0 waits inserted 0 0 0 (initial value) 1 15 1 0 30 1 50 bits 11 to 9?address- oe / we assertion delay (a5ted2?a5ted0): these bits set the delay time from address output to oe / we assertion on the connected pc mcia interface. the setting of these bits is selected when the pcmcia interface access tc bit is cleared to 0. bit 11: a5ted2 bit 10: a5ted1 bit 9: a5ted0 waits inserted 0 0 0 0 (initial value) 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 411 of 1076 sep 24, 2013 bits 8 to 6?address- oe / we assertion delay (a6ted2?a6ted0): these bits set the delay time from address output to oe / we assertion on the connected pc mcia interface. the setting of these bits is selected when the pcmc ia interface access tc bit is set to 1. bit 8: a6ted2 bit 7: a6ted1 bit 6: a6ted0 waits inserted 0 0 0 0 (initial value) 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 bits 5 to 3? oe / we negation-address delay (a5teh2?a5teh0): these bits set the address hold delay time from oe / we negation in a write on the connect ed pcmcia interface or in an i/o card read. the setting of these bits is selected wh en the pcmcia interface access tc bit is cleared to 0. bit 5: a5teh2 bit 4: a5teh1 bit 3: a5teh0 waits inserted 0 0 0 0 (initial value) 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 412 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 2 to 0? oe / we negation-address delay (a6teh2?a6teh0): these bits set the address hold delay time from oe / we negation in a write on the connect ed pcmcia interface or in an i/o card read. in the case of a memory card read, th e address hold delay time from the data sampling timing is set. the setting of these bits is select ed when the pcmcia interface access tc bit is set to 1. bit 2: a6teh2 bit 1: a6teh1 bit 0: a6teh0 waits inserted 0 0 0 0 (initial value) 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 413 of 1076 sep 24, 2013 13.2.10 synchronous dram mode register (sdmr) the synchronous dram mode register (sdmr) is a write-only virtual 16-bit register that is written to via the synchronous dram address bu s, and sets the mode of the area 2 and area 3 synchronous dram. settings for the sdmr register must be made before accessing synchronous dram. bit: 15 14 13 12 11 10 9 8 initial value: ? ? ? ? ? ? ? ? r/w: w w w w w w w w bit: 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? r/w: w w w w w w w w since the address bus, not the data bus, is used to write to the synchronous dram mode register, if the value to be set is ?x? and the sdmr regist er address is ?y?, valu e ?x? is written to the synchronous dram mode register by performing a write to address x + y. when the synchronous dram bus width is set to 32 bits, as a0 of the synchronous dram is connected to a2 of this lsi, and a1 of the synchronous dram is connected to a3 of this lsi, the value actually written to the synchronous dram is the value of ?x? shifted 2 bits to the right. for example, to write h'0230 to the area 2 sdmr register, arbitrary data is written to address h'ff900000 (address ?y?) + h'08c0 (value ?x?) (= h'ff9008c0). as a result, h'0230 is written to the sdmr register. the range of value ?x? is h'0000 to h'0ffc. similarly, to write h'0230 to the area 3 sdmr register, arbitrary data is written to address h'ff940000 (address ?y?) + h'08c0 (value ?x?) (= h'ff9408c0). as a result, h'0230 is written to the sdmr register. the range of value ?x? is h'0000 to h'0ffc. the lower 16 bits of the address are set in the synchronous dram mode register. when the bus width is 32 bits, the burst length is 4* and 8. when the bus width is 64 bits, the burst length is fixed at 4. when a setting is made in sdmr, byte-size writes are performed at the following addresses.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 414 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bus width burst length cas latency area 2 area 3 32 4 * 1 2 3 h'ff900048 h'ff900088 h'ff9000c8 h'ff940048 h'ff940088 h'ff9400c8 32 8 1 2 3 h'ff90004c h'ff90008c h'ff9000cc h'ff94004c h'ff94008c h'ff9400cc 64 4 1 2 3 h'ff900090 h'ff900110 h'ff900190 h'ff940090 h'ff940110 h'ff940190 for a 32-bit bus: 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address 0 0 0 0 0 0 0 0 0 lmo de2 lmo de1 lmo de0 wt bl2 bl1 bl0 ??????????????????? 10 bits set in case of 32-bit bus width for a 64-bit bus: 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address 0 0 0 0 0 0 0 0 lmo de2 lmo de1 lmo de0 wt bl2 bl1 bl0 ??????????????????? 10 bits set in case of 64-bit bus width lmode: cas latency bl: burst length wt: wrap type (0: sequential)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 415 of 1076 sep 24, 2013 bl lmode 000: reserved 000: reserved 001: reserved 001: 1 010: 4 010: 2 011: 8 011: 3 100: reserved 100: reserved 101: reserved 101: reserved 110: reserved 110: reserved 111: reserved 111: reserved note: * SH7750r only. 13.2.11 refresh timer control/st atus register (rtcsr) the refresh timer control/status re gister (rtcsr) is a 16-bit re adable/writable register that specifies the refresh cycle and whether interrupts are to be generated. rtcsr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? ? ? bit: 7 6 5 4 3 2 1 0 cmf cmie cks2 cks1 cks0 ovf ovie lmts initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?reserved: these bits are always read as 0. for the write values, see section 13.2.15, notes on accessing refresh control registers.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 416 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 7?compare-match flag (cmf): status flag that indicates a match between the refresh timer counter (rtcnt) and refresh time constant register (rtcor) values. bit 7: cmf description 0 rtcnt and rtcor values do not match (initial value) [clearing condition] when 0 is written to cmf 1 rtcnt and rtcor values match [setting condition] when rtcnt = rtcor * note: * if 1 is written, the original value is retained. bit 6?compare-match interrupt enable (cmie): controls generation or suppression of an interrupt request when the cmf flag is set to 1 in rtcsr. do not set this bit to 1 when cas- before-ras refreshing or auto-refreshing is used. bit 6: cmie description 0 interrupt requests initiated by cmf are disabled (initial value) 1 interrupt requests initiated by cmf are enabled bits 5 to 3?clock select bits (cks2?cks0): these bits select the input clock for rtcnt. the base clock is the external bus clock (ckio). the rtcnt count clock is obtained by scaling ckio by the specified factor. bit 5: cks2 bit 4: cks1 bit 3: cks0 description 0 0 0 clock input disabled (initial value) 1 bus clock (ckio)/4 1 0 ckio/16 1 ckio/64 1 0 0 ckio/256 1 ckio/1024 1 0 ckio/2048 1 ckio/4096
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 417 of 1076 sep 24, 2013 bit 2?refresh count overflow flag (ovf): status flag that indicat es that the number of refresh requests indicated by th e refresh count register (rfcr) has exceeded the number specified by the lmts bit in rtcsr. bit 2: ovf description 0 rfcr has not overflowed t he count limit indicated by lmts (initial value) [clearing condition] when 0 is written to ovf 1 rfcr has overflowed the count limit indicated by lmts [setting condition] when rfcr overflows the count limit set by lmts * note: * if 1 is written, the original value is retained. bit 1?refresh count overflow interrupt en able (ovie): controls generation or suppression of an interrupt request when the ovf flag is set to 1 in rtcsr. bit 1: ovie description 0 interrupt requests initiated by ovf are disabled (initial value) 1 interrupt requests initiated by ovf are enabled bit 0?refresh count overflow limit select (lmts): specifies the count li mit to be compared with the refresh count indicated by the refresh co unt register (rfcr). if the rfcr register value exceeds the value specified by lm ts, the ovf flag is set. bit 0: lmts description 0 count limit is 1024 (initial value) 1 count limit is 512
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 418 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.2.12 refresh timer counter (rtcnt) the refresh timer counter (rtcnt) is an 8-bit re adable/writable counter that is incremented by the input clock (selected by bits cks2?cks0 in the rtcsr register). when the rtcnt counter value matches the rtcor register value, the cm f bit is set in the rtcsr register and the rtcnt counter is cleared. rtcnt is initialized to h'0000 by a power-on reset, but continues to count when a manual reset is performed. in standby mode, rtcnt is not initialized, and retains its contents. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? ? ? bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 419 of 1076 sep 24, 2013 13.2.13 refresh time constant register (rtcor) the refresh time constant register (rtcor) is a readable/writable re gister that specifies the upper limit of the rtcnt counter. the rtcor register and rtcnt counter values (lower 8 bits) are constantly compared, and when they match the cmf bit is set in the rtcsr register and the rtcnt counter is cleared to 0. if the refresh bit (rfsh) has been set to 1 in the memory control register (mcr) and cas-before-ras has been se lected as the refresh mode, a memory refresh cycle is generated when the cmf bit is set. rtcor is initialized to h'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? ? ? bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 420 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.2.14 refresh count register (rfcr) the refresh count register (rfcr) is a 10-bit read able/writable counter that counts the number of refreshes by being incremented each time the rtcor register and rtcnt counter values match. if the rfcr register value exceeds the count lim it specified by the lmts bit in the rtcsr register, the ovf flag is set in the rtcsr register and the rfcr register is cleared. rfcr is initialized to h'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 13.2.15 notes on accessing refresh control registers when the refresh timer control/status register (rtcsr), refresh timer counter (rtcnt), refresh time constant register (rtcor), and refresh count register (rfcr) are written to, a special code is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. the following procedures should be used for read/write operations. writing to rtcsr, rtcnt, rtcor, and rfcr: a word transfer instruction must always be used when writing to rtcsr, rtcnt, rtcor, or rfcr. a write cannot be performed with a byte transfer instruction. when writing to rtcsr, rtcnt, or rtcor, set b'10100101 in the upper byte and the write data in the lower byte, as shown in figure 13.5. when writing to rfcr, set b'101001 in the 6 bits starting from the msb in the upper byte, and the write data in the remaining bits.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 421 of 1076 sep 24, 2013 15 14 13 12 11 10 9 8 10 100 101 76543210 15 14 13 12 11 10 9 8 10 100 1 76543210 write data write data rtcsr, rtcnt, rtcor rfcr figure 13.5 writing to rtcsr, rtcnt, rtcor, and rfcr reading rtcsr, rtcnt, rtcor, and rfcr: a 16-bit access must always be used when reading rtcsr, rtcnt, rtcor, or rf cr. undefined bits are read as 0. 13.3 operation 13.3.1 endian/access size and data alignment this lsi supports both big-endian mode, in which the most significant byte (msbyte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (lsbyte) is at the 0 address end. the mode is se t by means of the md5 external pin in a power-on reset by the reset pin, big-endian mode being set if the md5 pin is low, and little-endian mode if it is high. a data bus width of 8, 16, 32, or 64 bits can be selected for normal memory, 16, 32, or 64 bits for dram, 32 or 64 bits for synchronous dram, and 8 or 16 bits for the pcmcia interface. data alignment is carried out according to the data bu s width and endian mode of each device. if the data bus width is smaller than the access size, a number of bus cycles will be generated automatically until the access size is reached. in this case, addr ess incrementing is performed automatically according to the bus width as acce ss is performed. for exam ple, if longword access is performed in an 8-bit bus width area using the sram interface, four accesses are executed, with the address automatically incremented by 1 eac h time. in 32-byte transfer, a total of 32 bytes of data are transferred consecutively according to the set bus width. the first access is performed on the data for which there was an access reques t, and the remaining accesses are performed on 32-byte boundary data using wraparound. bus release or refresh operations are not performed between these transfers. data alignment and data length conversion between the different interfaces is performed automatically. quadword access is used only in transfer by the dmac. the relationship between the endian mode, device data length, and access unit, is shown in tables 13.7 to 13.14.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 422 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 data configuration msb lsb byte data 7 to 0 msb lsb word data 15 to 8 data 7 to 0 msb lsb longword data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 msb lsb quadword data 63 to 56 data 55 to 48 data 47 to 40 data 39 to 32 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 423 of 1076 sep 24, 2013 table 13.7 (1) 64-bit external devi ce/big-endian access and data alignment operation data bus acces s size address no. d63?56 d55?48 d47?40 d39?32 d31?24 d23?16 d15?8 d7?0 byte 8n 1 data 7?0 ? ? ? ? ? ? ? 8n + 1 1 ? data 7?0 ? ? ? ? ? ? 8n + 2 1 ? ? data 7?0 ? ? ? ? ? 8n + 3 1 ? ? ? data 7?0 ? ? ? ? 8n + 4 1 ? ? ? ? data 7?0 ? ? ? 8n + 5 1 ? ? ? ? ? data 7?0 ? ? 8n + 6 1 ? ? ? ? ? ? data 7?0 ? 8n + 7 1 ? ? ? ? ? ? ? data 7?0 word 8n 1 data 15?8 data 7?0 ? ? ? ? ? ? 8n + 2 1 ? ? data 15?8 data 7?0 ? ? ? ? 8n + 4 1 ? ? ? ? data 15?8 data 7?0 ? ? 8n + 6 1 ? ? ? ? ? ? data 15?8 data 7?0 long- word 8n 1 data 31?24 data 23?16 data 15?8 data 7?0 ? ? ? ? 8n + 4 1 ? ? ? ? data 31?24 data 23?16 data 15?8 data 7?0 quad- word 8n 1 data 63?56 data 55?48 data 47?40 data 39?32 data 31?24 data 23?16 data 15?8 data 7?0
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 424 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.7 (2) 64-bit external devi ce/big-endian access and data alignment operation strobe signals access size address no. we7 , cas7 , dqm7 we6 , cas6 , dqm6 we5 , cas5 , dqm5 we4 , cas4 , dqm4 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 8n 1 asserted 8n + 1 1 asserted 8n + 2 1 asserted 8n + 3 1 asserted 8n + 4 1 asserted 8n + 5 1 asserted 8n + 6 1 asserted 8n + 7 1 asserted word 8n 1 asserted asserted 8n + 2 1 asserted asserted 8n + 4 1 asserted asserted 8n + 6 1 asserted asserted 8n 1 asserted asserted asserted asserted long- word 8n + 4 1 asserted asserted asserted asserted quad- word 8n 1 asserted asserted asserted assert ed asserted asserted asserted asserted
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 425 of 1076 sep 24, 2013 table 13.8 32-bit extern al device/big-e ndian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 4n 1 data 7?0 ? ? ? asserted 4n + 1 1 ? data 7?0 ? ? asserted 4n + 2 1 ? ? data 7?0 ? asserted 4n + 3 1 ? ? ? data 7?0 asserted word 4n 1 data 15?8 data 7?0 ? ? asserted asserted 4n + 2 1 ? ? data 15?8 data 7?0 asserted asserted long- word 4n 1 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted quad- word 8n 1 data 63?56 data 55?48 data 47?40 data 39?32 asserted asserted asserted asserted 8n + 4 2 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 426 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.9 16-bit extern al device/big-e ndian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 2n 1 ? ? data 7?0 ? asserted 2n + 1 1 ? ? ? data 7?0 asserted word 2n 1 ? ? data 15?8 data 7?0 asserted asserted long- word 4n 1 ? ? data 31?24 data 23?16 asserted asserted 4n + 2 2 ? ? data 15?8 data 7?0 asserted asserted quad- word 8n 1 ? ? data 63?56 data 55?48 asserted asserted 8n + 2 2 ? ? data 47?40 data 39?32 asserted asserted 8n + 4 3 ? ? data 31?24 data 23?16 asserted asserted 8n + 6 4 ? ? data 15?8 data 7?0 asserted asserted
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 427 of 1076 sep 24, 2013 table 13.10 8-bit external device/big-endian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte n 1 ? ? ? data 7?0 asserted word 2n 1 ? ? ? data 15?8 asserted 2n + 1 2 ? ? ? data 7?0 asserted long- word 4n 1 ? ? ? data 31?24 asserted 4n + 1 2 ? ? ? data 23?16 asserted 4n + 2 3 ? ? ? data 15?8 asserted 4n + 3 4 ? ? ? data 7?0 asserted quad- word 8n 1 ? ? ? data 63?56 asserted 8n + 1 2 ? ? ? data 55?48 asserted 8n + 2 3 ? ? ? data 47?40 asserted 8n + 3 4 ? ? ? data 39?32 asserted 8n + 4 5 ? ? ? data 31?24 asserted 8n + 5 6 ? ? ? data 23?16 asserted 8n + 6 7 ? ? ? data 15?8 asserted 8n + 7 8 ? ? ? data 7?0 asserted
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 428 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.11 (1) 64-bit external device/ little-endian access and data alignment operation data bus access size address no. d63?56 d55?48 d47?40 d39?32 d31?24 d23?16 d15?8 d7?0 byte 8n 1 ? ? ? ? ? ? ? data 7?0 8n + 1 1 ? ? ? ? ? ? data 7?0 ? 8n + 2 1 ? ? ? ? ? data 7?0 ? ? 8n + 3 1 ? ? ? ? data 7?0 ? ? ? 8n + 4 1 ? ? ? data 7?0 ? ? ? ? 8n + 5 1 ? ? data 7?0 ? ? ? ? ? 8n + 6 1 ? data 7?0 ? ? ? ? ? ? 8n + 7 1 data 7?0 ? ? ? ? ? ? ? word 8n 1 ? ? ? ? ? ? data 15?8 data 7?0 8n + 2 1 ? ? data 15?8 data 7?0 ? ? 8n + 4 1 ? ? data 15?8 data 7?0 ? ? ? ? 8n + 6 1 data 15?8 data 7?0 ? ? ? ? ? ? long- word 8n 1 ? ? ? ? data 31?24 data 23?16 data 15?8 data 7?0 8n + 4 1 data 31?24 data 23?16 data 15?8 data 7?0 ? ? ? ? quad- word 8n 1 data 63?56 data 55?48 data 47?40 data 39?32 data 31?24 data 23?16 data 15?8 data 7?0
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 429 of 1076 sep 24, 2013 table 13.11 (2) 64-bit external device/ little-endian access and data alignment operation strobe signals access size address no. we7 , cas7 , dqm7 we6 , cas6 , dqm6 we5 , cas5 , dqm5 we4 , cas4 , dqm4 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 8n 1 asserted 8n + 1 1 asserted 8n + 2 1 asserted 8n + 3 1 asserted 8n + 4 1 asserted 8n + 5 1 asserted 8n + 6 1 asserted 8n + 7 1 asserted word 8n 1 asserted asserted 8n + 2 1 asserted asserted 8n + 4 1 asserted asserted 8n + 6 1 asserted asserted 8n 1 asserted asserted asserted asserted long- word 8n + 4 1 asserted asserted asserted asserted quad- word 8n 1 asserted asserted asserted assert ed asserted asserted asserted asserted
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 430 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.12 32-bit external device/li ttle-endian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 4n 1 ? ? data 7?0 asserted 4n + 1 1 ? ? data 7?0 ? asserted 4n + 2 1 ? data 7?0 ? ? asserted 4n + 3 1 data 7?0 ? ? ? asserted word 4n 1 ? ? data 15?8 data 7?0 asserted asserted 4n + 2 1 data 15?8 data 7?0 ? ? asserted asserted long- word 4n 1 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted quad- word 8n 1 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted 8n + 4 2 data 63?56 data 55?48 data 47?40 data 39?32 asserted asserted asserted asserted
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 431 of 1076 sep 24, 2013 table 13.13 16-bit external device/li ttle-endian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte 2n 1 ? ? ? data 7?0 asserted 2n + 1 1 ? ? data 7?0 ? asserted word 2n 1 ? ? data 15?8 data 7?0 asserted asserted long- word 4n 1 ? ? data 15?8 data 7?0 asserted asserted 4n + 2 2 ? ? data 31?24 data 23?16 asserted asserted quad- word 8n 1 ? ? data 15?8 data 7?0 asserted asserted 8n + 2 2 ? ? data 31?24 data 23?16 asserted asserted 8n + 4 3 ? ? data 47?40 data 39?32 asserted asserted 8n + 6 4 ? ? data 63?56 data 55?48 asserted asserted
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 432 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.14 8-bit external device/little-e ndian access and data alignment operation data bus strobe signals access size address no. d31?d24 d23?d16 d15?d8 d7?d0 we3 , cas3 , dqm3 we2 , cas2 , dqm2 we1 , cas1 , dqm1 we0 , cas0 , dqm0 byte n 1 ? ? ? data 7?0 asserted word 2n 1 ? ? ? data 7?0 asserted 2n + 1 2 ? ? ? data 15?8 asserted long- word 4n 1 ? ? ? data 7?0 asserted 4n + 1 2 ? ? ? data 15?8 asserted 4n + 2 3 ? ? ? data 23?16 asserted 4n + 3 4 ? ? ? data 31?24 asserted quad- word 8n 1 ? ? ? data 7?0 asserted 8n + 1 2 ? ? ? data 15?8 asserted 8n + 2 3 ? ? ? data 23?16 asserted 8n + 3 4 ? ? ? data 31?24 asserted 8n + 4 5 ? ? ? data 39?32 asserted 8n + 5 6 ? ? ? data 47?40 asserted 8n + 6 7 ? ? ? data 55?48 asserted 8n + 7 8 ? ? ? data 63?56 asserted
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 433 of 1076 sep 24, 2013 13.3.2 areas area 0: for area 0, external addres s bits a28 to a26 are 000. sram, mpx, and burst rom can be set to this area. a bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins md4 and md3. for details, see memory bus width in section 13.1.5, overview of areas. when area 0 is accessed, the cs0 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we7 , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits a0w2 to a0w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). when the burst rom interface is used, the number of burst cycle transfer states is selected in the range 2 to 9 according to the number of waits. the read/write strobe signal address and the cs setup/hold time can be set, respectively, to 0 or 1 and to 0 to 3 cycles using the a0s0, a0h1, and a0h0 bits in the wcr3 register. area 1: for area 1, external addres s bits a28 to a26 are 001. sram, mpx and byte control sram can be set to this area. a bus width of 8, 16, 32, or 64 bits can be selected with bits a1sz1 and a1sz0 in the bcr2 register. when mpx interface is set, a bus width of 32 or 64 bits should be selected with bits a1sz1 and a1sz0 in the bcr2 register. when byte control sram interface is set, select a bus width of 16, 32, or 64 bits. when area 1 is accessed, the cs1 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we7 , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits a1w2 to a1w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a1s0 and bits a1h1 and a1h0 in the wcr3 register.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 434 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 area 2: for area 2, external addres s bits a28 to a26 are 010. sram, mpx, dram, and synchronous dram can be set to this area. when sram interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits a2sz1 and a2sz0 in the bcr2 register. wh en mpx interface is set, a bus wi dth of 32 or 64 bits should be selected with bits a2sz1 and a2sz0 in the bcr2 register. when synchronous dram interface is set, select 32 or 64 bits with the sz bits in the mcr register. when dram is connected to area 2, select a bus wi dth of 16 or 32 bits with the sz bits in mcr. for details, see memory bus width in section 13.1.5, overview of areas. when area 2 is accessed, the cs2 signal is asserted. when sram interface is set, the rd signal, which can be used as oe , and write control signals we0 to we7 , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits a2w2 to a2w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a2s0 and bits a2h1 and a2h0 in the wcr3 register. when synchronous dram interface is set, the ras and cas signals, rd/ wr signal, and byte control signals dqm0 to dqm7 are asserted, and address multiplexing is performed. ras , cas , and data timing control, and address multiplexing control, can be set using the mcr register. when dram is connected, the ras2 signal, cas4 to cas7 signals, and rd/ wr signal are asserted, and address multiplexing is performed. ras2 , cas , and data timing control, and address multiplexing control, can be set using the mcr register. area 3: for area 3, external addres s bits a28 to a26 are 011. sram, mpx, dram, and synchronous dram can be set to this area. when sram interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits a3sz1 and a3sz0 in the bcr2 register. wh en mpx interface is set, a bus wi dth of 32 or 64 bits should be selected with bits a3sz1 and a3sz0 in the bcr2 register. when dram interface is set, 16, 32, or 64 bits can be selected with the sz bits in the mcr register. when synchronous dram interface is set, select 32 or 64 bits with the sz bits in mcr. for details, see memory bus width in section 13.1.5, overview of areas.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 435 of 1076 sep 24, 2013 when area 3 is accessed, the cs3 signal is asserted. when sram interface is set, the rd signal, which can be used as oe , and write control signals we0 to we7 , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected wi th bits a3w2 to a3w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a3s0 and bits a3h1 and a3h0 in the wcr3 register. when synchronous dram interface is set, the ras and cas signals, rd/ wr signal, and byte control signals dqm0 to dqm7 are asserted, and address multiplexing is performed. when dram interface is set, the ras signal, cas0 to cas7 signals, and rd/ wr signal are asserted, and address multiplexing is performed. ras , cas , and data timing control, and address multiplexing control, can be set using the mcr register. area 4: for area 4, external addres s bits a28 to a26 are 100. sram, mpx, and byte control sram can be set to this area. a bus width of 8, 16, 32, or 64 bits can be selected with bits a4sz1 and a4sz0 in the bcr2 register. when mpx interface is set, a bus width of 32 or 64 bits should be selected with bits a4sz1 and a4sz0 in the bcr2 register. when byte control sram interface is set, select a bus width of 16, 32, or 64 bits. for details, see memory bus width in section 13.1.5, overview of areas. when area 4 is accessed, the cs4 signal is asserted, and the rd signal, which can be used as oe , and write control signals we0 to we7 , are also asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits a4w2 to a4w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a4s0 and bits a4h1 and a4h0 in the wcr3 register.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 436 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 area 5: for area 5, external addres s bits a28 to a26 are 101. sram, mpx, burst rom, and a pcmcia interface can be set to this area. when sram interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits a5sz1 and a5sz0 in the bcr2 register. when burst rom interf ace is set, a bus width of 8, 16 or 32 bits can be selected with bits a5sz1 and a5sz0 in bcr2. when mpx interface is set, a bus width of 32 or 64 bits should be sel ected with bits a5sz1 and a5sz0 in bcr2. when a pcmcia interface is set, either 8 or 16 bits should be selected with bits a5sz1 and a5sz0 in bcr2. for details, see memory bus width in section 13.1.5, overview of areas. when area 5 set is accessed with sram interface set, the cs5 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we7 , are asserted. when a pcmcia interface is connected, the ce1a and ce2a signals, the rd signal, which can be used as oe , and the we1 , we2 , we3 , and we7 signals, which can be used as we , iciord , iciowr , and reg , respectively, are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits a5w2 to a5w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). when the burst function is used, the number of bu rst cycle transfer states is determined in the range 2 to 9 according to the number of waits. the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a5s0 and bits a5h1 and a5h0 in the wcr3 register. when a pcmcia interface is used, the address/ ce1a / ce2a setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits anted1 and anted0, and bits anteh1 and anteh0, in the pcr register. in addition, the number of wait cycles can be set in the range 0 to 50 with bits anpcw1 and anpcw0. the number of waits set in pcr is added to the number of waits set in wcr2.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 437 of 1076 sep 24, 2013 area 6: for area 6, external addres s bits a28 to a26 are 110. sram, mpx, burst rom, and a pcmcia interface can be set to this area. when sram interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits a6sz1 and a6sz0 in the bcr2 register. when burst rom interf ace is set, a bus width of 8, 16 or 32 bits can be selected with bits a6sz1 and a6sz0 in bcr2. when mpx interface is set, a bus width of 32 or 64 bits should be sel ected with bits a6sz1 and a6sz0 in bcr2. when a pcmcia interface is set, either 8 or 16 bits should be selected with bits a6sz1 and a6sz0 in bcr2. for details, see memory bus width in section 13.1.5, overview of areas. when area 6 is accessed with sram interface set, the cs6 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we7 , are asserted. when a pcmcia interface is set, the ce1b and ce2b signals, the rd signal, which can be used as oe , and the we1 , we2 , we3 , and we7 signals, which can be used as we , iciord , iciowr , and reg , respectively, are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits a6w2 to a6w0 in the wcr2 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( rdy ). when the burst function is used, the number of bu rst cycle transfer states is determined in the range 2 to 9 according to the number of waits. the read/write strobe signal address and cs setup and hold times can be set within a range of 0?1 and 0?3 cycles, respectively, by means of bit a6s0 and bits a6h1 and a6h0 in the wcr3 register. when a pcmcia interface is used, the address/ ce1b / ce2b setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits anted1 and anted0, and bits anteh1 and anteh0, in the pcr register. in addition, the number of wait cycles can be set in the range 0 to 50 with bits anpcw1 and anpcw0. the number of waits set in pcr is added to the number of waits set in wcr2.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 438 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.3.3 sram interface basic timing: the sram interface of this lsi uses strobe signal output in consideration of the fact that mainly sram will be connected. figure 13.6 shows the basic timing of normal space accesses. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. the csn signal is asserted on the t1 rising edge, and negated on the next t2 clock risi ng edge. therefore, there is no negation period in case of access at minimum pitch. there is no access size specification when readin g. the correct access address is output to the address pins (a[25:0]), but since there is no access size specification, 32 bits are always read in the case of a 32-bit device, and 16 bits in the case of a 16-bit device. when writing, only the we signal for the byte to be written is asserted. fo r details, see section 13.3 .1, endian/access size and data alignment. in 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed in wrap around mode on the data at the 32-byte boundary. the bus is not released during this transfer.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 439 of 1076 sep 24, 2013 t1 ckio a25?a0 cs n rd/ wr rd d63?d0 (read) w en d63?d0 (write) bs t2 rdy dackn (sa: io memory) dackn (sa: io memory) dackn (da) le g end: sa: sin g le address dma da: dual address dma note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.6 basic timi ng of sram interface
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 440 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 figures 13.7 to 13.10 show examples of connection to 64-, 32-, 16-, and 8-bit data width sram. a19?a3 cs n rd d63?d56 we7 SH7750, SH7750s, SH7750r 128k 8-bit sram a16?a0 cs oe i/o7?i/o0 we a16?a0 cs oe i/o7?i/o0 we a16?a0 cs oe i/o7?i/o0 we d55?d48 we6 d47?d40 we5 d39?d32 we4 d31?d24 we 3 d23?d16 we2 d15?d8 we1 d7?d0 we0 a16?a0 cs oe i/o7?i/o0 we a16?a0 cs oe i/o7?i/o0 we a16?a0 cs oe i/o7?i/o0 we a16?a0 cs oe i/o7?i/o0 we a16?a0 cs oe i/o7?i/o0 we figure 13.7 example of 64-bi t data width sram connection
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 441 of 1076 sep 24, 2013 ???? ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a18 a2 cs n rd d31 d24 we 3 d23 d16 we2 d15 d8 we1 d7 d0 we0 SH7750, SH7750s, SH7750r 128k 8-bit sram ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? figure 13.8 example of 32-bi t data width sram connection
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 442 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 a16 a0 cs oe i/o7 i/o0 we a17 a1 cs n rd d15 d8 we1 d7 d0 we0 SH7750, SH7750s, SH7750r 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? figure 13.9 example of 16-bi t data width sram connection
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 443 of 1076 sep 24, 2013 a16 a0 cs n rd d7 d0 we0 SH7750, SH7750s, SH7750r 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? ???? ???? figure 13.10 example of 8-bi t data width sram connection wait state control: wait state insertion on the sram inte rface can be controlled by the wcr2 settings. if the wcr2 wait specification bits co rresponding to a particul ar area are not zero, a software wait is inserted in ac cordance with that speci fication. for details, see section 13.2.6, wait control register 2 (wcr2). the specified number of tw cycl es are inserted as wait cycles using the sram interface wait timing shown in figure 13.11.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 444 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 t1 ckio a25?a0 cs n rd/ wr rd d63?d0 (read) w en d63?d0 (write) bs tw t2 rdy dackn (sa: io memory) dackn (sa: io memory) dackn (da) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.11 sram interface wa it timing (software wait only)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 445 of 1076 sep 24, 2013 when software wait insertion is specified by wcr2, the external wait input rdy signal is also sampled. rdy signal sampling is shown in figure 13.1 2. a single-cycle wait is specified as a software wait. sampling is performed at the transitio n from the tw state to the t2 state; therefore, the rdy signal has no effect if asserted in th e t1 cycle or the first tw cycle. the rdy signal is sampled on the rising edge of the clock. t1 tw twe t2 ckio a25?a0 cs n rd/ wr rd (read) d63?d0 (read) w en (write) d63?d0 (write) bs rdy dackn (sa: io memory) dackn (sa: io memory) dackn (da) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.12 sram interface wait st ate timing (wait state insertion by rdy signal)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 446 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 read-strobe negate timing (setting only possible in the SH7750r): when the sram interface is used, timing for the ne gation of the strobe during read operations can be specified by the setting of the a1rdh and a4rdh bits of the wcr3 register. for information about this setting, see the description of the wcr3 register. when a byte control sram setting is made, anrdh should be cleared to 0. ts1 ckio a25 ? a0 csn rd/wr rd d63 ? d0 bs t1 tw tw tw tw t2 th1 th2 * ts1: setup wait wcr3.ans (0 to 1) tw: access wait wcr2.anw (0 to 15) th1, th2: hold wait wcr3.anh (0 to 3) note: * when anrdh is set to 1 figure 13.13 sram interface read-strobe negate timing (ans = 1, anw = 4, anh = 2)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 447 of 1076 sep 24, 2013 13.3.4 dram interface direct connection of dram: when the memory type bits (dramtp2?0) in bcr1 are set to 100, area 3 becomes dram space; when set to 101, area 2 and area 3 become dram space. the dram interface function can then be us ed to connect dram to this lsi. 16, 32, or 64 bits can be selected as the inte rface data width for area 3 when bits dramtp2?0 are set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits dramtp2?0 are set to 101. 2-cas 16-bit drams can be connected, since cas is used to control byte access. signals used for connection when dram is connected to area 3 are ras , cas0 to cas7 , and rd/ wr . cas2 to cas7 are not used when the data width is 16 bits. when dram is connected to areas 2 and 3, the signals for area 2 dram connection are ras2 , cas4 to cas7 , and rd/ wr , and those for area 3 dram connection are ras , cas0 to cas3 , and rd/ wr . in addition to normal read and write access modes, fast page mode is supported for burst access. for dram connected to areas 2 and 3, edo mo de, which enables the dram access time to be increased, is supported.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 448 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 a12?a3 r a s cs 3 rd/ wr d63?d48 w e 7 w e 6 SH7750, SH7750s, SH7750r 1m 16-bit dram a9?a0 r a s o e w e i/o15?i/o0 u c a s l c a s d15?d0 w e1 w e 0 a9?a0 r a s o e w e i/o15?i/o0 u c a s l c a s a9?a0 r a s o e w e i/o15?i/o0 u c a s l c a s a9?a0 r a s o e w e i/o15?i/o0 u c a s l c a s d31?d16 w e3 w e 2 d47?d32 w e5 w e4 figure 13.14 example of dram connection (64-bit data width, area 3)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 449 of 1076 sep 24, 2013 a10 a2 ras cs 3 rd/ wr d31 d16 cas 3 cas2 d15 d0 cas1 cas0 SH7750, SH7750s, SH7750r 256k 16-bit dram a8 a0 ras oe we i/o15 i/o0 u cas lcas a8 a0 ras oe we i/o15 i/o0 u cas lcas ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? figure 13.15 example of dram connection (32-bit data width, area 3)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 450 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 a9 a1 cs 3 cs2 ras ras2 rd/ wr d15 d0 cas1 cas0 cas5 cas4 SH7750, SH7750s, SH7750r 256k 16-bit dram a8 a0 ras oe we i/o15 i/o0 u cas lcas a8 a0 ras oe we i/o15 i/o0 u cas lcas area 3 area 2 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? figure 13.16 example of dram connection (16-bit data width, areas 2 and 3)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 451 of 1076 sep 24, 2013 address multiplexing: when area 2 or area 3 is design ated as dram space, address multiplexing is always performed in accesses to dram. this enables dram, which requires row and column address multiplexing, to be connected to this lsi without using an external address multiplexer circuit. any of the five multiplexing methods shown below can be selected, by setting bits amxext and amx2?0 in mcr for area 2 or 3 dram. the relationship between the amxext and amx2?0 bits and address multiplexing is shown in table 13.15. the address output pins subject to address multiplexing are a17 to a1. the address signals output by pins a25 to a18 are undefined. table 13.15 relationship between amxext a nd amx2?0 bits and address multiplexing setting external address pins amxext amx2 amx1 amx0 number of column address bits output timing a1?a13 a14 a15 a16 a17 0 0 0 0 8 bits column address a1?a13 a14 a15 a16 a17 row address a9?a21 a22 a23 a24 a25 1 9 bits column address a1?a13 a14 a15 a16 a17 row address a10?a22 a23 a24 a25 a17 1 0 10 bits column address a1?a13 a14 a15 a16 a17 row address a11?a23 a24 a25 a16 a17 1 11 bits column address a1?a13 a14 a15 a16 a17 row address a12?a24 a25 a15 a16 a17 1 0 0 12 bits column address a1?a13 a14 a15 a16 a17 row address a13?a25 a14 a15 a16 a17 other settings reserved ? ? ? ? ? ?
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 452 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 basic timing: the basic timing for dram access is 4 cy cles. this basic timing is shown in figure 13.17. tpc is the precharge cycle, tr the ras assert cycle, tc1 the cas assert cycle, and tc2 the read data latch cycle. tr1 tr2 tc1 tc2 tpc row ckio a25?a0 cs n rd/ wr ras d63?d0 (read) cas d63?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) column legend: io: dack device sa: single address dma transfer da: dual address dma transfer the dack is in the high-active setting note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.17 basi c dram access timing
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 453 of 1076 sep 24, 2013 wait state control: as the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. therefore, provision is made for stat e extension by using the setting bits in wcr2 and mcr. the timing with state extension using these settings is shown in figure 13.18. additional tpc cycl es (cycles used to secure the ras precharge time) can be inserted by means of the tpc bit in mcr, giving from 1 to 7 cycles. the number of cycles from ras assertion to cas assertion can be set to between 2 and 5 by inserting trw cycles by means of the rcd bit in mcr. also, th e number of cycles from cas assertion to the end of the access can be varied between 1 and 16 according to the setting of a2w2 to a2w0 or a3w2 to a3w0 in wcr2. tr1 ckio a25?a0 cs n rd/ wr r a s d63 ? d0 (read) c a s d63 ? d0 (write) bs tr2 trw tc1 tcw tc2 tpc tpc dackn (sa: io memory) dackn (sa: io memory) column row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.18 dram wait state timing
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 454 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 burst access: in addition to the normal dram access mode in which a row addr ess is output in each data access, a fast page mode is also pr ovided for the case where consecutive accesses are made to the same row. this mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access. normal access or burst access using fast page mode can be selected by means of the burs t enable (be) bit in mcr. the timing for burst access using fast page mode is shown in figure 13.19. if the access size exceeds the set bus width, burst acces s is performed. in a 32-byte burst transfer (cache fill), the first access comprises a longword that includes the data requiring access. the remaining accesses are performed on 32-byte boundar y data that includes the relevant data. in burst transfer (cache write-b ack), wraparound writing is performed for 32-byte data. tr2 tc1 tc2 tc1 tc2 tc2 tr1 rc1c2c3c4 tc1 tpc tc2 tc1 ckio a25?a0 cs n rd/ wr r a s c a s d63?d0 (read) d63?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) d4 d3 d2 d2 d1 d3 d4 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.19 dram burst access timing
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 455 of 1076 sep 24, 2013 edo mode: with dram, in addition to the mode in which data is output to the data bus only while the cas signal is asserted in a data read cycle, an edo (extended data out) mode is also provided in which, once the cas signal is asserted while the ras signal is asserted, even if the cas signal is negated, data is output to the data bus until the cas signal is next asserted. in this lsi, the edo mode bit (edomode) in mcr enable s either normal access/burst access using fast page mode, or edo mode norm al access/burst access, to be selected for dram. when edo mode is set, be must be set to 1 in mcr. ed o mode normal access is show n in figure 13.20, and burst access in fi gure 13.21. cas negation period: the cas negation period can be set to 1 or 2 by means of the tcas bit in the mcr register. tr1 row tc1 tc2 tce tpc tr2 ckio a25?a0 cs n rd/ wr r a s c a s n d63?d0 (read) bs dackn (sa: io memory) column note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.20 dram bus cycle (edo mode, rcd = 0, anw = 0, tpc = 1)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 456 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tr1 rc1c2c3 c4 tc1 tc2 tc1 tc2 tc1 tc1 tr2 tc2 tc2 tpc tce ckio a25?a0 cs n rd/ wr r a s c a s d63?d0 (read) bs dackn (sa: io memory) d4 d3 d2 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.21 burst access timing in dram edo mode ras down mode: this lsi has an address comparator for detecting row address matches in burst mode. by using this address comparator, and also setting ras down mode specification bit rasd to 1, it is possible to select ras down mode, in which ras remains asserted after the end of an access. when ras down mode is used, if the re fresh cycle is longer than the maximum dram ras assert time, the refresh cycle must be d ecreased to or below th e maximum value of t ras . ras down mode can only be used when dram is connected in area 3. in ras down mode, in the event of an access to an address with a different row address, an access to a different area, a refresh request, or a bus request, ras is negated and the necessary operation is performed. when dram access is resumed after th is, since this is the st art of ras down mode, the operation starts with row address output. timing charts are shown in figures 13.22 (1) to (4).
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 457 of 1076 sep 24, 2013 tr1 tr2 tc1 tc2 tc1 tc1 tpc rc1c2c3c4 tc2 tc2 tc1 tc2 ckio a25?a0 cs n rd/ wr r a s c a s d63?d0 (read) d63?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) d4 d3 d2 d1 d4 d3 d2 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.22 (1) dram burst bu s cycle, ras down mode start (fast page mode, rcd = 0, anw = 0)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 458 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tnop tc1 tc2 tc1 tc2 tc1 tc1 tc2 tc2 ckio a25?a0 cs n rd/ wr r a s c a s n d63?d0 (read) d63?d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) c0 c1 c2 c3 d0 d0 d1 d2 d3 d1 d2 d3 end of ras down mode note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.22 (2) dram burst bus cy cle, ras down mode continuation (fast page mode, rcd = 0, anw = 0)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 459 of 1076 sep 24, 2013 tpc tr2 tc1 tc2 tc1 tc2 tc2 tr1 rc1c2c3 c4 tc1 tc1 tce tc2 ckio a25?a0 cs n rd/ wr r a s c a s d63?d0 (read) bs dackn (sa: io memory) d4 d3 d2 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.22 (3) dram burst bu s cycle, ras down mode start (edo mode, rcd = 0, anw = 0)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 460 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tc2 tc1 tc2 tc1 tc2 tc2 tc1 c1 c2 c3 c4 tc1 tce ckio a25?a0 cs n rd/ wr r a s c a s d63?d0 (read) bs dackn (sa: io memory) d4 d3 d2 d1 end of ras down mode note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.22 (4) dram burst bus cy cle, ras down mode continuation (edo mode, rcd = 0, anw = 0)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 461 of 1076 sep 24, 2013 refresh timing: the bus state controller includes a function for controlling dram refreshing. distributed refreshing using a cas-before-ras cycle can be performed for dram by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. self-refresh mode is also supported. ? cas-before-ras refresh when cas-before-ras refresh cycles are execu ted, refreshing is performed at intervals determined by the input clock selected by bits cks2?cks0 in rtcsr, and the value set in rtcor. the value of bits cks2?cks0 in rt cor should be set so as to satisfy the specification for the dram refresh interval. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in mcr, then make the cks2?cks0 setting. when the clock is selected by cks2?cks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and the back pin goes high. if this lsi's external bus can be used, cas-before-ras refreshing is performed. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 13.23 shows the operation of cas-before-ras refreshing. rtcnt value rtcor-1 h'00000000 rtcsr.cks2?0 external bus refresh request cleared by start of refresh cycle = 000 000 rtcnt cleared to 0 when rtcnt = rtcor cas-before-ras refresh cycle time refresh request figure 13.23 cas-before -ras refresh operation
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 462 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 13.24 shows the timing of the cas-before-ras refresh cycle. the number of ras assert cycles in the refresh cycle is speci fied by bits tras2?tras0 in mcr. the specification of the ras precharge time in the refresh cycle is determined by the setting of bits trc2?trc0 in mcr. trr2 trr3 trr4 trr5 trc trr1 trc trc ckio a25?a0 cs n rd/ wr r a s c a s d63?d0 bs figure 13.24 dram cas-before-ras ref resh cycle timing (tras = 0, trc = 1)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 463 of 1076 sep 24, 2013 ? self-refresh the self-refreshing supported by this lsi is shown in figure 13.25. after the self-refresh is cleared, the refresh c ontroller immediately generates a refresh request. the ras precharge time immediately after the end of the self-refreshing can be set by bits trc2?trc0 in mcr. cas-before-ras refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset. when the bus has been released in response to a bus arbitration request, or when a transition is made to standby mode, signals generally become high-impedance, but whether the ras and cas signals become high-impedance or continue to be output can be controlled by the hizcnt bit in bcr1. this enables the dram to be kept in the self-refreshing state. as the dram cas signal is multiplexed with wen for normal memory (sram, etc.), access to memory that uses the wen signals must be disabled during self-refreshing. ? relationship between refresh requests and bus cycle requests if a refresh request is generated during executio n of a bus cycle, execu tion of the refresh is deferred until the bus cycle is completed. refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width me mory) and during a 32-b yte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a tas instruction, and between read an d write cycles when dmac dual address transfer is executed. if a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. if a ma tch between rtcnt and rtcor occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. in order for refr eshing to be performed normally, care must be taken to ensure that no bus cycle or bus master ship occurs that is longer than the refresh interval. when a refresh request is generated, the back pin is negated (driven high). therefore, normal refreshing can be performed by having the back pin monitored by a bus master other than this lsi requesting the bus, or the bus arbiter, and returning the bus to this lsi.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 464 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 trr2 trr3 trr4 trr5 trc trr1 trc trc ckio a25?a0 cs n rd/ wr r a s c a s d63?d0 bs figure 13.25 dram se lf-refresh cycle timing power-on sequence: regarding use of dram after powering on, it is requested that a wait time (at least 100 s or 200 s) during which no access can be performed be provided, followed by at least the prescribed number (usually 8) of dummy cas-before-ras refresh cycles. as the bus state controller does not perform any special opera tions for a power-on reset, the necessary power- on sequence must be carried out by the initiali zation program executed af ter a power-on reset.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 465 of 1076 sep 24, 2013 13.3.5 synchronous dram interface connection of synchronous dram: since synchronous dram can be selected by the cs signal, it can be connected to ph ysical space areas 2 and 3 using ras and other control signals in common. if the memory type bits (dramtp2?0 ) in bcr1 are set to 010, area 2 is normal memory space and area 3 is synchronous dram sp ace; if set to 011, areas 2 and 3 are both synchronous dram space. with this lsi, burst read/burst write mode is supported as the synchronous dram operating mode. the data bus width is 32 or 64 bits, and the sz size bits in mcr must be set to 00 or 11. the burst enable bit (be) in mcr is ignored, a 32-byte burst transfer is performed in a cache fill/copy-back cycle, and in a wr ite-through area write or a non-cacheable area read/write, 32-byte data is read even in a single read in order to access synchronous dram with a burst read/write access. 32-byte data transfer is also performed in a single write, but dqmn is not asserted when unnecessary data is transferred. for details on the burst length, see section 13.2.10, synchronous dram mode register (sdmr), and power-on sequence in section 13.3.5, synchronous dram interface. the SH7750r gr oup supports burst read and burst wr ite operations with a burst length of 4 as a synchronous dram operating mode when using a 32-bit data bus. the burst enable (be) bit in mcr is ignored, and a 32-byt e burst transfer is performed in a cache fill or copy-back cycle. in write-through area write operations and non-cacheab le area read or write op erations, 16 bytes of data is read even in a single read because burs t read or write accesses to synchronous dram use a burst length of 4. sixteen bytes of data is transferred in the case of a single write also, but dqmn is not asserted when unnece ssary data is transferred. for changing the burst length (a function only available in the SH7750r) for a 32-bit bus, see notes on changing the burst length (SH7750r only) in section 13.3.5, synchronous dram interface. the control signals for connection of synchronous dram are ras , cas , rd/ wr , cs2 or cs3 , dqm0 to dqm7, and cke. all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid and latched only when cs2 or cs3 is asserted. synchronous dram can therefore be connected in parallel to a number of areas. cke is negated (driven low) when the frequency is changed, when the clock is unstable after the clock supply is stopped and restarted, or when self-refreshing is performed, an d is always asserted (high) at other times. commands for synchronous dram are specified by ras , cas , rd/ wr , and specific address signals. the commands are nop, au to-refresh (ref), self-refresh (self), precharge all banks (pall), precharge specified bank (pre), row ad dress strobe bank active (actv), read (read), read with precharge (reada), wr ite (writ), write with precharge (writa), and mode register setting (mrs).
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 466 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 byte specification is performed by dqm0 to dqm7. a read/write is performed for the byte for which the corresponding dqm signal is low. when the bus width is 64 bits, in big-endian mode dqm7 specifies an access to address 8n, and dqm0 specifies an access to address 8n + 7. in little-endian mode, dqm7 specifies an access to ad dress 8n + 7, and dqm0 specifies an access to address 8n. figures 13.26 and 13.27 show examples of the connection of 16m 16-bit synchronous drams. a12?a3 ckio cke cs 3 ras cass rd/ wr d63?d48 dqm7 dqm6 SH7750, SH7750s, SH7750r 512k 16-bit 2-ban k synchronous dram a9?a0 clk cke cs ras cas we i/o15?i/o0 dqmu dqml d47?d32 dqm5 dqm4 d31?d16 dqm3 dqm2 d15?d0 dqm1 dqm0 a9?a0 clk cke cs ras cas we i/o15?i/o0 dqmu dqml a9?a0 clk cke cs ras cas we i/o15?i/o0 dqmu dqml a9?a0 clk cke cs ras cas we i/o15?i/o0 dqmu dqml figure 13.26 example of 64-bit data wi dth synchronous dram connection (area 3)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 467 of 1076 sep 24, 2013 a11?a2 ckio cke cs 3 ras cass rd/ wr d31?d16 dqm3 dqm2 SH7750, SH7750s, SH7750r 512k 16-bit 2-ban k synchronous dram a9?a0 clk cke cs ras cas we i/o15?i/o0 dqmu dqml d15?d0 dqm1 dqm0 a9?a0 clk cke cs ras cas we i/o15?i/o0 dqmu dqml figure 13.27 example of 32-bit data wi dth synchronous dram connection (area 3) address multiplexing: synchronous dram can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits amxext and amx2? amx0 in mcr. table 13.16 shows the relationship between the address multiplex specification bits and the bits output at the address pins. see appendix f, synchronous dram address multiplexing tables. address pin output at a25?a18, a1, and a0 are undefined. when a0, the lsb of the synchronous dram address, is connected to this lsi, with a 32-bit bus width it makes a longword address specification. connection should therefore be made in this order: connect pin a0 of the synchronous dram to pin a2 of this lsi, then connect pin a1 to pin a3. with a 64-bit bus width, the lsb makes a quadword address specification. connection should therefore be made in this order: connect pin a0 of the synchronous dram to pin a3 of this lsi, then connect pin a1 to pin a4.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 468 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.16 example of correspondence be tween this lsi and synchronous dram address pins (64-bit bus width, amx2?amx0 = 011, amxext = 0) lsi address pin synchronous dram address pin ras cycle cas cycle function a14 a22 a22 a11 bank select bank address a13 a21 h/l a10 address precharge setting a12 a20 0 a9 a11 a19 0 a8 a10 a18 a10 a7 a9 a17 a9 a6 a8 a16 a8 a5 a7 a15 a7 a4 a6 a14 a6 a3 a5 a13 a5 a2 a4 a12 a4 a1 a3 a11 a3 a0 a2 ? a2 not used a1 ? a1 not used a0 ? a0 not used burst read: the timing chart for a burst read is shown in figure 13.28. in the following example it is assumed that four 512k 16-bit 2-bank synchronous drams are connected, and a 64-bit data width is used. the burst length is 4. following the tr cycle in which actv command output is performed, a reada command is issued in the tc1 cycle, and th e read data is accepted on the rising edge of the external command clock (ckio) from cycle td1 to cycle td4. the tpc cycle is used to wait for completion of auto-prechar ge based on the reada command inside the synchronous dram; no new access command can be issu ed to the same bank during this cycle. in this lsi, the number of tpc cycl es is determined by the specification of bits tpc2?tpc0 in mcr, and commands are not issued for synchronous dram during this interval. the example in figure 13.28 sh ows the basic cycle. to connect slower synchronous dram, the cycle can be extended by setting wcr2 and mcr bits. the number of cycles from the actv command output cycle, tr, to the reada command output cycle, tc 1, can be specified by bits rcd1 and rcd0 in mcr, with a value of 0 to 3 sp ecifying 2 to 4 cycles, re spectively. in the case of 2 or more cycles, a trw cycle, in which an nop command is issued for the synchronous dram, is inserted between the tr cycle and the tc cycle. the number of cycles from reada
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 469 of 1076 sep 24, 2013 command output cycle tc1 to the first read data latc h cycle, td1, can be speci fied as 1 to 5 cycles independently for areas 2 and 3 by means of bits a2w2?a2w0 and a3w2?a3w0 in wcr2. this number of cycles corresponds to the number of synchronous dram cas latency cycles. tr trw tc1 tc2 tc3 tc4/td1 td3 td2 td4 ckio bank prechar g e-sel address cs n rd/ wr r a s c a ss d63?d0 (read) dqmn bs dackn (sa: io memory) cke h/l c0 d0 d1 d2 d3 row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.28 basic timing for synchronous dram burst read
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 470 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 in a synchronous dram cycle, the bs signal is asserted for one cycl e at the start of the bus cycle. the access sequence is as fo llows: in a fill operatio n in the event of a cache miss, 64-bit boundary data including the missed data is read first, then 32-byte boundary data including the missed data is read in wraparound mode. single read: with this lsi, as synchronous dram is set to burst read/burst write mode, read data output continues after the required data has been read. to prevent data collisions, after the required data is read in td1, empty read cycles td2 to td4 are performed, and this lsi waits for the end of the synchronous dram operation. the bs signal is asserted only in td1. when the data width is 64 bits, there are 4 burst transfers in a read. in cache-through and other dma read cycles, of cycles td1 to td4, bs is asserted and data latched only in the td1 cycle. since such empty cycles increase the memory access time, and tend to reduce program execution speed and dma transfer speed, it is importan t both to avoid unnece ssary cache-through area accesses, and to use a data structure that will allo w data to be placed at a 32-byte boundary, and to be transferred in 32-byte units, when carrying out dma transfer with synchronous dram specified as the source.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 471 of 1076 sep 24, 2013 tr tc1 tc2 c1 tc3 tc4/td1 td2 td4 trw h/l c1 td3 tpc tpc tpc ckio bank prechar g e-sel address cs n dqmn rd/ wr r a s c a ss d63?d0 (read) bs cke dackn (sa: io memory) row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.29 basic timing for synchronous dram single read
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 472 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 burst write: the timing chart for a burst write is shown in figure 13.30. in this lsi, a burst write occurs only in the event of cach e copy-back or a 32-byte transfer by the dmac. in a burst write operation, the writa command is issued in the tc1 cycle following the tr cycle in which the actv command is output. in the write cycle, the write data is output at the same time as the write command. in the case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for synchronous dram is postponed during this interval . the number of trwl cycles can be specified by bits trwl2?trwl0 in mcr. 32-byte boundary data is written in wraparound mode. dack is asserted two cycles before the data write cycle.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 473 of 1076 sep 24, 2013 tr tc1 tc2 tc3 tc4 trwl tpc trw h/l c1 trwl ckio bank precharge-sel address cs n dqmn rd/ wr ras cass d63?d0 (read) bs cke dackn (sa: io memory) c1 c2 c3 c4 row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.30 basic timing fo r synchronous dram burst write single write: the basic timing chart for write access is sh own in figure 13.31. in a single write operation, following the tr cycle in which actv command output is performed, a writa command that performs auto -precharge is issued in the tc1 cycle. in the write cycle, the write data is output at the same time as the write comman d. in the case of a write with auto-precharge, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for synchronous dram until precharging is completed. consequently, in additio n to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for synchronous dram is postponed during this
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 474 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 interval. the number of trwl cycles can be specified by bits trwl2?trwl0 in mcr. dack is asserted two cycles before the data write cycle. as this lsi supports burst read/burst write operations for synchronous dram, there are empty cycles in a single write operation. tr tc1 tc2 tc3 tc4 trwl tpc trw h/l c1 trwl ckio bank precharge-sel address cs n dqmn rd/ wr ras cass d63?d0 (read) bs cke dackn (sa: io memory) c1 row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.31 basic timing for synchronous dram single write
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 475 of 1076 sep 24, 2013 ras down mode: the synchronous dram bank function is used to support high-speed accesses to the same row address. when the rasd bit in mcr is 1, read/write command accesses are performed using commands without auto-precharge (read, writ). in this case, precharging is not performed when the access ends. when accessing the same row addr ess in the same bank, it is possible to issue the read or writ command immediately, without issuing an actv command, in the same way as in the dram ras down state. as synchronous dram is internally divided into two or four banks, it is possible to activate one row address in each bank. if the next access is to a different row address, a pre command is first issued to precharge the relevant bank, then when precharging is completed, the access is perf ormed by issuing an actv command followed by a read or writ command. if this is followed by an access to a different row address, the access time will be longer because of the precharg ing performed after the access request is issued. in a write, when auto-precharge is performed, a command cannot be issued for a period of trwl + tpc cycles after issuance of the writ comm and. when ras down mode is used, read or writ commands can be issued successively if the row address is the same. the number of cycles can thus be reduced by trwl + tpc cycles for each write . the number of cycl es between issuance of the precharge command and the row address strobe command is determined by bits tpc2? tpc0 in mcr. there is a limit on t ras , the time for placing each bank in the active state. if there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program executio n, it is necessary to set auto-refresh and set the refresh cycle to no more th an the maximum value of t ras . in this way, it is possible to observe the restrictions on the maximum activ e state time for each bank. if auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. a burst read cycle without auto-precharge is shown in figure 13.32, a burst read cycle for the same row address in figure 13.33, and a burst read cy cle for different row addresses in figure 13.34. similarly, a burst write cycle without auto-precharge is shown in figure 13.35, a burst write cycle for the same row address in figure 13.36, and a burst write cycle for diffe rent row addresses in figure 13.37. when synchronous dram is read, there is a 2-cycle latency for the dmqn signal that performs the byte specification. as a result, when the read command is issued in figure 13.32, if the tc cycle is executed immediately, the dmqn signal sp ecification for td1 cycle data output cannot be carried out. therefore, the cas latency should not be set to 1. when ras down mode is set, if only accesses to the respective banks in area 3 are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 13.32 or 13.35, followed by re petition of the cycle in figure 13.33 or 13.36. an access to a
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 476 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 different area during this time has no effect. if th ere is an access to a different row address in the bank active state, after this is de tected the bus cycle in figure 13.3 4 or 13.37 is executed instead of that in figure 13.33 or 13.36. in ras down mode, too, a pall command is issued before a refresh cycle or before bus releas e due to bus arbitration. c2 c3 c4 tr tc1 tc2 c1 tc3 tc4/td1 td2 td4 trw h/l c1 td3 ckio bank prechar g e-sel address cs n dqmn rd/ wr r a s c a ss d63?d0 (read) bs cke dackn (sa: io memory) row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.32 burst read timing
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 477 of 1076 sep 24, 2013 c2 c3 c4 tc1 tc3 tc4/td1 c1 td2 td3 td4 tc2 h/l c1 ckio bank prechar g e-sel address cs n dqmn rd/ wr r a s c a ss d63?d0 (read) bs cke dackn (sa: io memory) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.33 burst read timing (ras down, same row address)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 478 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tpr tr trw c1 c2 c3 c4 tc1 tc2 tc3 td2 tpc h/l c1 tc4/td1 td3 td4 ckio bank prechar g e-sel row row row address cs n dqmn rd/ wr r a s c a ss d63?d0 (read) bs cke dackn (sa: io memory) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.34 burst read timing (ras down, differen t row addresses)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 479 of 1076 sep 24, 2013 tr tc1 tc2 tc3 tc4 trwl trw h/l c1 trwl ckio bank precharge-sel address cs n dqmn rd/ wr ras cass d63?d0 (read) bs cke c1 c2 c3 c4 row row row dackn (sa: io memory) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.35 burst write timing
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 480 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tnop tc2 tc3 tc4 trwl trwl tc1 h/l c1 tncp ckio bank precharge-sel address cs n dqmn rd/ wr ras cass d63?d0 (read) bs cke c1 c2 c3 c4 row dackn (sa: io memory) single-address dma normal write note: in the case of sa-dma only, the (tnop) cycle is inserted, and the dackn signal is output as shown by the solid line. in a normal write, the (tnop) cycle is omitted and the dackn signal is output as shown by the dotted line. dackn shows an example where dmac, chcrn, and al (acknowledge level) are 0. figure 13.36 burst write timing (same row address)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 481 of 1076 sep 24, 2013 tpr tr trw tc1 tc2 tc3 tpc h/l h/l c1 tc4 trwl trwl trwl ckio bank precharge-sel address cs n dqmn rd/ wr ras cass d63?d0 (read) bs cke dackn (sa: io memory) c1 c2 c3 c4 row row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.37 burst write timi ng (different row addresses) pipelined access: when the rasd bit is se t to 1 in mcr, pipelined access is performed between an access by the cpu and an access by the dmac, or in the case of consecutive accesses by the dmac, to provide faster access to synchronous dram. as synchronous dram is internally divided into two or four banks, after a read or writ command is issued for one bank it is possible to issue a pre, actv, or other command during the cas latency cycle or data latch cycle, or during the da ta write cycle, and so shorten the access cycle.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 482 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 when a read access is followed by another read access to the same row address, after a read command has been issued, another read command is issued before the end of the data latch cycle, so that there is read data on the data bus continuously. when an access is made to another row address and the bank is different, the pre command or actv command can be issued during the cas latency cycle or data latch cycle. if th ere are consecutive access requests for different row addresses in the same bank, the pre command cannot be issued until the last-but-one data latch cycle. if a read access is followed by a write acce ss, it may be possible to issue a pre or act command, depending on the bank and row address, but since the write data is output at the same time as the writ command, the pre, actv, and wr it commands are issued in such a way that one or two empty cycles occur automatically on the data bus. similarly, with a read access following a write access, or a write access following a write access, the pre, actv, read, or writ command is issued during the data write cycle for the preceding ac cess; however, in the case of different row addresses in the same bank, a pre command cannot be issued, and so in this case the pre command is issued fo llowing the number of trwl cycl es specified by the trwl bits in mcr, after the end of the last data write cycle. figure 13.38 shows a burst read cycle for a different bank and row address following a preceding burst read cycle. pipelined access is enabled only for consecutive acces s to area 3, and will be discontinued in the event of an access to another area. pipelined access is also discontinued in the event of a refresh cycle, or bus release due to bus arbitration. the cases in which pipelined access is available are shown in table 13.17. in this table, ?dmac dual? indicates transfer in dmac dual address mode, and ?dmac single?, transfer in dmac single address mode.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 483 of 1076 sep 24, 2013 tc1_a tc1_b h/l c_b ckio bank prechar g e-sel address cs n dqmn rd/ wr r a s c a ss d63?d0 (read) bs cke a1 a2 a3 a4 b1 b2 c_a h/l note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.38 burst read cy cle for different bank and ro w address following preceding burst read cycle
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 484 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 13.17 cycles for which pipeline access is possible succeeding access cpu dmac dual dmac single preceding access read write read write read write cpu read x x o x o o write x x o x o o dmac dual read x x x x x x write o o o x o o dmac single read o o x x o o write o o o x o o legend: o: pipeline access possible x: pipeline access not possible refreshing: the bus state controller is provided with a function for controlling synchronous dram refreshing. auto-refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. if synchronous dram is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1. ? auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks2? cks0 in rtcsr, and the value set in rtco r. the value of bits cks2?cks0 in rtcor should be set so as to satisfy the refresh interval specification for the synchronous dram used. first make the settings for rtcor, rtcn t, and the rmode and rfsh bits in mcr, then make the cks2?cks0 setting last of all. when the clock is selected by cks2?cks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the tw o values are the same, a refresh request is generated and an auto-refresh is performed. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 13.4 0 shows the auto-refresh cycle timing. first, an ref command is issued in the trr cy cle. after the trr cycle, new command output cannot be performed for the duration of the numb er of cycles specified by bits tras2?tras0 in mcr plus the number of cycles specifi ed by bits trc2?trc0 in mcr. the tras2? tras0 and trc2?trc0 bits must be set so as to satisfy the synchronous dram refresh cycle time specification (active/active command delay time). auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 485 of 1076 sep 24, 2013 when both areas 2 and 3 are set to the synchronous dram, auto-refreshing of area 2 is performed subsequent to area 3. rtcnt value rtcor-1 h'00000000 rtcsr.cks2?0 external bus refresh request cleared by start of refresh cycle = 000 000 rtcnt cleared to 0 when rtcnt = rtcor auto-refresh cycle time refresh request figure 13.39 auto-refresh operation trr2 trr3 trr4 trr5 trc trr1 trc trrw trc ckio cs n rd/ wr r a s dqmn bs cke d63?d0 c a ss figure 13.40 synchronous dram auto-refresh timing
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 486 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? self-refreshing self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit to 1. the self-refresh state is maintained while the cke signal is low. synchronous dram cannot be accessed wh ile in the self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command issuance is disabled fo r the number of cycles specified by bits trc2?trc0 in mcr. self-refresh timing is shown in figure 13.41. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. when self-re freshing is activated from the st ate in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if rfsh is set to 1 and rmode is clear ed to 0 when self-refresh mode is cleared. if the transition from clearing of self-refresh mode to the start of auto-refre shing takes time, this time should be taken into consideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will en able refreshing to be started immediately. after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using this lsi's standby function, and is maintained even after recovery from standby mode other than through a power-on reset. in the case of a power-on reset, the bus state c ontroller's registers are initialized, and therefore the self-refresh state is cleared. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 487 of 1076 sep 24, 2013 trs2 trs3 trs4 trs5 trc trs1 trc trc ckio cs n rd/ wr r a s dqmn bs cke d63?d0 c a ss figure 13.41 synchronous dram self-refresh timing
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 488 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? relationship between refresh requests and bus cycle requests if a refresh request is generated during executio n of a bus cycle, executi on of the refresh is deferred until the bus cycle is completed. refres h operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width me mory) and during a 32-b yte transfer such as a cache fill or write-back, and also between read and write cycles duri ng execution of a tas instruction, and between read an d write cycles when dmac dual address transfer is executed. if a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. if a ma tch between rtcnt and rtcor occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. in order for refr eshing to be performed normally, care must be taken to ensure that no bus cycle or bus master ship occurs that is longer than the refresh interval. when a refresh request is generated, the back pin is negated (driven high). therefore, normal refreshing can be performed by having the back pin monitored by a bus master other than this lsi requesting the bus, or the bus arbiter, and returning the bus to this lsi.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 489 of 1076 sep 24, 2013 power-on sequence: in order to use synchronous dram, mode setting must first be performed after powering on. to perform synchronous dram initialization correctly, th e bus state controller registers must first be set, followed by a write to the synchronous dram mode register. in synchronous dram mode register setting, the address signal value at that time is latched by a combination of the ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the synchronous dram mode register by performing a write to address h'ff900000 + x for area 2 synchronous dram, and to address h'ff940000 + x for area 3 synchronous dram. in this operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/write, cas latency 1 to 3, wrap type = sequential, and burst length 4* or 8, supported by this lsi, arbitrary data is written by byte- size access to the following addresses. bus width burst length cas latency area 2 area 3 32 4 * 1 2 3 h'ff900048 h'ff900088 h'ff9000c8 h'ff940048 h'ff940088 h'ff9400c8 32 8 1 h'ff90004c h'ff94004c 2 h'ff90008c h'ff94008c 3 h'ff9000cc h'ff9400cc 64 4 1 h'ff900090 h'ff940090 2 h'ff900110 h'ff940110 3 h'ff900190 h'ff940190 note: * SH7750r only. the value set in mcr.mrset is used to select whether a precharge all banks command or a mode register setting command is issued. the timing for the precharge all banks command is shown in figure 13.42 (1), and the timing for the mode register setting command in figure 13.42 (2). before mode register, a 200 s idle time (depending on the memory manufacturer) must be guaranteed after the power required for the synchronous dram is turned on. if the reset signal pulse width is greater than this idle time, there is no problem in making the precharge all banks setting immediately. first, a precharge all banks (pall) command is issu ed in the trp1 cycle by performing a write to address h'ff900000 + x or h'ff940000 + x while mcr.mrset = 0. next, the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. this is achieved automatically while various kinds of initialization are being performed after auto- refresh setting, but a way of carrying this out mo re dependably is to change the rtcor register
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 490 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 value to set a short refresh request generation in terval just while these dummy cycles are being executed. with simple read or write access, the address counter in the synchronous dram used for auto-refreshing is not initialized, and so the cycl e must always be an auto-refresh cycle. after auto-refreshing has been executed at least the pres cribed number of times, a mode register setting command is issued in the tmw1 cycle by setting mcr.mrset to 1 and performing a write to address h'ff900000 + x or h'ff940000 + x. synchronous dram mode register setting should be executed once only after power-on (reset) and before synchronous dram access, and no subsequent changes should be made. ckio bank precharge-sel address cs n rd/ wr r a s c a ss d63?d0 cke trp1 trp2 trp3 trp4 tmw1 tmw2 tmw3 tmw4 (high) tmw5 figure 13.42 (1) synchronous dram mode write timing (pall)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 491 of 1076 sep 24, 2013 ckio bank precharge-sel address cs n rd/ wr r a s c a ss d63?d0 cke trp1 trp2 trp3 trp4 tmw1 tmw2 tmw3 tmw4 (high) tmw5 figure 13.42 (2) synchronous dram mo de write timing (mode register set) notes on changing the burst length (SH7750r only): in the SH7750r, when synchronous dram is connected with a 32-bit memory bus, the burst length can be selected as either 4 or 8 by the setting of the sdbl bit of the bcr3 register. for more details, see the description of the bcr3 register.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 492 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? burst read figure 13.43 is the timing chart of a burst-read operation with a burst length of 4. following the tr cycle, during which an actv command is output, a read command is issued during cycle tc1, and a reada command is issued four cycles later. during the td1 to td8 cycles, read data are accepted on the rising edges of the external command clock (ckio). tpc is the cycle used to wait for the auto-precharging, whic h is triggered by the reada command, to be completed in the synchronous dram. during this cycle, a new command for accessing the same bank cannot be issued. in the SH7750r, th e number of tpc cycles is determined by the setting of the tpc2 to tpc0 bits of mcr, and no command that operates on the synchronous dram may be issued during these cycles. tr trw tc1 tc2 tc3 tc4/td1 td3 td2 td4 ckio bank prechar g e-sel address cs n rd/ wr r a s c a ss d31?d0 (read) dqmn bs cke h/l c5 td5 td6 td8 td7 tpc h/l c1 c1 c2 c3 c4 c7 c8 c5 c6 dackn (sa: io memory) row row row note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.43 basic timing of synchronous dram burst read (burst length = 4)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 493 of 1076 sep 24, 2013 in a synchronous dram cycle, the bs signal is asserted for one cycle at the beginning of each data transfer cycle that is in response to a read or reada command. data are accessed in the following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that include the missing data are first read by the initial read command; after that, the data between 16-bit boundaries data that include the missing data are read in a wraparound way. the subsequently issued reada command reads the 16 bytes of data, which is the remainder of the data between 32-byte boundaries, from the start of the 16-byte boundary. ? burst write figure 13.44 is the timing chart for a burst-write operation with a burst length of 4. in this lsi, a burst write takes place when a 32-byte data tran sfer has occurred. in a burst-write operation, subsequent to the tr cycle, in which actv command output takes place, a writ command is issued during the tc1 cycle, and a writa command is issued four cycles later. during the write cycle, write data is output together w ith the write command. with a write command that includes an auto precharge, the precharge is performed on the relevant bank of the synchronous dram on completion of the write command so no new command that accesses the same bank can be issued until precharging is completed. for this reason, in addition to the tpc precharge-waiting cycle used in read access, trwl cycles, which are a period of waiting for precharging to start after the write command, are added. these cycles delay the issuing of new commands to the synchronous dram. these cycles delay the issuing of new commands to the synchronous dram. the setting of the trwl2 to trwl0 bits of mcr selects the number of trwl cycles. the da ta between 16-byte boundaries is first accessed, and the data between 32-byte boundaries are then written in a wraparound way. dack is asserted for two cycles before the data-write cycle.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 494 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tr tc1 tc2 tc3 tc4 tc5 tc7 trw c1 tc6 dackn (sa: io memory) c1 c2 c3 c4 c5 c6 c7 c8 row row tc8 trw1 tpc trw1 h/l h/l c5 row ckio bank prechar g e-sel address cs n dqmn rd/ wr r a s c a ss d31?d0 (read) bs cke note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.44 basic timing of a burst write to sy nchronous dram connecting a 128-mbit/256-mbit synchronous dram with 64-bit bus width (SH7750r only): it is possible to connect 128-mbit or 256-mbit synchronous drams with 64-bit bus width to the SH7750r. ras down mode is also available using a 128 mbytes of external memory space in area 2 or 3. either eight 128-mbit (4 m 8 bit 4 bank) drams or four 256-mbit (4 m 8 bit 4 bank) drams can be connected. figure 13.45 shows an example in which four 256-mbit drams are connected. notes on usage: ? bcr1.dramtp2 ? dramtp0 = 011: sets areas 2 and 3 as synchronous-dram-interface spaces. ? mcr.sz = 00: sets the bus width of the synchronous dram to 64 bits. ? mcr.amx = 6: selects the 128-mbit or 256-mbit address-multiplex setting for the synchronous dram. ? in the auto-refresh operation, the ref command is issued twice continuously in response to a single refresh request. the interv al cycle number between the first and second ref commands issuance is specified by the setting of the tras2?tras0 bits in mcr, which is 4 to 11 ckio
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 495 of 1076 sep 24, 2013 cycles. the interval cycle number between the second ref command and the next actv command issuance is specified by the settings of both the tras2?tras0 bits and the trc2? trc0 bits in mcr in the sum total, which is 4 to 32 ckio cycles. set rtcor and bits cks2?cks0, and mcr so as to satisfy the refresh-interval rating of the synchronous dram which you are using. the synchronous dram auto-refresh timing with 64-bit bus width is shown below figure. ? when setting the mode register of the synchronous dram, set the address for area 2. ? control signals required in this connection are ras , cas , rd/ wr , cs3 , dqm0 ? dqm7, and cke. cs2 is not used. ? do not use partial-sharing mode. if you use this, correct operation is not guaranteed. ckio cke cs 3 ras cass rd/ wr a17 a16 a15?a3 d63?d48 dqm7 dqm6 d47?d32 dqm5 dqm4 d31?d16 dqm3 dqm2 d15?d0 dqm1 dqm0 SH7750r clk cke cs ras cas we bank1 bank0 a12?a0 i/o15?i/o0 dqmu dqml clk cke cs ras cas we bank1 bank0 a12?a0 i/o15?i/o0 dqmu dqml clk cke cs ras cas we bank1 bank0 a12?a0 i/o15?i/o0 dqmu dqml clk cke cs ras cas we bank1 bank0 a12?a0 i/o15?i/o0 dqmu dqml figure 13.45 example of the connection of synchronous dram with 64-bit bus width (256 mbits)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 496 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 trr2 trr3 trr4 mcr.tras[2:0] mcr.tras[2:0] and mcr.trc[2:0] trrw * 1 trr1 trr2 trr3 trr4 trrw * 2 trr1 trc * 2 trc * 2 trc * 2 * 3 trr5 ckio cs 3 rd/ wr ras dqmn bs cke d63 ? d0 cass notes: 1. the interval cycle number between the first and second ref commands is 4 + trrw m (m = 0 to 7) ckio cycles by the setting of the tras[2:0] bits. 2. the interval cycle number between the second ref command and the actv command after the refresh operation is 4 + trrw m (m = 0 to 7) + 3trc n (n = 0 to 7) ckio cycles by the setting of the tras[2:0] bits and the trc[2:0] bits. 3. the next actv command is issued at trr3 to trr5 (including trrw m) + 3trc n (n = 0 to 7) + 1 ckio cycles after second ref command in this refresh operation. this 1 ckio cycle is included in the setting of the tras[2:0] bits. set mcr.tras[2:0], mcr.trc[2:0], rtcor and rtcsr.cks[2:0] so as to satisfy the specification of the synchronous dram. figure 13.46 synchronous dram auto-r efresh timing with 64-bit bus width (tras[2:0] = 001 , trc[2:0] = 001)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 497 of 1076 sep 24, 2013 13.3.6 burst rom interface setting bits a0bst2?a0bst0, a5bst2?a5bst0, and a6bst2?a6bst0 in bcr1 to a non- zero value allows burst rom to be connected to areas 0, 5, and 6. the burst rom interface provides high-speed access to rom that has a burst access function. the timing for burst access to burst rom is shown in figure 13.47. two wait cycl es are set. basically, access is performed in the same way as for sram interface, but when the firs t cycle ends, only the address is changed before the next access is executed. when 8-bit rom is connected, the number of consecutive accesses can be set as 4, 8, 16, or 32 with bits a0bst2?a0bst0, a5bst2?a5bst0, or a6bst2? a6bst0. when 16-bit rom is connected, 4, 8, or 16 can be set in the same way. when 32-bit rom is connected, 4 or 8 can be set. rdy pin sampling is always performed when one or more wait states are set. the second and subsequent access cycles also comprise two cycles when a burst rom setting is made and the wait specification is 0. the timing in this case is shown in figure 13.48. a write operation for the burst rom interface is performed as if the sram interface is selected. in 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed on the data at the 32-byte bo undary. the bus is not released during this period. figure 13.49 shows the timing when a burst rom setting is made, and setup/hold is specified in wcr3.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 498 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 t1 tb1 tb2 tb1 tb2 tb1 tb2 t2 ckio a25?a5 a4?a0 cs n rd/ wr rd d63?d0 (read) bs rdy dackn (sa: io memory) notes: 1. for a write cycle, a basic bus cycle (write cycle) is performed. 2. for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.47 burst rom basic access timing
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 499 of 1076 sep 24, 2013 t1 tw tb2 tb1 tw tb2 tw tw tb1 tb2 tw t2 tb1 ckio a25?a5 a4?a0 cs n rd/ wr rd d63?d0 (read) bs rdy dackn (sa: io memory) notes: 1. for a write cycle, a basic bus cycle (write cycle) is performed. 2. for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.48 burst rom wait access timing
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 500 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio a25?a5 a4?a0 cs n rd/ wr rd d63?d0 (read) bs rdy dackn (sa: io memory) ts1 tb2 th1 ts1 tb1 tb2 ts1 t1 th1 tb1 th1 ts1 tb1 t2 th1 tb2 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.49 burst rom wait access timing 13.3.7 pcmcia interface in this lsi, setting the a56pcm bit in bcr1 to 1 makes the bus interface for external memory space areas 5 and 6 an ic memory card interface or i/o card interface as stipulated in jeida specification version 4.2 (pcmcia2.1). figure 13.50 shows an example of pcmcia card connection to this ls i. to enable active insertion of the pcmcia cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between this lsi's bus interface and the pcmcia cards. as operation in big-endian mode is not explicitly stipulated in the jeida/pcmcia specifications, this lsi supports only a little-endian mode pcmcia interface. in the SH7750, the pcmcia inte rface area can only be accessed when the mmu is used. the pcmcia interface memory space can be set in page units and there is a choice of 8-bit common memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit i/o space, 16-bit i/o space, or dyna mic bus sizing, according to the accessed sa2 to sa0 bits. the setting for wait cycles during a bus access can also be made in mmu page units. when the tc bit to be accessed is cleared to 0, bits a5w2 to a5w0 in wait control register 2 (wcr2), and
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 501 of 1076 sep 24, 2013 bits a5pcw1 and a5pcw0, a5ted2 to a5ted0 , and a5teh2 to a5teh0 in the pcmcia control register (pcr), are select ed. when the tc bit to be accessed is set to 1, bits a6w2 to a6w0 in wait control register 2 (wcr2), and bits a6pcw1 and a6pcw0, a6ted2 to a6ted0, and a6teh2 to a6teh0 in the pcmcia control re gister (pcr), are select ed. for the method of setting bits sa2 to sa0 and b it tc for the page to be acces sed, see section 3, memory management unit (mmu). in the SH7750s and SH7750r, th e pcmcia interface can be accessed even when the mmu is not used. when the mmu is off (mmucr.at=0), access is always performed by means of bits sa2 to sa0 and bit tc in the page table entry assistance register (ptea). when the mmu is on (mmucr.at=1), the situation is the same as for the SH7750. in this lsi, access to a pcmcia interface area by the dmac is always performed using the dmac's chcrn.ssan, chcrn.dsan, chcrn.stc, and chcrn.dtc values. sa2 sa1 sa0 description 0 0 0 reserved (setting prohibited) 1 dynamic i/o bus sizing 1 0 8-bit i/o space 1 16-bit i/o space 1 0 0 8-bit common memory 1 16-bit common memory 1 0 8-bit attribute memory 1 16-bit attribute memory anpcw1?anpcw0 specify the number of wait states to be inse rted in a low-speed bus cycle; a value of 0, 15, 30, or 50 can be set, and this value is added to the number of wait states for insertion specified by wcr2. anted 2?anted0 can be set to a value from 0 to 15, enabling the address, cs , ce2a , ce2b , and reg setup times with respect to the rd and we1 signals to be secured. anteh2?anteh0 can also be set to a value from 0 to 15, enabling the address, cs , ce2a , ce2b , and reg write data hold times with respect to the rd and we1 signals to be secured. wait cycles between cycles are set with bits a5iw2?a5iw0 and a6iw2?a6iw0 in wait control register 1 (wcr1). the inter-cycle write cycles selected depend only on the area accessed (area 5 or 6): when area 5 is accessed, bits a5iw2?a5iw0 are selected, an d when area 6 is accessed, bits a6iw2?a6iw0 are selected.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 502 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 in 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed on the data at the 32-byte bo undary. the bus is not released during this period. table 13.18 relationship between addre ss and ce when usin g pcmcia interface bus width (bits) read/ write access size (bits) * 1 odd/ even iois16 access ce2 ce1 a0 d15?d8 d7?d0 8 read 8 even don't care ? 1 0 0 invalid read data odd don't care ? 1 0 1 invalid read data 16 even don't care first 1 0 0 invalid lower read data even don't care second 1 0 1 invalid upper read data odd don't care ? ? ? ? ? ? write 8 even don't care ? 1 0 0 invalid write data odd don't care ? 1 0 1 invalid write data 16 even don't care first 1 0 0 invalid lower write data even don't care second 1 0 1 invalid upper write data odd don't care ? ? ? ? ? ? 16 read 8 even don't care ? 1 0 0 invalid read data odd don't care ? 0 1 1 read data invalid 16 even don't care ? 0 0 0 upper read data lower read data odd don't care ? ? ? ? ? ? write 8 even don't care ? 1 0 0 invalid write data odd don't care ? 0 1 1 write data invalid 16 even don't care ? 0 0 0 upper write data lower write data odd don't care ? ? ? ? ? ?
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 503 of 1076 sep 24, 2013 bus width (bits) read/ write access size (bits) * 1 odd/ even iois16 access ce2 ce1 a0 d15?d8 d7?d0 read 8 even 0 ? 1 0 0 invalid read data odd 0 ? 0 1 1 read data invalid dynamic bus sizing * 2 16 even 0 ? 0 0 0 upper read data lower read data odd 0 ? ? ? ? ? ? write 8 even 0 ? 1 0 0 invalid write data odd 0 ? 0 1 1 write data invalid 16 even 0 ? 0 0 0 upper write data lower write data odd 0 ? ? ? ? ? ? read 8 even 1 ? 1 0 0 invalid read data odd 1 first 0 1 1 ignored invalid odd 1 second 1 0 1 invalid read data 16 even 1 first 0 0 0 invalid lower read data even 1 second 1 0 1 invalid upper read data odd 1 ? ? ? ? ? ? write 8 even 1 ? 1 0 0 invalid write data odd 1 first 0 1 1 invalid write data odd 1 second 1 0 1 invalid write data 16 even 1 first 0 0 0 upper write data lower write data even 1 second 1 0 1 invalid upper write data odd 1 ? ? ? ? ? ? notes: 1. in 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address incrementing performed automatically according to the bus width, until the transfer data size is reached. 2. pcmcia i/o card interface only
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 504 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 g a25?a0 d15?d0 cd1, cd2 c e1 g c e 2 o e w e / p g m ( i ord ) ( i owr ) ( i o i s 1 6 ) w ait a25?a0 d15?d0 cd1, cd2 c e1 c e 2 o e w e / p g m w ait a25?a0 SH7750 SH7750s SH7750r d15?d0 rd/ wr c e 2b c e 2 a rd w e1 c e1 b /( cs6 ) c e1a /( cs 5 ) i c i ord i c i owr rdy i o i s 1 6 g dir d7?d0 d15 ? d8 g dir g g g dir g dir d7?d0 d15 ? d8 output port r e g r e g r e g pc card (memory i/o) pc card (memory i/o) card detection circuit card detection circuit figure 13.50 example of pcmcia interface
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 505 of 1076 sep 24, 2013 memory card interface basic timing: figure 13.51 shows the basic timing for the pcmcia ic memory card interface, and figure 13.52 shows the pcmcia memory card interface wait timing. ckio tpcm1 tpcm2 a25?a0 c exx rd/ wr d15?d0 (read) d15?d0 (write) rd (read) w e1 (write) bs dackn (da) r e g note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.51 basic timing for pcmcia memory card interface
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 506 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio tpcm0 a25?a0 rd/ wr c exx r e g rd (read) d15?d0 (read) d15?d0 (write) w e1 (write) bs rdy dackn (da) notes: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. * SH7750s, SH7750r only tpcm0w tpcm1 tpcm1w tpcm1w tpcm2 tpcm2w * figure 13.52 wait timing for pcmcia me mory card interface
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 507 of 1076 sep 24, 2013 common memory 1 common memory (64 mb) attribute memory (64 mb) i/o space (64 mb) attribute memory i/o space 1 i/o space 2 virtual address space card 1 on cs5 card 2 on cs6 access by cs5 wait controller virtual address space physical i/o addresses io 1 io 1 different virtual pages mapped to the same physical page example of i/o spaces with different cycle times (less than 1 kb) the page size can be 1 kb, 4 kb, 64 kb, or 1 mb. example of pcmcia interface mapping io 2 io 2 1 kb page 1 kb page common memory 2 access by cs6 wait controller . . . . . . figure 13.53 pcmcia space allocation i/o card interface timing: figures 13.54 and 13.55 show the timing for the pcmcia i/o card interface. when an i/o card interface access is made to a pcmcia card in little-endian mode, dynamic sizing of the i/o bus width is possible using the iois16 pin. when a 16-bit bus width is set, if the iois16 signal is high during a word-size i/o bus cycle, the i/o port is recognized as being 8 bits in width. in this case, a data access for only 8 bits is performed in the i/o bus cycle being executed, followed automatically by a data access for the remaining 8 bits. dynamic bus sizing is also performed in the case of byte-size access to address 2n + 1. figure 13.56 shows the basic timing for dynamic bus sizing.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 508 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio tpci1 tpci2 a25?a0 rd/ wr c exx i c i ord (read) d15?d0 (read) i c i owr (write) d15?d0 (write) bs dackn (da) r e g note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.54 basic timing fo r pcmcia i/o card interface
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 509 of 1076 sep 24, 2013 ckio a25?a0 rd/ wr c exx i c i ord (read) i c i owr (write) dackn (da) d15?d0 (read) d15?d0 (write) bs rdy i o i s 1 6 tpci0 tpci0w tpci1 tpci1w tpci1w tpci2 tpci2w r e g note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.55 wait timing fo r pcmcia i/o card interface
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 510 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tpci tpci0 tpci1w tpci2 tpci2w tpci0 tpci tpci2 tpci1w tpci2w ckio a25?a1 a0 rd/ wr i ord ( w e 2 ) (read) i owr ( w e3 ) (write) d15?d0 (write) d15?d0 (read) bs i o i s 1 6 c exx r e g ( w e 7 ) rdy dackn (da) note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.56 dynamic bus sizing ti ming for pcmcia i/o card interface
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 511 of 1076 sep 24, 2013 13.3.8 mpx interface if the md6 pin is set to 0 in a power-on reset by the reset pin, the mpx interface for normal memory is selected for area 0. the mpx interface is selected fo r areas 1 to 6 by means of the mpx bit in bcr1 and the memmode, a4mpx, and aimpx bits in bcr3. the mpx interface offers a multiplexed address/data type bus protocol, and permits easy connection to an external memory controller chip that uses a single 32-bit multiplexed address/data bus. a bus cycle consists of an address phase and a data phase. in the address phase, th e address information is output to d25 ? d0, and the access size to d63 ? d61 and d31?d29*. the bs signal which indicates the address ph ase is asserted for one cycle. the csn signal is asserted at the rise of t m1 , and negated after the last data transf er in the data phase. therefore, a negate period does not exist for access with the minimum pitch. the frame signal is asserted at the rise of t m1 , and negated when the cycle of the last da ta transfer starts in the data phase. therefore, in an external de vice supporting the mpx interface, the address information and access size output in the address phase must be sa ved in the external device memory, and data corresponding to the data phase must be input or output. for details of access sizes and data alignment, see section 13.3.1, endian/access size and data alignment. the address pins output at a25?a0 are undefined. 32-byte transfer performed consecutively for a total of 32 bytes according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed on the data at the 32-byte bo undary. when the access si ze is larger than the data bus width, as in this case, burst access is ge nerated, with the address output once, followed by multiple data cycles. the bus is not released during this period. note: * SH7750r only. d63 d62 d61 access size 0 0 0 byte 1 word 1 0 longword 1 quadword 1 x x 32-byte burst legend: x: don't care
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 512 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio cs n bs rd / frame rd/ wr d63?d0 rdy SH7750, SH7750s, SH7750r mpx device clk cs bs frame we i/o63?i/o0 rdy figure 13.57 example of 64-bit data width mpx connection the mpx interface timing is shown below. when the mpx interface is used for areas 1 to 6, a bu s size of 32 or 64 bits should be specified in bcr2. for wait control, waits specified by wcr2 and wait insertion by means of the rdy pin can be used. in a read, one wait cycle is automatically inserted after address output, even if wcr2 is cleared to 0.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 513 of 1076 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d63?d0 bs tmd1w tmd1 rdy dackn (da) d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.58 mpx interface timing 1 (single read cycle, anw = 0, no external wait, bus width: 64 bits)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 514 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d63?d0 bs tmd1w tmd1w tmd1 rdy dackn (da) d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.59 mpx interface timing 2 (single read, anw = 0, one external wait inserted, bus width: 64 bits)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 515 of 1076 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d63?d0 bs tmd1 rdy dackn (da) d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.60 mpx interface timing 3 (single write cycle, anw = 0, no wait, bus width: 64 bits)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 516 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d63?d0 bs tmd1w tmd1w tmd1 rdy dackn (da) d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.61 mpx interface timing 4 (single write, anw = 1, one external wait inserted, bus width: 64 bits)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 517 of 1076 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d63?d0 bs tmd1w tmd1 tmd2 tmd3 tmd4 rdy dackn (da) d1 d2 d3 d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the figure 13.62 mpx interface timing 5 (burst read cycle, anw = 0, no external wait, bus width: 64 bits, transfer data size: 32 bytes)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 518 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d63?d0 bs tmd1w tmd1 tmd2w tmd2 tmd3 tmd4w tmd4 rdy dackn (da) d3 d1 d2 d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.63 mpx interface timing 6 (burst read cycle, anw = 0, external wait control, bus width: 64 bits, transfer data size: 32 bytes)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 519 of 1076 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d63?d0 bs tmd1 tmd2 tmd3 tmd4 rdy dackn (da) d0 d1 d2 d3 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.64 mpx interface timing 7 (burst write cycle, anw = 0, no ex ternal wait, bus width: 64 bits, transfer data size: 32 bytes)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 520 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 d2 d1 tm1 ckio a rd / f r ame cs n rd/ wr d63?d0 bs tmd1w tmd1 tmd2w tmd2 tmd3 tmd4w tmd4 rdy dackn (da) d3 d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.65 mpx interface timing 8 (burst write cycle, anw = 1, external wait control, bus width: 64 bits, transfer data size: 32 bytes)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 521 of 1076 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d31?d0 bs tmd1w tmd1 tmd2 rdy dackn (da) d1 d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.66 mpx interface timing 9 (burst read cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 64 bits)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 522 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d31?d0 bs tmd1w tmd1w tmd1 tmd2 rdy dackn (da) d1 d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.67 mpx interface timing 10 (burst read cycle, anw = 0, one external wait inserted, bus width: 32 bits, transfer data size: 64 bits)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 523 of 1076 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d31?d0 bs tmd1 tmd2 rdy dackn (da) d0 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.68 mpx interface timing 11 (burst write cycle, anw = 0, no ex ternal wait, bus width: 32 bits, transfer data size: 64 bits)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 524 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d31?d0 bs tmd1w tmd1w tmd1 tmd2 rdy dackn (da) d0 d1 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.69 mpx interface timing 12 (burst write cycle, anw = 1, one external wait inserted, bus width: 32 bits, transfer data size: 64 bits)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 525 of 1076 sep 24, 2013 tm1 ckio rd / f r ame cs n rd/ wr d31?d0 bs tmd1w tmd1 tmd2 tmd3 tmd4 tmd5 tmd6 tmd7 tmd8 rdy dackn (da) d1 d2 d3 d0 d5 d6 d7 d4 a note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.70 mpx interface timing 13 (burst read cycle, anw = 0, no external wait, bus width: 32 bits, transfer data size: 32 bytes)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 526 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d31?d0 bs tmd1w tmd1 tmd2w tmd2 tmd3 tmd7 tmd8w tmd8 rdy dackn (da) d6 d7 d1 d2 d0 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.71 mpx interface timing 14 (burst read cycle, anw = 0, external wait control, bus width: 32 bits, transfer data size: 32 bytes)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 527 of 1076 sep 24, 2013 tm1 ckio a rd / f r ame cs n rd/ wr d31?d0 bs tmd1 tmd2 tmd3 tmd4 tmd5 tmd6 tmd7 tmd8 rdy dackn (da) d0 d1 d2 d3 d4 d5 d6 d7 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.72 mpx interface timing 15 (burst write cycle, anw = 0, no ex ternal wait, bus width: 32 bits, transfer data size: 32 bytes)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 528 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 d2 d1 tm1 ckio a rd / f r ame cs n rd/ wr d31?d0 bs tmd1w tmd1 tmd2w tmd2 tmd3 tmd7 tmd8w tmd8 rdy dackn (da) d0 d6 d7 note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.73 mpx interface timing 16 (burst write cycle, anw = 1, external wait control, bus width: 32 bits, transfer data size: 32 bytes)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 529 of 1076 sep 24, 2013 13.3.9 byte control sr am interface the byte control sram interface is a memory interface that outputs a byte select strobe ( wen ) in both read and write bus cycles. it has 16 bit data pins, and can be connected to sram which has an upper byte select strobe and lower byte select strobe function such as ub and lb. areas 1 and 4 can be designated as byte contro l sram interface. however, when these areas are set to mpx mode, mpx mode has priority. the byte control sram interface write timing is the same as fo r the normal sram interface. in read operations, the wen pin timing is different. in a read access, only the we signal for the byte being read is asserted. assertion is synchronized with the fall of the ckio clock, as for the we signal, while negation is synchronized with the rise of the ckio clock, using the same timing as the rd signal. in 32-byte transfer such as a cache fill or c opy-back, a total of 32 bytes are transferred consecutively according to the set bus width. the first access is pe rformed on the data for which there was an access request, and the remaining acce sses are performed on the data at the 32-byte boundary. the bus is not released during this period. figure 13.74 shows an example of byte control sram connection to this lsi, and figures 13.75 to 13.77 show examples of byte control sram read cycle.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 530 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 a18?a3 cs n rd rd/ wr d63?d48 we7 we6 SH7750, SH7750s, SH7750r 64k 16-bit sram a15?a0 cs oe we i/o15?i/o0 u b lb d15 ? d0 we1 we0 a15?a0 cs oe we i/o15?i/o0 u b lb a15?a0 cs oe we i/o15?i/o0 u b lb a15?a0 cs oe we i/o15?i/o0 u b lb d31 ? d16 we 3 we2 d47 ? d32 we5 we4 figure 13.74 example of 64-bit data width byte control sram
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 531 of 1076 sep 24, 2013 t1 t2 ckio a25?a0 cs n rd/ wr rd d63?d0 (read) bs dackn (sa: io memory) dackn (da) rdy w en note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.75 byte control sram basic re ad cycle (no wait)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 532 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 t1 tw t2 ckio a25?a0 cs n rd/ wr rd d63?d0 (read) bs dackn (sa: io memory) dackn (da) rdy w en note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.76 byte contro l sram basic read cycle (o ne internal wait cycle)
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 533 of 1076 sep 24, 2013 t1 tw twe t2 ckio a25?a0 cs n rd/ wr rd d63?d0 (read) bs dackn (sa: io memory) dackn (da) rdy w en note: for dackn, an example is shown where chcrn.al (access level) = 0 for the dmac. figure 13.77 byte co ntrol sram basic read cycle (one internal wait + one external wait)
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 534 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.3.10 waits between access cycles a problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and so resulting in lower reliability or incorrect operation. to avoid this problem, a data collision prevention feature has been provided. this memorizes the preceding access area and the kind of read/write, and if there is a possibi lity of a bus collision when the next access is started, inserts a wait cycle before the access cycle to prevent a data collision. wait cycle inser tion consists of insertin g idle cycles between access cycles, as shown in section 13.2.5, wait control register (wcr1). when this lsi performs consecutive write cycles, the data transfer direction is fi xed (from this lsi to other memory) and there is no problem. with read accesses to the same area, also, in principle da ta is output from the same data buffer, and wait cycle insertion is not performed. if there is originally space be tween accesses, according to the setting of bits aniw2?aniw0 (n = 0 to 6) in wcr1 , the number of idle cy cles inserted is the specified number of idle cycles minus the number of empty cycles. when bus arbitration is performed, the bus is re leased after waits are inserted between cycles. in single address mode dma transfer, when data transfer is performed from an i/o device to memory the data on the bus is determined by the speed of the i/o device. with a low-speed i/o device, an inter-cycle idle wait equivalent to the ou tput buffer turn-off time must be inserted. even with high-speed memory, when dma transfer is cons idered, it may be necessary to insert an inter- cycle wait to adjust to the speed of a low-speed de vice, preventing the memory from being used at full speed. bits dmaiw2?dmaiw0 in wait control register 1 (wcr1) allow an inter-cycle wait setting to be made when transferring data from an i/o device to memory using single address mode dma transfer. from 0 to 15 waits can be inserted. the number of waits specified by dmaiw2? dmaiw0 are inserted in single ad dress dma transfers to all areas. in dual address mode dma transf er, the normal inter-cycle wait specified by aniw2?aniw0 (n = 0 to 6) is inserted.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 535 of 1076 sep 24, 2013 t1 c ki o cs m cs n a25?a0 bs rd/ wr rd d31?d0 t2 twait t1 t2 twait t1 t2 area m space read area m inter-access wait specification area n inter-access wait specification area n space read area n space write figure 13.78 waits between access cycles
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 536 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 13.3.11 bus arbitration this lsi is provided with a bus arbitration functio n that grants the bus to an external device when it makes a bus request. there are three bus arbitration modes: master mo de, partial-sharing master mode, and slave mode. in master mode the bus is held on a constant basis, and is released to another device in response to a bus request. in slave mode the bus is not held on a constant basis; a bus request is issued each time an external bus cycle occurs, and the bus is re leased again at the end of the access. in partial- sharing master mode, only area 2 is shared with external devices; slave mode is in effect for area 2, while for other spaces, bus arbitration is not performed and the bus is held constantly. the area in the master mode chip to which area 2 in the pa rtial-sharing master mode chip is allocated is determined by an external circuit. master mode and slave mode can be specified by the external mode pins. partial-sharing master mode is entered from master mode by means of a software setting. see appendix c, mode pin settings, for the external mode pin settings. in ma ster mode and slave mode , the bus goes to the high-impedance state when not being held. in partial-sharing master mode, the bus is constantly driven, and therefore an external buffer is necessa ry for connection to the master bus. in master mode, it is possible to connect an external device that issues bus requests instead of a slave mode chip. in the following description, an external devi ce that issues bus requests is also referred to as a slave. this lsi has two internal bus masters: the cpu and the dmac. when synchronous dram or dram is connected and refresh control is performed, refresh requests constitute a third bus master. in addition to these are bus requests from external devices in master mode. if requests occur simultaneously, priority is given, in high-to-low order, to a bus request from an external device, a refresh request, the dmac, and the cpu. to prevent incorrect operation of connected devices when the bus is transferred between master and slave, all bus control signals are negated befo re the bus is released. when mastership of the bus is received, also, bus contro l signals begin driving the bus from the negate d state. since signals are driven to the same value by the mast er and slave exchanging the bus, output buffer collisions can be avoided. bus transfer is executed between bus cycles. when the bus release request signal ( breq ) is asserted, this lsi releases the bus as soon as the currently executin g bus cycle ends, and outputs the bus use permission signal ( back ). however, bus release is not performed during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing long word access to 8-bit bus width
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 537 of 1076 sep 24, 2013 memory) or during a 32-byte transf er such as a cache fill or write-b ack. in addition, bus release is not performed between read and write cycles duri ng execution of a tas in struction, or between read and write cycles when dmac dual address transfer is executed. when breq is negated, back is negated and use of the bus is resumed. see appendix e, pin functions, for the pin states when the bus is released. when a refresh request is generated, this lsi perf orms a refresh operation as soon as the currently executing bus cycle ends. however, refresh operations are deferred during multiple bus cycles generated because the data bus width is smal ler than the access size (for example, when performing longword access to 8-bit bus width memo ry) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a tas instruction, and between read an d write cycles when dmac dual address transfer is executed. refresh operations are also deferr ed in the bus-released state. if the synchronous dram interface is set to the ras down mode the pall command is issued before a refresh cycle occurs or before the bus is released by bus arbitration. as the cpu in this lsi is connected to cache me mory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside this lsi. when writing from the cpu, an external write cycle is generated when write- through has been set for the cache in this lsi, or when an access is made to a cache-off area. there is consequently a delay until the bus is returned. when this lsi wants to take back the bus in resp onse to an internal memory refresh request, it negates back . on receiving the back negation, the device that asse rted the external bus release request negates breq to release the bus. the bus is thereb y returned to this lsi, which then carries out the necessary processing.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 538 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 hiz hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z ckio hi-z br eq b a c k a25?a0 cs n rd/ wr rd w en d63?d0 (write) bs br eq / bs a c k b a c k / bsr eq a25?a0 cs n rd/ wr rd w en d63?d0 (write) bs master access slave access master access asserted for at least 2 cycles ne g ated within 2 cycles hi-z hi-z hi-z hi-z hi-z hi-z master mode device access must be asserted for at least 2 cycles must be ne g ated within 2 cycles slave mode device access figure 13.79 arbitration sequence
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 539 of 1076 sep 24, 2013 13.3.12 master mode the master mode processor holds the bus itself unless it receives a bus request. on receiving an assertion (low le vel) of the bus request signal ( breq ) from off-chip, the master mode processor releases the bus and asserts (d rives low) the bus use permission signal ( back ) as soon as the currently executing bu s cycle ends. if a bus release reque st due to a refresh request has not been issued, on receiving the breq negation (high level) indicati ng that the slave has released the bus, the processor negates (drives high) the back signal and resumes use of the bus. if a bus request is issued due to a memory refresh request in the bus-releas ed state, the processor negates the bus use permission signal ( back ), and on receiving the breq negation indicating that the slave has released the bus, resumes use of the bus. when the bus is released, all bus interface related output signals and input/ output signals go to the high-impedance state, except for the synchronous dram interface cke signal and bus arbitration back signal, and dack0 and dack1 which control dma transfers. with dram, the bus is released after precharging is completed. with synchronous dram, also, a precharge command is issued fo r the active bank and the bus is released after precharging is completed. the actual bus release sequence is as follows. first, the bus use permission signal is asserted in synchronization with the rising edge of the clock. the address bus and data bus go to the high-impedance state in synchronization with the next rising edge of the clock after this back assertion. at the same time, the bus control signals ( bs , csn , ras1 , ras2 , wen , rd , rd/ wr , rd2 , rd/ wr2 , ce2a , and ce2b ) go to the high- impedance state. these bus control signals are negated no later than one cycle before going to high-impedance. bus request signal sampling is performed on the rising edge of the clock. the sequence for re-acquiring the bu s from the slave is as follows. as soon as breq negation is detected on the rising edge of the clock, back is negated and bus control signal driving is started. driving of the address bus and data bus starts at the next rising edge of an in-phase clock. the bus control si gnals are asserted and the bus cycle is actually started, at the earliest, at the clock rising edge at which the address and data signals are driven. in order to reacquire the bus and start executi on of a refresh operation or bus access, the breq signal must be negated for at least two cycles.
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 540 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 if a refresh request is generated when back has been asserted and the bus has been released, the back signal is negated even while the breq signal is asserted to request the slave to relinquish the bus. when this lsi is used in master mode, consecutive bus accesses may be attempted to reduce the overhead due to arbitra tion in the case of a slave design ed independently by the user. when connecting a slave for which the total dura tion of consecutive accesses exceeds the refresh cycle, the design should provide for the bus to be released as soon as possible after negation of the back signal is detected. 13.3.13 slave mode in slave mode, the bus is normally in the released state, and an external device cannot be accessed unless the bus is acquired through execution of the bus arbitration sequence. in a reset, also, the bus-released state is established and the bus arbitration sequence is started from the reset vector fetch. to acquire the bus, the slave device asserts (drives low) the bsreq signal in synchronization with the rising edge of the clock. the bus use permission bsack signal is sampled for assertion (low level) in synchronization with the rising edge of the clock. when bsack assertion is detected, the bus control signals and address bus ar e immediately driven at the negated level. the bus cycle is started at the next rising edge of the clock. the last signal negated at the end of the access cycle is synchronized with the rising edge of the clock. when the bus cycle ends, the bsreq signal is negated and the release of the bus is reported to the master. on the next rising edge of the clock, the control signals are set to high-impedance. in order for the slave mode processor to begin access, the bsack signal must be asserted for at least two cycles. for a slave access cycle in dram or synchronous dram, the bus is released on completion of precharging, as in the case of the master. refresh control is left to the master mode device, and any refresh control settings made in slave mode are ignored. do not use dram/synchronous dram ras down mode in slave mode. synchronous dram mode register settings should be made by the master mode device. do not use the dmac's ddt mode in slave mode.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 541 of 1076 sep 24, 2013 13.3.14 partial-sharing master mode in partial-sharing master mode, area 2 only is shared with other devices, and other areas can be accessed at all times. partial-sharing master mode can be set by setting master mode with the external mode pins, and setting the pshr bit to 1 in bcr1 in the initialization procedure in a power-on reset. do not access area 2 until these se ttings have been performe d. in a manual reset the bus state controller setting register values are retained, and so need not be set again. partial-sharing master mode is designed for use in conjunction with a master mode chip. the partial-sharing master can access a device on the ma ster side via area 2, but the master cannot access a device on the partial-sharing master side. an address and control signal buffer and a data buffer must be located between the partial-sharing master and the master, and controll ed by a buffer control circuit. the partial-sharing master mode pr ocessor uses the followi ng procedure to access area 2. it asserts the bsreq signal on the rising edge of the clock, and issues a bus request to the master. it samples bsack on each rising edge of th e clock, and on receiving bsack assertion, starts the access cycle on the next rising edge of the clock. at the end of the access, it negates bsreq on the rising edge of the clock. buffer control in an access to an area 2 device by the partial-sharing master is carried out by referencing the cs2 signal or bsreq and bsack signals on the partial- sharing master side. permission to use the bus is reported by the bsack line connected to the partial-sharing master, but the master may also negate the bsack signal even while the bus is being used, if it needs the bus urgently in order to service a refresh, for example. consequently, the partial-sharing master has to monitor the bsreq signal to see whether it can continue to use the bus after detecting bsack assertion. in the case of the addr ess buffer, after the address buffer is turned on when bsack assertion is detected, the buffer is kept on until bsreq is negated, at which point it is turned off. if the turning-off of th e buffer used is late, resulting in a collision with the start of an access cycle on the master side, the bsreq signal output from the partial-sharing master must be routed through a delay circuit as part of the buffer control circuit, and input to the master breq signal. in order for a partial-sharing master mo de processor to begin area 2 access, the bsack signal must be asserted for at least two cycles. when the bus is released after area 2 has been accesse d in partial-sharing master mode, if area 2 is synchronous dram, there is a wait of the period required for auto-precharge before bus release is performed. in partial-sharing master mode, refreshing is not performed for area 2 (refresh requests are ignored).
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 542 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 do not use dram/synchronous dram ras down mode in partial-sharing master mode. area 2 synchronous dram mode register settings should be made by the master mode device. set partial-sharing master mode (by setting the pshr bit to 1 in bcr1) after completion of the area 3 synchronous dram mode register settings. in partial-sharing master mode, dma transfer should not be performed on area 2, and the dmac's ddt mode should not be used. 13.3.15 cooperation between master and slave to enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. before dram or synchronous dram is used, initialization operations must be carried out. resp onsibility must also be assigned when a standby operation is performed to implement the power-down state. the design of this lsi provides for all control, including initialization, refreshing, and standby control, to be carried out by the master mode device. in a dual-processor configuration using direct master/slave connection, all processing except di rect access to memory is handled by the master. in a combination of master mode and partial-sh aring master mode, the partial-sharing master mode processor performs initializa tion, refreshing, and standby control for the areas connected to it, with the exception of area 2, while the master performs initialization of the memory connected to it. if this lsi is specified as the master in a power- on reset, it will not accep t bus requests from the slave until the breq enable bit (bcr1.breqen) is set to 1. to ensure that the slave processo r does not access memory requiring initialization before use, such as dram and synchronous dram, until initialization is completed, write 1 to the breq enable bit after initialization ends. before setting self-refresh mode in standby mode, etc., write 0 to the breq enable bit to invalidate the breq signal from the sl ave. write 1 to the breq enable bit only after the master has performed the necessary pro cessing (refresh settings, etc.) for exiting self-refresh mode.
SH7750, SH7750s, SH7750r group section 13 bus state controller (bsc) r01uh0456ej0702 rev. 7.02 page 543 of 1076 sep 24, 2013 13.3.16 notes on usage refresh: auto refresh operations stop when a transition is made to standby mode, hardware standby mode or deep-sleep mode. if the memory system requires refresh operations, set the memory in the self-refresh state prior to making th e transition to standby mode, hardware standby mode or deep-sleep mode. bus arbitration: on transition to standby mode or deep-sleep mode, the processor in master mode does not release bus privileges. in systems performing bus arbitration, make the transition to standby mode or deep-sleep mode only after setting the bus privilege release enable bit (bcr1.breqen) to 0 for the processor in master mode. if the bus privilege release enable bit remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or deep-sleep mode. synchronous dram mode register setting (SH7750, SH7750s only): the following conditions must be satisfied when setting the synchronous dram mode register. ? the dmac must not be activated until synchronous dram mode register setting is completed.* 1 ? register setting for the on-chip peripheral modules* 2 must not be performed until synchronous dram mode register setting is completed.* 3 notes: 1. if a conflict occurs between synchronous dram mode register setting and memory access using the dmac, neither operation can be guaranteed. 2. this applies to the following on-chip peripheral modules: cp g, rtc, intc, tmu, sci, scif, and h-udi. 3. if synchronous dram mode register setting is performed immediately following write access to the on-chip peripheral modules* 2 , the values written to the on-chip peripheral modules cannot be guaranteed. note that following power-on, synchronous dram mode register settings should be perf ormed before accessing synchronous dram. after making mode register settings, do not change them. bsreq output in partial- sharing master mode: when conditions a. to d. below are all satisfied, the bsreq pin may be driven low during a refresh operation and a bus release request issued to the master mode device, even though there was no request to access area 2. the period that bsreq is asserted is 3 to 21 ckio cycles, as specified by the setting of mcr.trc (see d. below).
section 13 bus state controller (bsc) SH7750, SH7750s, SH7750r group page 544 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 conditions under which problem occurs a. the partial-sharin g master mode is selected (bcr1.pshr = 1). b. refresh is enabled for ar ea 3 (bcr1.dramtp[2:0] = 010, 011, or 101; mcr.rfsh = 1; mcr.rmode = 0). c. except for refresh requests, no requests to access external memory (chip-internal requests by the cpu or dmac to access areas 0 to 6) have been issued to the bus status controller following access to the shared area, area 2. d. mcr.trc is set to a value other than 0 (mcr.trc[2:0] 000). example: if the refresh cycle is approximately 4,096 times/64 ms , one refresh takes place every 15 s or so. therefore, the master mode device?s bu s performance may be decreased by 3 to 21 ckio cycles every 15 s or so when the mast er mode device responds to a bus request. in addition, if the master mode device is using the bus when bsreq is asserted, bsack may not be asserted immediately. in this case the above problem has little effect on the master mode device. workarounds: methods 1. or 2. below can be used as workarounds if degradation of the bus performance of the master mode device due to the phenomenon described above poses a problem. 1. set mcr.trc[2:0] to 0 0 0. 2. store the program in an area other than ar ea 2, and insert an in struction to perform a dummy access to external memory (area 0, 1, or 3 to 6) immediately after the instruction accessing area 2.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 545 of 1076 sep 24, 2013 section 14 direct memory access controller (dmac) 14.1 overview the SH7750 and SH7750s include an on-chip four-channel di rect memory access controller (dmac). the SH7750r includes an on-chip eight-channel dmac. the dmac can be used in place of the cpu to perform high-speed data tr ansfers among external devices equipped with dack (tmu, sci, scif), external memories, memory-mapped external devices, and on-chip peripheral modules (except the dmac, bsc, and ubc). using the dmac re duces the burden on the cpu and increases the operating efficiency of the chip. when using the SH7750r, see the following sections: section 14.6, configuration of dmac (SH7750r); section 14.7, register descriptions (SH7750r); section 14.8, operation (SH7750r). 14.1.1 features the dmac has the following features. ? four channels (SH7750/SH7750s), eight channels (SH7750r) ? physical address space ? choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length ? maximum of 16 m (16,777,216) transfers ? choice of single or dual address mode ? single address mode: either the transfer source or the transfer destination (external device) is accessed by a dack signal while the other is accessed by address. one data transfer is completed in one bus cycle. ? dual address mode: both the transfer source and transfer destination are accessed by address. values set in dmac internal regi sters indicate the accessed address for both the transfer source and the transf er destination. two bus cycles are required for one data transfer. ? choice of bus mode: cycle steal mode or burst mode ? two types of dmac channel priority ranking: ? fixed priority mode: channel pr iorities are permanently fixed. ? round robin mode: sets the lowest priority for the channel for which an execution request was last accepted. ? an interrupt request can be sent to the cpu on completion of the specified number of transfers.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 546 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? transfer requests: the following three dmac transfer activation requ ests are supported. ? external request (1) normal dma mode from two dreq pins. either low level detection or falling edge detection can be specified. external requests can be accepted on channels 0 and 1 only. (2) on-demand data transfer mode (ddt mode) in this mode of the SH7750 and SH7750s, interfacing between an external device and the dmac is performed using the dbreq , bavl , tr , tdack , id [1:0], and d [63:0] pins. external requests can be accepted on all four channels. in the SH7750r, the dbreq , bavl , tr , tdack , id [2:0], and d [63:0] pins are used as the interface between an external device and the dmac. external requests can be accepted on any of the eight channels. for channel 0, data transfer can be carried out with the transfer mode, number of transfers, transfer address (single only), etc., speci fied by the external device. although channel 0 has no request queue, th ere are four request queues for each of the other channels: i.e., channels 1 to 3 in the SH7750 or SH7750s, and channels 1 to 7 in the SH7750r. in the SH7750r, request queues can be cleared on a channel-by-channel basis in ddt mode in either of the following two ways. ? clearing a request queue by dtr format the request queues of the relevant channel are cleared when it receives dtr.sz = 110, dtr.id = 00, dtr.md = 11, and dtr.count [7:4]* = [1 ? 8]. ? using software to clear the request queue the request queues of the relevant cha nnel are cleared by writing a 1 to the chcrn.qcl bit (reques t-queue clear bit) of each channel. note: * dtr.count [7:4] (dtr [55:52]): sets the port as not used. ? requests from on-chip peripheral modules transfer requests from the sci, scif, and tmu. these can be accepted on all channels. ? auto-request the transfer request is generated automatically within the dmac. ? channel functions: transfer modes that can be set are different for each channel. ? normal dma mode ? channel 0: single or dual address mode. external requests are accepted. ? channel 1: single or dual address mode. external requests are accepted. ? channel 2: dual ad dress mode only. ? channel 3: dual ad dress mode only.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 547 of 1076 sep 24, 2013 ? channel 4 (SH7750r only): dual address mode only. ? channel 5 (SH7750r only): dual address mode only. ? channel 6 (SH7750r only): dual address mode only. ? channel 7 (SH7750r only): dual address mode only. ? ddt mode channel function ? channel 0: single address mode . external requests are accepted dual address mode (SH7750s, SH7750r) ? channel 1: single or dual address m ode. external requests are accepted. ? channel 2: single or dual address m ode. external requests are accepted. ? channel 3: single or dual address m ode. external requests are accepted. ? channel 4 (SH7750r only): single or dual address mode. external requests are accepted. ? channel 5 (SH7750r only): single or dual address mode. external requests are accepted. ? channel 6 (SH7750r only): single or dual address mode. external requests are accepted. ? channel 7 (SH7750r only): single or dual address mode. external requests are accepted. 14.1.2 block diagram (SH7750, SH7750s) figure 14.1 shows a block diagram of the dmac.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 548 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 sarn darn dmatcrn chcrn dmaor tmu sci, scif dack0, dack1 drak0, drak1 le g end: dmaor: dmac operation re g ister sarn: dmac source address re g ister darn: dmac destination address re g ister dmatcrn: dmac transfer count re g ister chcrn: dmac channel control re g ister note: n = 0 to 3 on-chip peripheral module peripheral bus internal bus dmac module count control re g ister control activation control request priority control bus interface 32b data buffer bus state controller ch0 ch1 ch2 ch3 request controller dtr command buffer ddt module sar0, dar0, dmatcr0, chcr0 only external bus bavl tdack id[1:0] d[63:0] ddtmode dbreq bavl request 4 48 bits tr dbreq tdack id[1:0] ddtd dreq0 , dreq1 external address/on-chip peripheral module address figure 14.1 block diagram of dmac
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 549 of 1076 sep 24, 2013 14.1.3 pin configuration (SH7750, SH7750s) tables 14.1 and 14.2 show the dmac pins. table 14.1 dmac pins channel pin name a bbreviation i/o function 0 dma transfer request dreq0 input dma transfer request input from external device to channel 0 dreq acceptance confirmation drak0 output acceptance of request for dma transfer from channel 0 to external device notification to exte rnal device of start of execution dma transfer end notification dack0 output strobe output to external device of dma transfer request from channel 0 to external device 1 dma transfer request dreq1 input dma transfer request input from external device to channel 1 dreq acceptance confirmation drak1 output acceptance of request for dma transfer from channel 1 to external device notification to exte rnal device of start of execution dma transfer end notification dack1 output strobe output to external device of dma transfer request from channel 1 to external device
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 550 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 14.2 dmac pins in ddt mode pin name abbreviation i/o function data bus request dbreq ( dreq0 ) input data bus release request from external device for dtr format input data bus available bavl (drak0) output data bus release notification data bus can be used 2 cycles after bavl is asserted transfer request signal tr ( dreq1 ) input if asserted 2 cycles after bavl assertion, dtr format is sent only tr asserted: dma request dbreq and tr asserted simultaneously: direct request to channel 2 dmac strobe tdack (dack0) output reply strobe signal for external device from dmac channel number notification id [1:0] (drak1, dack1) output notification of channel number to external device at same time as tdack output (id [1] = drak1, id [0] = dack1) 14.1.4 register configuration (SH7750, SH7750s) table 14.3 summarizes the dmac re gisters. the dmac has a total of 17 registers: four registers are allocated to each channel, and an additional co ntrol register is shared by all four channels. table 14.3 dmac registers chan- nel name abbre- viation read/ write initial value p4 address area 7 address access size 0 dma source address register 0 sar0 r/w * 2 undefined h'ffa00000 h'1fa00000 32 dma destination address register 0 dar0 r/w * 2 undefined h'ffa00004 h'1fa00004 32 dma transfer count register 0 dmatcr0 r/w * 2 undefined h'ffa00008 h'1fa00008 32 dma channel control register 0 chcr0 r/w * 1 * 2 h'00000000 h'ffa0000c h'1fa0000c 32
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 551 of 1076 sep 24, 2013 chan- nel name abbre- viation read/ write initial value p4 address area 7 address access size 1 dma source address register 1 sar1 r/w undefined h'ffa00010 h'1fa00010 32 dma destination address register 1 dar1 r/w undefined h'ffa00014 h'1fa00014 32 dma transfer count register 1 dmatcr1 r/w undefined h'ffa00018 h'1fa00018 32 dma channel control register 1 chcr1 r/w * 1 h'00000000 h'ffa0001c h'1fa0001c 32 2 dma source address register 2 sar2 r/w undefined h'ffa00020 h'1fa00020 32 dma destination address register 2 dar2 r/w undefined h'ffa00024 h'1fa00024 32 dma transfer count register 2 dmatcr2 r/w undefined h'ffa00028 h'1fa00028 32 dma channel control register 2 chcr2 r/w * 1 h'00000000 h'ffa0002c h'1fa0002c 32 3 dma source address register 3 sar3 r/w undefined h'ffa00030 h'1fa00030 32 dma destination address register 3 dar3 r/w undefined h'ffa00034 h'1fa00034 32 dma transfer count register 3 dmatcr3 r/w undefined h'ffa00038 h'1fa00038 32 dma channel control register 3 chcr3 r/w * 1 h'00000000 h'ffa0003c h'1fa0003c 32 com- mon dma operation register dmaor r/w * 1 h'00000000 h'ffa 00040 h'1fa00040 32 notes: longword access should be used for all cont rol registers. if a different access width is used, reads will return all 0s and writes will not be possible. 1. bit 1 of chcr0?chcr3 and bits 2 and 1 of dmaor can only be written with 0 after being read as 1, to clear the flags. 2. in the SH7750, writes from the cpu are masked in ddt mode, while writes from external i/o devices using the dtr format ar e possible. in the SH7750s, writes from the cpu and writes from external i/o devices using the dtr format are possible in ddt mode.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 552 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.2 register descriptions (SH7750, SH7750s) 14.2.1 dma source address registers 0?3 (sar0?sar3) bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 0 initial value: ? ? r/w: r/w r/w dma source address registers 0?3 (sar0?sar3) are 32-bit readable/writable registers that specify the source address of a dma transfer. these registers have a counter feedback function, and during a dma transfer they indicate the next so urce address. in single address mode, the sar value is ignored when an external device with dack has been specified as the transfer source. specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64- bit, or 32-byte data transfer, resp ectively. if a different address is specified, an address error will be detected and the dmac will halt. the initial value of these registers after a power-on or manual reset is undefined. they retain their values in standby mode and deep sleep mode. when transfer is performed from memory to an external devi ce with dack in ddt mode, dtr format [31:0] is set in sar0 [31:0]. for details, see data transfer request format in section 14.5.2, pin in ddt mode.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 553 of 1076 sep 24, 2013 14.2.2 dma destination address registers 0?3 (dar0?dar3) bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:23 0 initial value: ? ? r/w: r/w r/w dma destination address registers 0?3 (dar0?dar3 ) are 32-bit readable/writable registers that specify the destination address of a dma transf er. these registers have a counter feedback function, and during a dma transf er they indicate the next destin ation address. in single address mode, the dar value is ignored when a device with dack has been specified as the transfer destination. specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64- bit, or 32-byte data transfer, re spectively. if a different address is specified, an address error will be detected and the dmac will halt. the initial value of these registers after a power-on or manual reset is undefined. they retain their values in standby mode and deep sleep mode. when transfer is performed from an external device with dack to memory in ddt mode, dtr format [31:0] is set in dar0 [31:0]. for details , see data transfer reque st format in section 14.5.2, pin in ddt mode. notes: 1. when a 16-bit, 32-bit, 64-bit, or 32-byte boundary address is specified, take care with the setting of bit 0, bits 1?0, bits 2?0, or bits 4?0, respectively. if an address specification that ignores boundary considerat ions is made, the dmac will detect an address error and halt operation on all channe ls (dmaor: address error flag ae = 1). the dmac will also detect an address error an d halt if an area 7 address is specified in a data transfer employing the external bus, or if the addr ess of a nonexistent on-chip peripheral module is specified. 2. external addresses are 29-bit. as sar[31:29] and dar[31:29] are not used in dma transfers, settings of sar[31:29] = 000 and dar[31:29] = 000 are recommended.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 554 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.2.3 dma transfer count registers 0?3 (dmatcr0?dmatcr3) bit: 31 30 29 28 27 26 25 24 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w dma transfer count registers 0? 3 (dmatcr0?dmatcr3) are 32-bit readable/writable registers that specify the transfer count for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). specifying h'000001 gives a transfer count of 1, while h'000000 gives the maximum setting, 16,777,216 (1 6m) transfers. during dmac operation, the remaining number of transfers is shown. bits 31?24 of these registers are reserved; they ar e always read as 0, and should only be written with 0. the initial value of these registers after a power-on or manual reset is undefined. they retain their values in standby mode and deep sleep mode. in ddt mode, settings to dmatcr0[7:0] may be made from dtr format [55:48] as well. for details, see data transfer request format in section 14.5.2, pin in ddt mode.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 555 of 1076 sep 24, 2013 14.2.4 dma channel control registers 0?3 (chcr0?chcr3) bit: 31 30 29 28 27 26 25 24 ssa2 ssa1 ssa0 stc dsa2 dsa1 dsa0 dtc initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 ? ? ? ? ds rl am al initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w (r/w) r/w (r/w) bit: 15 14 13 12 11 10 9 8 dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 tm ts2 ts1 ts0 ? ie te de initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r/w r/(w) r/w note: the te bit can only be written with 0 after being read as 1, to clear the flag. the rl, am, al, and ds bits may be absent, depending on the channel. dma channel control registers 0?3 (chcr0?chcr3) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. bits 31?28 and 27?24 indicate the source address and destination address, respectively; these settings are only valid when the transfer involves the cs5 or cs6 space and the relevant space has been specified as a pcmcia interface space. in other cases, thes e bits should be cleared to 0. for details of the pcmcia interface, see section 13 .3.7, pcmcia interface, in section 13, bus state controller (bsc). in ddt mode, chcr0 is set according to the dtr format. (the following settings are fixed: chcr0 [31:24] = 0, [18:16] = 0, [15:14] = 01, [13:12] = 01, [2] = 0, [1] = 0, [0] = 1) bits 18 and 16 are not present in chcr2 and chcr3. in chcr2 and chcr3, these bits cannot be modified (a write value of 0 should always be used) and are always read as 0.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 556 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 these registers are initialized to h'00000000 by a power-on or manual reset. they retain their values in standby mode and deep sleep mode. bits 31 to 29?source address space attribute specification (ssa2?ssa0): these bits specify the space attribute for access to a pcmcia interface area. bit 31: ssa2 bit 30: ssa1 bit 29: ssa0 description 0 0 0 reserved in pcmcia access (initial value) 1 dynamic bus sizing i/o space 1 0 8-bit i/o space 1 16-bit i/o space 1 0 0 8-bit common memory space 1 16-bit common memory space 1 0 8-bit attribute memory space 1 16-bit attribute memory space bit 28?source address wait control select (stc): specifies cs5 or cs6 space wait cycle control for access to a pcmcia interface area. this bit selects the wait control register in the bsc that performs area 5 and 6 wait cycle control. bit 28: stc description 0 c5 space wait cycle selection (initial value) settings of bits a5w2?a5w0 in wait control register 2 (wcr2), and bits a5pcw1?a5pcw0, a5ted2?a5ted0, and a5teh2?a5teh0 in the pcmcia control register (pcr), are selected 1 c6 space wait cycle selection settings of bits a6w2?a6w0 in wait control register 2 (wcr2), and bits a6pcw1?a6pcw0, a6ted2?a6ted0, and a6teh2?a6teh0 in the pcmcia control register (pcr), are selected note: for details, see section 13.3.7, pcmcia interface.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 557 of 1076 sep 24, 2013 bits 27 to 25?destination address space attribute specification (dsa2?dsa0): these bits specify the space attribute for acce ss to a pcmcia interface area. bit 27: dsa2 bit 26: dsa1 bit 25: dsa0 description 0 0 0 reserved in pcmcia access (initial value) 1 dynamic bus sizing i/o space 1 0 8-bit i/o space 1 16-bit i/o space 1 0 0 8-bit common memory space 1 16-bit common memory space 1 0 8-bit attribute memory space 1 16-bit attribute memory space bit 24?destination address wait control select (dtc): specifies cs5 or cs6 space wait cycle control for access to a pcmcia interface area. this bit selects the wait control register in the bsc that performs area 5 and 6 wait cycle control. bit 24: dtc description 0 c5 space wait cycle selection (initial value) settings of bits a5w2?a5w0 in wait control register 2 (wcr2), and bits a5pcw1?a5pcw0, a5ted2?a5ted0, and a5teh2?a5teh0 in the pcmcia control register (pcr), are selected 1 c6 space wait cycle selection settings of bits a6w2?a6w0 in wait control register 2 (wcr2), and bits a6pcw1?a6pcw0, a6ted2?a6ted0, and a6teh2?a6teh0 in the pcmcia control register (pcr), are selected note: for details, see section 13.3.7, pcmcia interface. bits 23 to 20?reserved: these bits are always read as 0, and should only be written with 0.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 558 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 19? dreq select (ds): specifies either low level detection or falling edge detection as the sampling method for the dreq pin used in external request mode. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, it is valid in chcr0?chcr3. bit 19: ds description 0 low level detection (initial value) 1 falling edge detection notes: level detection burst mode when tm = 1 and ds = 0 edge detection burst mode when tm = 1 and ds = 1 bit 18?request check level (rl): selects whether the drak signa l (that notifies an external device of the acceptance of dreq ) is an active-high or active-low output. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, this bit is invalid. bit 18: rl description 0 drak is an active-high output (initial value) 1 drak is an active-low output bit 17?acknowledge mode (am): in dual address mode, selects whether dack is output in the data read cycle or write cycle. in single address mode, dack is always output regardless of the setting of this bit. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, this bit is valid for chcr1 to chcr3 in the SH7750. in the SH7750s, this bit is valid for chcr0 to chcr3. (ddt mode: tdack ) bit 17: am description 0 dack is output in read cycle (initial value) 1 dack is output in write cycle
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 559 of 1076 sep 24, 2013 bit 16?acknowledge level (al): specifies the dack (acknowledge) signal as active-high or active-low. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, this bit is invalid. bit 16: al description 0 active-high output (initial value) 1 active-low output bits 15 and 14?destination address mode 1 and 0 (dm1, dm0): these bits specify incrementing/decrementing of the dma transfer destination addres s. the specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. for channel 0, in ddt mode these bits are set to dm1 = 0 and dm0 = 1 with the dtr format. bit 15: dm1 bit 14: dm0 description 0 0 destination address fixed (initial value) 1 destination address incremented (+1 in 8-bit transfer, +2 in 16- bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-byte burst transfer) 1 0 destination address decremented (?1 in 8-bit transfer, ?2 in 16-bit transfer, ?4 in 32-bit transfer, ?8 in 64-bit transfer, ?32 in 32-byte burst transfer) 1 setting prohibited
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 560 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 13 and 12?source addre ss mode 1 and 0 (sm1, sm0): these bits specify incrementing/decrementing of the dm a transfer source address. the specification of these bits is ignored when data is transferre d from an external device to ex ternal memory in single address mode. for channel 0, in ddt mode these bits are set to sm1 = 0 and sm0 = 1 with the dtr format. bit 13: sm1 bit 12: sm0 description 0 0 source address fixed (initial value) 1 source address incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32- byte burst transfer) 1 0 source address decremented (?1 in 8-bit transfer, ?2 in 16-bit transfer, ?4 in 32-bit transfer, ?8 in 64-bit transfer, ?32 in 32- byte burst transfer) 1 setting prohibited
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 561 of 1076 sep 24, 2013 bits 11 to 8?resource select 3 to 0 (rs3?rs0): these bits specify the tr ansfer request source. bit 11: rs3 bit 10: rs2 bit 9: rs1 bit 8: rs0 description 0 0 0 0 external request, dual address mode * 1 * 4 (external address space external address space) (initial value) 1 setting prohibited 1 0 external request, single address mode external address space external device * 1 * 3 * 4 1 external request, single address mode external device external address space * 1 * 3 * 4 1 0 0 auto-request (external address space external address space) * 2 1 auto-request (external address space on-chip peripheral module) * 2 1 0 auto-request (on-chip peripheral module external address space) * 2 1 setting prohibited 1 0 0 0 sci transmit-data-empty interrupt transfer request (external address space sctdr1) * 2 1 sci receive-data-full interrupt transfer request (scrdr1 external address space) * 2 1 0 scif transmit-data-empty interrupt transfer request (external address space scftdr2) * 2 1 scif receive-data-full interrupt transfer request (scfrdr2 external address space) * 2 1 0 0 tmu channel 2 (input capture interrupt, external address space external address space) * 2 1 tmu channel 2 (input capture interrupt, external address space on-chip peripheral module) * 2 1 0 tmu channel 2 (input capture interrupt, on-chip peripheral module external address space) * 2 1 setting prohibited notes: 1. external request specifications are valid only for channels 0 and 1. requests are not accepted for channels 2 and 3 in normal dma mode. 2. dual address mode 3. in ddt mode, selection is possible with the dtr format [60] (r/w bit) and [57-56] (md1, md0 bits) specification for channel 0 only. 4. in ddt mode:
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 562 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 [SH7750] an external request specification should be set for channels 1 to 3. for channel 0, only single address mode can be set with the dtr format. [SH7750s] an external request specification can be set for channels 0 to 3. bit 7?transmit mode (tm): specifies the bus mode for transfer. bit 7: tm description 0 cycle steal mode (initial value) 1 burst mode bits 6 to 4?transmit size 2 to 0 (ts2?ts0): these bits specify the transfer data size. for external memory access, the setting of these b its serves as the access size in section 13.3, operation. for register access, the setting of these bits is the size in which the register is accessed. bit 6: ts2 bit 5: ts1 bit 4: ts0 description 0 0 0 quadword size (64-bit) s pecification (initial value) 1 byte size (8-bit) specification 1 0 word size (16-bit) specification 1 longword size (32-bit) specification 1 0 0 32-byte block transfer specification bit 3?reserved: this bit is always read as 0, and should only be written with 0. bit 2?interrupt enable (ie): when this bit is set to 1, an interrupt request (dmte) is generated after the number of data transfer s specified in dmatcr (when te = 1). bit 2: ie description 0 interrupt request not generated afte r number of transfers specified in dmatcr (initial value) 1 interrupt request generated after number of transfers specified in dmatcr
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 563 of 1076 sep 24, 2013 bit 1?transfer end (te): this bit is set to 1 after the number of transfers specified in dmatcr. if the ie bit is set to 1 at this tim e, an interrupt request (dmte) is generated. if data transfer ends before te is set to 1 (for ex ample, due to an nmi inte rrupt, address error, or clearing of the de bit or the dme bit in dmaor), th e te bit is not set to 1. when this bit is 1, the transfer enabled state is not entere d even if the de bit is set to 1. bit 1: te description 0 number of transfers specified in dmatcr not completed (initial value) [clearing conditions] ? when 0 is written to te after reading te = 1 ? in a power-on or manual reset, and in standby mode 1 number of transfers specified in dmatcr completed bit 0?dmac enable (de): enables operation of the corresponding channel. bit 0: de description 0 operation of corresponding channel is disabled (initial value) 1 operation of corresponding channel is enabled when auto-request is specified (with rs3?rs0), transf er is begun when this bit is set to 1. in the case of an external request or on-chip peripheral module request, transfer is begun when a transfer request is issued after this bit is set to 1. transfer can be suspended midway by clearing this bit to 0. even if the de bit has been set, transfer is no t enabled when te is 1, when dme in dmaor is 0, or when the nmif or ae bit in dmaor is 1. for channel 0, in ddt mode this bit is set to 1 when a dtr format is received. de remains set to 1 even if te is set to 1. when the mode is switched from ddt mode to normal dma mode (ddt bit = 0 in dmaor), the de bit must be cleared to 0.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 564 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.2.5 dma operation register (dmaor) bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ddt ? ? ? ? ? pr1 pr0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? cod ? ae nmif dme initial value: 0 0 0 0 0 0 0 0 r/w: r r r r/(w) r r/(w) r/(w) r/w notes: the ae and nmif bits can only be written wit h 0 after being read as 1, to clear the flags. the cod bit can be written to in the SH7750s only. dmaor is a 32-bit readable/writable register that specifies the dmac transfer mode. dmaor is initialized to h'00000000 by a power-on or manual reset. they retain their values in standby mode and deep sleep mode. bits 31 to 16?reserved: these bits are always read as 0, and should only be written with 0.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 565 of 1076 sep 24, 2013 bit 15?on-demand data transfer (ddt): specifies on-demand da ta transfer mode. bit 15: ddt description 0 normal dma mode (initial value) 1 on-demand data transfer mode note: bavl (drak0) is an active-high output in normal dma mode. when the ddt bit is set to 1, the bavl pin function is enabled and this pin becomes an active-low output. bits 14 to 10?reserved: these bits are always read as 0, and should only be written with 0. bits 9 and 8?priority mode 1 and 0 (pr1, pr0): these bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. bit 9: pr1 bit 8: pr0 description 0 0 ch0 > ch1 > ch2 > ch3 (initial value) 1 ch0 > ch2 > ch3 > ch1 1 0 ch2 > ch0 > ch1 > ch3 1 round robin mode bits 7 to 5?reserved: these bits are always read as 0, and should only be written with 0. bit 4 (SH7750s)?check overrun for dreq (cod): when this bit is set to 1, cancellation of an accepted dreq acceptance flag is enabled. when cancellation of an accepted dreq acceptance flag is enabled by setting cod to 1, clear chcrn.ds to 0 and then negate dreq (to the high level). for details, see external request mode in section 14.3.2, dma transfer requests. bit 4: cod description 0 dreq acceptance flag cancellation disabled (initial value) 1 dreq acceptance flag cancellation enabled note: when external request mode is used in the SH7750s, recommend setting cod to 1 permanently. bit 4 (SH7750)?reserved: these bits are always read as 0, and should only be written with 0. bit 3?reserved: this bit is always read as 0, and should only be written with 0. bit 2?address e rror flag (ae): indicates that an address er ror has occurred during dma transfer. if this bit is set duri ng data transfer, transfers on al l channels are suspended, and an
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 566 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 interrupt request (dmae) is generated. the cpu cannot write 1 to ae. this bit can only be cleared by writing 0 after reading 1. bit 2: ae description 0 no address error, dma transfer enabled (initial value) [clearing condition] when 0 is written to ae after reading ae = 1 1 address error, dma transfer disabled [setting condition] when an address error is caused by the dmac bit 1?nmi flag (nmif): indicates that nmi has been input. this bit is set regardless of whether or not the dmac is operating. if this b it is set during data tr ansfer, transfers on all channels are suspended. the cpu cannot write 1 to nmif. this bit can only be cleared by writing 0 after reading 1. bit 1: nmif description 0 no nmi input, dma transfer enabled (initial value) [clearing condition] when 0 is written to nmif after reading nmif = 1 1 nmi input, dma transfer disabled [setting condition] when an nmi interrupt is generated bit 0?dmac master enable (dme): enables activation of the entire dmac. when the dme bit and the de bit of the chcr register for the co rresponding channe l are set to 1, that channel is enabled for transfer. if this bi t is cleared during data transfer , transfers on all channels are suspended. even if the dme bit has been set, transfer is no t enabled when te is 1 or de is 0 in chcr, or when the nmi or ae bit in dmaor is 1. bit 0: dme description 0 operation disabled on all channels (initial value) 1 operation enabled on all channels
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 567 of 1076 sep 24, 2013 14.3 operation when a dma transfer request is issued, the dmac starts the transfer according to the predetermined channel priority order. it ends th e transfer when the tran sfer end conditions are satisfied. transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. there are two modes fo r dma transfer: single address mode and dual address mode. either burst mode or cycle st eal mode can be selected as the bus mode. 14.3.1 dma transfer procedure after the desired transfer conditions have been set in the dma source address register (sar), dma destination address register (dar), dm a transfer count register (dmatcr), dma channel control register (chcr), and dma operation register (dmaor), the dmac transfers data according to the following procedure: 1. the dmac checks to see if transfer is enable d (de = 1, dme = 1, te = 0, nmif = 0, ae = 0). 2. when a transfer request is issued and tran sfer has been enabled, the dmac transfers one transfer unit of data (determined by the setting of ts2?ts0). in auto-request mode, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value is decremented by 1 for each transf er. the actual transfer flow de pends on the address mode and bus mode. 3. when the specified number of transfers have been completed (when the dmatcr value reaches 0), the tr ansfer ends normally. if the ie bit in chcr is set to 1 at this time, a dmte interrupt request is sent to the cpu. 4. if a dmac address error or nmi interrupt occurs , the transfer is suspe nded. transfer is also suspended when the de bit in chcr or the dme bit in dmaor is cleared to 0. in the event of an address error, a dmae interrupt request is forcibly sent to the cpu. figure 14.2 shows a flowchart of this procedure. note: if transfer request is issued while transfer is disabled, the transfer enable wait state (transfer suspended state) is entered. transfer is started when subsequently enabled (by setting de = 1, dme = 1, te = 0, nmif = 0, ae = 0)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 568 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 start initial settin g s (sar, dar, dmatcr, chcr, dmaor) ille g al address check (reflected in ae bit) de, dme = 1? nmif, ae, te = 0? transfer request issued? * 1 transfer (1 transfer unit) dmatcr - 1 dmatcr update sar, dar dmte interrupt request (when ie = 1) dmatcr = 0? nmif or ae = 1 or de = 0 or dme = 0? end of transfer normal end nmif or ae = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection method transfer suspended * 4 * 2 * 3 no no yes yes yes no no no yes yes no yes notes: 1. in auto-request mode, transfer be g ins when the nmif, ae, and te bits are all 0, and the de and dme bits are set to 1. 2. dreq level detection (external request) in burst mode, or cycle steal mode. 3. dreq ed g e detection (external request) in burst mode, or auto-request mode in burst mode. 4. an ille g al address is detected by comparin g bits ts2?ts0 in chcrn with sarn and darn. figure 14.2 dmac transfer flowchart
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 569 of 1076 sep 24, 2013 14.3.2 dma transfer requests dma transfer requests are basically generated at ei ther the data tr ansfer source or destination, but they can also be issued by external devices or on-chip peripheral modu les that are neither the source nor the destination. transfers can be requested in three modes: auto-re quest, external request, and on-chip peripheral module request. the transfer request mode is selected by means of bits rs3?rs0 in dma channel control registers 0?3 (chcr0?chcr3). auto request mode: when there is no transfer request sign al from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bit in chcr0?chcr3 and the dme bit in the dma operation register (dmaor) are set to 1, the transfer begins (so long as the te bit in chcr0?chcr3 and the nmif and ae bits in dmaor are all 0). external request mode: in this mode a transfer is performed in response to a transfer request signal ( dreq ) from an external device. one of the modes shown in table 14.4 should be chosen according to the application system . if dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), transfer starts when dreq is input. the ds bit in chcr0/chcr1 is used to select either falling edge detection or low level detection for the dreq signal (level detection when ds = 0, edge detection when ds = 1). dreq is accepted after a power-on reset if te = 0, nmif = 0, and ae = 0, but transfer is not executed if dma transfer is not enabled (de = 0 or dme = 0). in this case, dma transfer is started when enabled (by setting de = 1 and dme = 1).
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 570 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 14.4 selecting external request mode with rs bits rs3 rs2 rs1 rs0 address mode transfer source transfer destination 0 0 0 0 dual address mode external memory or memory-mapped external device, or external device with dack external memory or memory-mapped external device, or external device with dack 1 0 single address mode external memory or memory-mapped external device external device with dack 1 single address mode external device with dack external memory or memory-mapped external device ? external request acceptance conditions 1. when at least one of dmaor.dme and chcr.de is 0, and dmaor.nmif, dmaor.ae, and chcr.te are all 0, if an external request ( dreq : edge-detected) is input it will be held inside the dmac until dma transfer is either executed or canceled. since dma transfer is not enabled in this cas e (dme = 0 or de = 0), dma transfer is not initiated. dma transfer is started after it is enabled (dme = 1, de = 1, dmaor.nmif = 0, dmaor.ae = 0, chcr.te = 0). 2. when dma transfer is enabled (dme = 1, de = 1, dmaor.nmif = 0, dmaor.ae = 0, chcr.te = 0), if an external request ( dreq ) is input, dma tran sfer is started. 3. an external request ( dreq ) will be ignored if input when chcr.te = 1, dmaor.nmif = 1, or dmaor.ae = 1, or during a power-on reset or manual reset, in deep sleep mode or standby mode, or while the dmac is in the module standby state. 4. a previously input external request will be canceled by the occurrence of an nmi interrupt (dmaor.nmif = 1) or address error (dmaor.ae = 1), or by a power-on reset or manual reset. in the SH7750s, it is possible to cancel a previously input external request ( dreq ). with dmaor.cod set to 1, clear chcrn .ds to 0 and then drive the dreq pin high. on the SH7750r, it is possi ble to cancel an external reque st that has been accepted by external request ( dreq ) edge detection by first negating dreq and then clearing chcr.ds from 1 to 0. afterwards ch cr.ds should be reset to 1 and dreq asserted. (the SH7750r has no dmaor.cod bit, but it is possible to cancel an external request that has been accepted by external request ( dreq ) edge detection, as is the case when the dmaor.cod bit of the SH7750s is set to 1.)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 571 of 1076 sep 24, 2013 ? usage notes an external request ( dreq ) is detected by a low level or fall ing edge. ensure that the external request ( dreq ) signal is held high when there is no dma transfer request from an external device after a power-on reset or manual reset. when dma transfer is restarted, check whet her a dma transfer request is being held. on-chip peripheral module request mode: in this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. as shown in table 14.5, there are seven transfer request signa ls: input capture interrupts from the timer unit (tmu), and receive-data-full interrupts (rxi) and transmit-data-empty interrupts (txi) from the two serial communication interfaces (sci, scif). if dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), transfer starts when a transfer request signal is input. the source of the transfer reques t does not have to be the data transfer source or destination. however, when the transfer request is set to rx i (transfer request by sc i/scif receive-data-full interrupt), the transfer source must be the sci/ scif's receive data regi ster (scrdr1/scfrdr2). when the transfer request is set to txi (tra nsfer request by sci/scif transmit-data-empty interrupt), the transfer destination must be the sci/scif's transmit data register (sctdr1/scftdr2).
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 572 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 14.5 selecting on-chip peripheral module request mode with rs bits rs3 rs2 rs1 rs0 dmac transfer request source dmac transfer request signal transfer source transfer destination bus mode 1 0 0 0 sci transmitter sctdr1 (sci transmit-data- empty transfer request) external * sctdr1 cycle steal mode 1 sci receiver scrdr1 (sci receive-data-full transfer request) scrdr1 external * cycle steal mode 1 0 scif transmitter scftdr2 (scif transmit-data- empty transfer request) external * scftdr2 cycle steal mode 1 scif receiver scfrdr2 (scif receive-data-full transfer request) scfrdr2 external * cycle steal mode 1 0 0 tmu channel 2 input capture occurrence external * external * burst/cycle steal mode 1 tmu channel 2 input capture occurrence external * on-chip peripheral burst/cycle steal mode 1 0 tmu channel 2 input capture occurrence on-chip peripheral external * burst/cycle steal mode legend: tmu: timer unit sci: serial communication interface scif: serial communication interface with fifo notes: 1. sci/scif burst transfer setting is prohibited. 2. if input capture interrupt acceptance is set for multiple channels and de = 1 for each channel, processing will be executed on the highest-priority channel in response to a single input capture interrupt. 3. a dma transfer request by means of an in put capture interrupt can be canceled by setting tcr2.icpe1 = 0 and icpe0 = 0 in the tmu. * external memory or memory-mapped external device to output a transfer request from an on-chip peripheral module, set the dma transfer request enable bit for that module and output a transfer request signal. for details, see sections 12, timer unit (tmu), 15, serial communica tion interface (sci), and 16, serial communication in terface with fifo (scif).
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 573 of 1076 sep 24, 2013 when a dma transfer corresponding to a transfer request signal from an on-chip peripheral module shown in table 14.5 is carried out, the si gnal is discontinued automatically. this occurs every transfer in cycle steal mode, and in the last transfer in burst mode. 14.3.3 channel priorities if the dmac receives simultaneous tr ansfer requests on two or more channels, it selects a channel according to a predetermined priori ty system, either in a fixed mode or round robin mode. the mode is selected with priority bits pr1 and pr0 in the dma operation register (dmaor). fixed mode: in this mode, the relative channel prioriti es remain fixed. the following priority orders are available in fixed mode: ? ch0 > ch1 > ch2 > ch3 ? ch0 > ch2 > ch3 > ch1 ? ch2 > ch0 > ch1 > ch3 the priority order is selected with bits pr1 and pr0 in dmaor. round robin mode: in round robin mode, each time the transfer of one transfer unit (byte, word, longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest priority level. this is illustrated in figure 14.3. the order of priority in round robin mode immediately after a reset is ch0 > ch1 > ch2 > ch3. note: in round robin mode, if no transfer request is accepted for any channel during dma transfer, the priority order becomes ch0 > ch1 > ch2 > ch3.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 574 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ch0 > ch1 > ch2 > ch3 ch1 > ch2 > ch3 > ch0 ch0 > ch1 > ch2 > ch3 transfer on c hannel 0 priority order after transfer initial priority order channel 0 is g iven the lowest priority. transfer on c hannel 1 priority order after transfer initial priority order transfer on c hannel 2 priority order after transfer initial priority order priority after transfer due to issuance of a transfer request for channel 1 only. when channel 2 is g iven the lowest priority, the priorities of channels 0 and 1, which were hi g her than channel 2, are also shifted simultaneously. if there is a transfer request for channel 1 only immediately afterward, channel 1 is g iven the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down. transfer on c hannel 3 initial priority order priority order after transfer no chan g e in priority order ch0 > ch1 > ch2 > ch3 ch3 > ch0 > ch1 > ch2 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 when channel 1 is g iven the lowest priority, the priority of channel 0, which was hi g her than channel 1, is also shifted simultaneously. figure 14.3 round robin mode figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transf er request during a tran sfer on channel 0. the operation of the dmac in this case is as follows.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 575 of 1076 sep 24, 2013 1. transfer requests are issued simultaneously for channels 0 and 3. 2. since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. a transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby). 4. at the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. at this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is started (channel 3 is on transfer standby). 6. at the end of the channel 1 transfer, channel 1 shifts to the lowest priority level. 7. the channel 3 transfer is started. 8. at the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority. 3 1, 3 3 transfer request channel waiting dmac operation channel priority order 1. issued for channels 0 and 3 3. issued for channel 1 2. start of channel 0 transfer 0 > 1 > 2 > 3 1 > 2 > 3 > 0 2 > 3 > 0 > 1 0 > 1 > 2 > 3 4. end of channel 0 transfer 5. start of channel 1 transfer 6. end of channel 1 transfer 7. start of channel 3 transfer 8. end of channel 3 transfer chan g e of priority order chan g e of priority order chan g e of priority order none figure 14.4 example of changes in priority order in round robin mode
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 576 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.3.4 types of dma transfer the dmac supports the transfers shown in table 14.6. it can operate in single address mode, in which either the transf er source or the transf er destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output. the actual tr ansfer operation timing depends on the bus mode, which can be either burst mode or cycle steal mode. table 14.6 supported dma transfers transfer destination transfer source external device with dack external memory memory-mapped external device on-chip peripheral module external device with dack not available single address mode single address mode not available external memory single address mode dual address mode dual address mode dual address mode memory-mapped external device single address mode dual address mode dual address mode dual address mode on-chip peripheral module not available dual address mode dual address mode not available
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 577 of 1076 sep 24, 2013 address modes single address mode: in single address mode, both the transfer source and the transfer destination are external; one is acce ssed by the dack signal and the other by an address. in this mode, the dmac performs a dma transfer in one bus cycle by simultaneously outputting the external device strobe si gnal (dack) to either the transfer so urce or transfer de stination external device to access it, while outputting an address to th e other side of the transfer. figure 14.5 shows an example of a transfer between external memory and an exte rnal device with dack in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle. dmac dack dreq external memory external device with dack SH7750, SH7750s, SH7750r external address bus : data flow external data bus le g end: figure 14.5 data flow in single address mode two types of transfer are possible in single addr ess mode: (1) transfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and external memory. only the external request signal ( dreq ) is used in both these cases. figure 14.6 shows the dma transfer timing for single address mode. the access timing depends on the type of external me mory. for details, see the descriptions of the memory interfaces in section 13 , bus state controller (bsc).
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 578 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 address output to external memory space data output from external device with dack dack si g nal to external device with dack we si g nal to external memory space address output to external memory space data output from external memory space rd si g nal to external memory space dack si g nal to external device with dack (a) from external device with dack to external memory space (b) from external memory space to external device with dack ckio a28?a0 csn d63?d0 dack we ckio a28?a0 csn d63?d0 rd dack figure 14.6 dma transfer timing in single address mode dual address mode: dual address mode is used to acces s both the transf er source and the transfer destination by address. the transfer source and destin ation can be accessed by either on- chip peripheral module or external address. even if the operand cache is used in ram mode, the ram cannot be set as the transfer source or transfer destination.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 579 of 1076 sep 24, 2013 in dual address mode, data corresponding to th e size specified by chcrn. ts is read from the transfer source in the data read cycle, and, in the data write cy cle, it is transferred in two bus cycles in order to write in the transfer destination the data corre sponding to the size specified by chcrn.ts. in this process, the transfer data is temporarily stored in the data buffer in the bus state controller (bsc). in a transfer between external memories such as that shown in figure 14.7, data is read from external memory into the bsc's data buffer in the read cycle, then written to the other external memory in the write cycle. figure 14.8 shows the timing for this operation. the dack output timing is the same as that of csn in a read or write cycle sp ecified by the chcrn.am bit. data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar takin g the sar value as the address, data is read from the transfer source module and stored temporarily in the data buffer in the bus state controller (bsc). 1st bus c y c le 2nd bus c y c le takin g the dar value as the address, the data stored in the bsc's data buffer is written to the transfer destination module. dmac bsc bsc dmac figure 14.7 operation in dual address mode
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 580 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio a26?a0 csn d63?d0 rd we dack transfer from external memory space to external memory space transfer source address transfer destination address data read cycle (1st cycle) data write cycle (2nd cycle) figure 14.8 example of transfer timing in dual address mode bus modes there are two bus modes, cycle steal mode and bur st mode, selected with the tm bit in chcr0? chcr3. cycle steal mode: in cycle steal mode, the dmac releases the bus to the cpu at the end of each transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. wh en the next transfer request is issued, the dmac reacquires the bus from the cpu and carries out another transfer-unit transfer. at the end of this transfer, the bus is again given to the cpu. this is repeat ed until the transfer end condition is satisfied. cycle steal mode can be used with all categories of transfer request sour ce, transfer source, and transfer destination.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 581 of 1076 sep 24, 2013 figure 14.9 shows an example of dma transf er timing in cycle steal mode. the transfer conditions in this example are dual address mode and dreq level detection. cpu cpu dmac dmac cpu dmac dmac cpu cpu cpu dreq bus cycle bus returned to cpu read write read write figure 14.9 example of dma transfer in cycle steal mode burst mode: in burst mode, once the dmac has acquired the bus it holds th e bus and transfers data continuously until the transfer end condition is satisfied. with dreq low level detection in external request mode, however, when dreq is driven high the bus passes to another bus master after the end of the dmac transfer request that ha s already been accepted, even if the transfer end condition has not been satisfied. figure 14.10 shows an example of dma transfer timing in burst mode. the transfer conditions in this example are single address mode and dreq level detection (chcrn.ds = 0, chcrn.tm = 1). cpu dmac dmac dmac dmac dmac dmac cpu cpu cpu dreq bus cycle figure 14.10 example of dm a transfer in burst mode note: burst mode can be set regardless of the transfer size. a 32-byte block transfer burst mode setting can also be made.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 582 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 relationship between dma transfer type, request mode, and bus mode table 14.7 shows the relationship between the ty pe of dma transfer, th e request mode, and the bus mode. table 14.7 relationship between dma tr ansfer type, request mode, and bus mode address mode type of transfer request mode bus mode transfer size (bits) usable channels single external device with dack and external memory external b/c 8/16/32/64/32b 0, 1 (2, 3) * 6 external device with dack and memory-mapped external device external b/c 8/16/32/64/32b 0, 1 (2, 3) * 6 dual external memory and external memory internal * 1 external * 7 b/c 8/16/32/64/32b 0 to 3 * 5 * 6 external memory and memory-mapped external device internal * 1 external * 7 b/c 8/16/32/64/32b 0 to 3 * 5 * 6 memory-mapped external device and memory-mapped external device internal * 1 external * 7 b/c 8/16/32/64/32b 0 to 3 * 5 * 6 external memory and on-chip peripheral module internal * 2 b/c * 3 8/16/32/64 * 4 0 to 3 * 5 * 6 memory-mapped external device and on-chip peripheral module internal * 2 b/c * 3 8/16/32/64 * 4 0 to 3 * 5 * 6 legend: 32b: 32-byte burst transfer b: burst c: cycle steal external: external request internal: auto-request or on-chip peripheral module request notes: 1. external request, auto-request, or on- chip peripheral module request (tmu input capture interrupt request) possible. in the case of an on-chip peripheral module request, it is not possible to specify external memo ry data transfer with the sci (scif) as the transfer request source. 2. auto-request, or on-chip peripheral module request possible. if the transfer request source is the sci (scif), either the tr ansfer source must be scrdr1 (scfrdr2) or the transfer destination mu st be sctdr1 (scftdr2). 3. when the transfer request source is the sci (scif), only cycle steal mode can be used.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 583 of 1076 sep 24, 2013 4. access size permitted for the on-chip perip heral module register that is the transfer source or transfer destination. 5. when the transfer request is an external request, only channels 0 and 1 can be used. 6. in ddt mode, transfer requests can be accepted for all channels from external devices capable of dtr format output. 7. see tables 14.8 and 14.9 for the transfer sources and transfer destinations in dma transfer by means of an external request. (a) normal dma mode table 14.8 shows the memory interfaces that can be specified for the transf er source and transfer destination in dma transfer initiated by an extern al request supported by this lsi in normal dma mode. table 14.8 external request transfer sources and destinat ions in normal dma mode transfer direction (settable memory interface) transfer source transfer destination address mode usable dmac channels 1 synchronous dram external device with dack single 0, 1 2 external device with dack synchronous dram single 0, 1 3 sram-type, dram external device with dack single 0, 1 4 external device with dack sram-type, dram single 0, 1 5 synchronous dram sram-type, mpx, pcmcia * dual 0, 1 6 sram-type, mpx, pcmcia * synchronous dram dual 0, 1 7 sram-type, dram, pcmcia, mpx sram-type, mpx, pcmcia * dual 0, 1 8 sram-type, mpx, pcmcia * sram-type, dram, pcmcia, mpx dual 0, 1 "sram-type" in the table indicates an sram, byte control sram, or burst rom setting. notes: memory interfaces on which transfer is pos sible in single address mode are sram, byte control sram, burst rom, dram, and synchronous dram. when performing dual address mode transfer, make the dack output setting for the sram, byte control sram, burst rom, pcmcia, or mpx interface. * dack output setting in dual address mode transfer (b) ddt mode table 14.9 shows the memory interfaces that can be specified for the transf er source and transfer destination in dma transfer initiated by an exte rnal request supported by this lsi in ddt mode.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 584 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 14.9 external request transfer so urces and destinations in ddt mode transfer direction (settable memory interface) transfer source transfer destination address mode usable dmac channels 1 synchronous dram * 1 external device with dack single 0 to 3 2 external device with dack synchronous dram single 0 to 3 3 synchronous dram sram-type, mpx, pcmcia * 2 dual 0 to 3 4 sram-type, mpx, pcmcia * 2 synchronous dram dual 0 to 3 5 sram-type, dram, pcmcia, mpx sram-type, mpx, pcmcia * 2 dual 0 to 3 6 sram-type, mpx, pcmcia * 2 sram-type, dram, pcmcia, mpx dual 0 to 3 "sram-type" in the table indicates an sram, byte control sram, or burst rom setting. notes: the only memory interface on which sing le address mode transfer is possible in ddt mode is synchronous dram. when performing dual address mode transfer, make the dack output setting for the sram, byte control sram, burst rom, pcmcia, or mpx interface. 1. in SH7750, the bus width must be 64 bits 2. dack output setting in dual address mode transfer bus mode and channel priority order when, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to channel 0, which has a higher priority, the channel 0 transfer is started immediately. if fixed mode has been set for the priority levels (ch0 > ch1), transfer on channel 1 is continued after transfer on channel 0 is co mpletely finished, whether cycle st eal mode or burst mode is set for channel 0. if round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for channel 0. channel execution alte rnates in the order: channel 1 channel 0 channel 1 channel 0. an example of round robin mode operation is shown in figure 14.11. since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the cpu until channel 1 transfer ends.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 585 of 1076 sep 24, 2013 cpu dmac ch1 dmac ch1 dmac ch0 dmac ch1 dmac ch0 dmac ch1 dmac ch1 cpu le g end: priority system: round robin mode channel 0: cycle steal mode channel 1: burst mode (ed g e-sensin g ) ch0 ch1 ch0 cpu cpu dmac channel 1 burst mode dmac channel 0 and channel 1 round robin mode dmac channel 1 burst mode figure 14.11 bus handling with two dmac channels operating note: when channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the bus is passed to the cpu during a break in requests. 14.3.5 number of bus cycle states and dreq pin sampling timing number of states in bus cycle: the number of states in the bus cycle when the dmac is the bus master is controlled by the bus state controlle r (bsc) just as it is when the cpu is the bus master. see section 13, bus state controller (bsc), for details. dreq pin sampling timing: in external request mode, the dreq pin is sampled at the rising edge of ckio clock pulses. when dreq input is detected, a dmac bus cycle is generated and dma transfer executed after four ckio cycles at the earliest. when falling edge detection is selected for dreq , the dmac will recognize dreq two cycles (ckio) later because the signal must pass throug h the asynchronous input synchronization circuit. (there is a 1-cycle (ckio) delay when low-level detection is selected.) the second and subsequent dreq sampling operations are performe d one cycle after the start of the first dmac transfer bus cycle (i n the case of single address mode). drak is output for one cycle only, once each time dreq is detected, regardless of the transfer mode or dreq detection method. in the case of burst mode edge detection, dreq is sampled in the first cycle only, and so drak is output in the first cycle only .
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 586 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 operation: figures 14.12 to 14.22 show the timing in each mode. 1. cycle steal mode in cycle steal mode, the dreq sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of dreq . for example, in figure 14.12 (cycle steal mo de, dual address mode, level detection), dmac transfer begins, at the earliest, four ckio cycles after the first sampling operatio n. the second sampling operation is performed one cycle after the start of the first dmac transfer write cycle. if dreq is not detected at this time, sampling is executed in every subsequent cycle. in figure 14.13 (cycle steal mode, dual address mode, edge detection), dmac transfer begins, at the earliest, five ckio cycles after the first sampling operation. the second sampling operation begins from the cycle in which the first dmac transfer read cycle ends. if dreq is not detected at this time, sampling is executed in every subsequent cycle. for details of the timing for various kinds of memory access, see section 13, bus state controller (bsc). figure 14.18 shows the cas e of cycle steal mode, single addr ess mode, and level detection. in this case, too, transfer is started, at th e earliest, four ckio cycles after the first dreq sampling operation. the second sampling operation is performed one cycle after the start of the first dmac tran sfer bus cycle. figure 14.19 shows the cas e of cycle steal mode, single addr ess mode, and edge detection. in this case, transfer is star ted, at the earliest, five ckio cycles after the first dreq sampling operation. the second sampling begins one cycle after the first assertion of drak. in single address mode, the dack signal is output every dmac transfer cycle. 2. burst mode, dual address mode, level detection dreq sampling timing in burst mode using dual address mode and level detection is virtually the same as for cycle steal mode. for example, in figure 14.14, dmac transfer be gins, at the earliest, four ckio cycles after the first sampling operation. the second sampling op eration is performed one cycle after the start of the first dmac transfer write cycle. in the case of dual address mode transfer initiated by an external request, the dack signal can be output in either the read cycle or the writ e cycle of the dmac transfer according to the specification of the am bit in chcr. 3. burst mode, single address mode, level detection dreq sampling timing in burst mode using single address mode and level detection is shown in figure 14.20.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 587 of 1076 sep 24, 2013 in the example shown in figure 14.20, dmac tran sfer begins, at the ear liest, four ckio cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first dmac transfer bus cycle. in single address mode, the dack signal is output every dmac transfer cycle. in figure 14.22, with a 32-byte data size, 64-bit bus width, and sdram: row hit write, dmac transfer begins, at the earliest, six ckio cycles after the first sampling operation. the second sampling operation begins one cycle after dack is asserted for the first dmac transfer. 4. burst mode, dual address mode, edge detection in burst mode using dual address mode and edge detection, dreq sampling is performed in the first cycle only. for example, in the case shown in figure 14.15, dmac transfer begins, at the earliest, five ckio cycles after the first sampling operation. dm ac transfer then continues until the end of the number of data transfers set in dmatcr. dreq is not sampled during this time, and therefore drak is output in the first cycle only. in the case of dual address mode transfer initiated by an external request, the dack signal can be output in either the read cycle or the write cycle of the dmac transfer according to the specification of the am bit in chcr. 5. burst mode, single address mode, edge detection in burst mode using single address mode and edge detection, dreq sampling is performed only in the first cycle. for example, in the case shown in figure 14.21, dmac transfer begins, at the earliest, five cycles after the first sampling operation. dmac transfer then continues until the end of the number of data transfers set in dmatcr. dreq is not sampled during this time, and therefore drak is output in the first cycle only. in single address mode, the dack signal is output every dmac transfer cycle. suspension of dma transfer in case of dreq level detection with dreq level detection in burst mode or cycle steal mode, and in dual address mode or single address mode, the external device for which dma transfer is bein g executed can judge from the rising edge of ckio that dark has been asserted, and suspend dma transfer by negating dreq . in this case, the next dark signal is not output.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 588 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 source address read write read 1st acceptance 2nd acceptance write bus locked source address destination address bus locked destination address cpu cpu dmac cpu dmac drak0 dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[63:0] : dreq samplin g and determination of channel priority le g end: figure 14.12 dual addres s mode/cycle steal mode external bus external bus/ dreq (level detection), dack (read cycle)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 589 of 1076 sep 24, 2013 source address read write read read 3rd acceptance 4th accep- tance 1st acceptance 2nd acceptance write bus locked source address source address destination address bus locked destination address cpu dmac cpu dmac cpu dmac drak0 dreq1 dreq0 (ed g e detection) dack0 bus cycle a[25:0] ckio d[63:0] : dreq samplin g and determination of channel priority le g end: figure 14.13 dual addres s mode/cycle steal mode external bus external bus/ dreq (edge detection), dack (read cycle)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 590 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 source address read write read 1st acceptance 2nd acceptance write bus locked source address destination address bus locked destination address cpu dmac-2 cpu dmac-1 drak0 dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[63:0] : dreq samplin g and determination of channel priority le g end: figure 14.14 dual a ddress mode/burst mode external bus external bus/ dreq (level detection), dack (read cycle)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 591 of 1076 sep 24, 2013 source address read write read 1st acceptance write bus locked source address destination address bus locked destination address cpu dmac-2 cpu dmac-1 te bit: transfer end drak0 dreq1 dreq0 (ed g e detection) dack0 bus cycle a[25:0] ckio d[63:0] : dreq samplin g and determination of channel priority le g end: figure 14.15 dual a ddress mode/burst mode external bus external bus/ dreq (edge detection), dack (read cycle)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 592 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bus cycle (b cyc :p cyc = 1:1) on-chip peripheral address bus ckio source address on-chip peripheral data bus read read read d[63:0] write write write source address source address a[25:0] destination address destination address destination address cpu cpu dmac cpu dmac cpu dmac figure 14.16 dual addres s mode/cycle steal mode on-chip sci (level detection) external bus
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 593 of 1076 sep 24, 2013 bus cycle ckio source address read read read d[63:0] write write write source address source address a[25:0] destination address destination address destination address cpu dmac cpu dmac cpu dmac t1 t2 t1 t2 t1 t2 on-chip peripheral address bus on-chip peripheral data bus (b cyc :p cyc = 1:1) figure 14.17 dual addres s mode/cycle steal mode external bus on-chip sci (level detection)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 594 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 read read read read 1st acceptance cpu cpu cpu dmac cpu dmac dmac cpu dmac source address 2nd acceptance source address 3rd acceptance source address 4th acceptance source address drak0 dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[63:0] : dreq samplin g and determination of channel priority le g end: figure 14.18 single address mode/cycle steal mode external bus external bus/ dreq (level detection)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 595 of 1076 sep 24, 2013 source address read read read 3rd acceptance 1st acceptance 2nd acceptance source address source address cpu cpu dmac cpu dmac cpu dmac drak0 dreq1 dreq0 (ed g e detection) dack0 bus cycle a[25:0] ckio d[63:0] : dreq samplin g and determination of channel priority le g end: figure 14.19 single address mode/cycle steal mode external bus external bus/ dreq (edge detection)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 596 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 source address read read read read 4th acceptance 3rd acceptance 1st acceptance 2nd acceptance source address source address source address cpu dmac-4 dmac-2 dmac-3 cpu dmac-1 : dreq samplin g and determination of channel priority drak0 dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[63:0] le g end: figure 14.20 single address mode/burst mode external bus external bus/ dreq (level detection)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 597 of 1076 sep 24, 2013 source address read read te bit: transfer end read read 1st acceptance source address source address source address cpu dmac-2 dmac-4 dmac-3 cpu dmac-1 drak0 dreq0 (ed g e detection) dack0 bus cycle a[25:0] ckio d[63:0] : dreq samplin g and determination of channel priority le g end: figure 14.21 single address mode/burst mode external bus external bus/ dreq (edge detection)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 598 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 drak0 : dreq samplin g and determination of channel priority dreq1 dreq0 (level detection) dack0 bus cycle a[25:0] ckio d[63:0] 1st acceptance cpu cpu d1 d2 d4 asserted 2 cycles before start of bus cycle asserted 2 cycles before start of bus cycle asserted 2 cycles before start of bus cycle 2nd acceptance 3rd acceptance dmac-1 dmac-2 dmac-3 destination address destination address destination address d1 d2 d4 d1 d2 d3 d4 d3 d3 le g end: figure 14.22 single address mode/burst mode external bus external bus/ dreq (level detection)/32-byte block transfer (bus width: 64 bits, sdram: row hit write)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 599 of 1076 sep 24, 2013 14.3.6 ending dma transfer the conditions for ending dma transfer are differ ent for ending on individual channels and for ending on all channels together. except for the case where transfer ends when the value in the dma transfer count register (dmatcr) reaches 0, the following conditions apply to ending transfer. 1. cycle steal mode (external request, on-chip peripheral module request, auto-request) when a transfer end condition is satisfied, acceptance of dm ac transfer requests is suspended. the dmac completes transfer for th e transfer requests accepted up to the point at which the transfer end conditio n was satisfied, then stops. in cycle steal mode, the operation is the same for both edge and level transfer request detection. 2. burst mode, edge detection (external request, on-chip peripheral module request, auto- request) the delay between the point at which a transfer end condition is satisfied and the point at which the dmac actually stops is the same as in cycle steal mode. in burst mode with edge detection, only the first transfer request activ ates the dmac, but the timing of stop request (de = 0 in chcr, dme = 0 in dmaor) samplin g is the same as the transfer request sampling timing shown in 4 and 5 under operation in section 14.3.5, number of bus cycle states and dreq pin sampling timing. therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the dmac stops. 3. burst mode, level detection (external request) the delay between the point at which a transfer end condition is satisfied and the point at which the dmac actually stops is the same as in cycle steal mode. as in the case of burst mode with edge detection, the timing of stop request (de = 0 in chcr, dme = 0 in dmaor) sampling is the same as the transfer request sampling timing shown in 2 and 3 under operation in section 14.3.5, number of bus cycle states and dreq pin sampling timing. therefore, a transfer request is regarded as having been issued until a st op request is detected, and the corresponding processing is executed before the dmac stops. 4. transfer suspension bus timing transfer suspension is executed on completion of processing for one transfer unit. in dual address mode transfer, write cycl e processing is executed even if a transfer en d condition is satisfied during the read cycle, and the transfers covered in 1, 2, and 3 above are also executed before operation is suspended.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 600 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 conditions for ending transf er on individual channels: transfer ends on the corresponding channel when either of the following conditions is satisfied: ? the value in the dma transfer coun t register (dmatcr) reaches 0. ? the de bit in the dma channel control register (chcr) is cleared to 0. 1. end of transfer when dmatcr = 0 when the dmatcr value reaches 0, dma transf er ends on the corresponding channel and the transfer end flag (te) in chcr is set. if the interrupt enable b it (ie) is set at this time, an interrupt (dmte) request is sent to the cpu. transfer ending when dmatcr = 0 does not follow the procedures described in 1 to 4 in section 14.3.6, ending dma transfer. 2. end of transfer when de = 0 in chcr when the dma enable bit (de) in chcr is cleared, dma transfer is suspended on the corresponding channel. the te bit is not set in this case. transfer ending in this case follows the procedures described in 1 to 4 in section 14.3.6, ending dma transfer. conditions for ending transfer si multaneously on all channels: transfer ends on all channels simultaneously when either of the following conditions is satisfied: ? the address error bit (ae) or nmi flag (nmif) in the dma operation register (dmaor) is set to 1. ? the dma master enable bit (dme ) in dmaor is cleared to 0. 1. end of transfer when ae = 1 in dmaor if the ae bit in dmaor is set to 1 due to an ad dress error, dma transfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6, ending dma transfer, and the bus is passed to the cpu. therefore, when ae is set to 1, the values in the dma source address register (sar), dma destination address re gister (dar), and dma transfer count register (dmatcr) indicate the addresses for the dma transfer to be performed next and the remaining number of tr ansfers. the te bit is not set in this case. before resuming transfer, it is necessary to make a new setting for the channel that caused the address error, then write 0 to the ae bit after first reading 1 from it. acceptance of external requests is suspended while ae is set to 1, so a dma tran sfer request must be reissued when resuming transfer. acceptance of internal requests is also suspe nded, so when resuming transfer, the dma transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 601 of 1076 sep 24, 2013 2. end of transfer when nmif = 1 in dmaor if the nmif bit in dmaor is set to 1 due to an nmi interrupt, dma tran sfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6 , ending dma transfer, and the bus is passed to the cpu. therefor e, when nmif is set to 1, the values in the dma source address register (sar), dma des tination address regist er (dar), and dma transfer count register (dma tcr) indicate the addresses fo r the dma transfer to be performed next and the remaining number of tr ansfers. the te bit is not set in this case. before resuming transfer after nmi interrupt hand ling is completed, 0 must be written to the nmif bit after first reading 1 from it. as in the case of ae being set to 1, acceptance of external requests is suspended while nmif is se t to 1, so a dma transfer request must be reissued when resuming transfer . acceptance of internal request s is also suspended, so when resuming transfer, the dma tran sfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. 3. end of transfer when dme = 0 in dmaor if the dme bit in dmaor is clear ed to 0, dma transfer is suspended on all channels in accordance with the c onditions in 1 to 4 in section 14.3.6 , ending dma transfer, and the bus is passed to the cpu. the te bit is not set in th is case. when dme is cleared to 0, the values in the dma source address regi ster (sar), dma destination address register (dar), and dma transfer count register (d matcr) indicate the addresses for the dma transfer to be performed next and the remaining number of transfers. when resuming transfer, dme must be set to 1. operation will then be resumed from the next transfer.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 602 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.4 examples of use 14.4.1 examples of transfer between external memory and an external device with dack examples of transfer of data in external memory to an external device with dack using dmac channel 1 are considered here. table 14.10 shows the transfer conditions and the corresponding register settings. table 14.10 conditions for transfer between external memory and an external device with dack, and corresponding register settings transfer conditions register set value transfer source: external memory sar1 h'0c000000 transfer source: external device with dack dar1 (accessed by dack) number of transfers: 32 dmatcr1 h'00000020 transfer source address: decremented chcr1 h'000022a5 transfer destination address: (setting invalid) transfer request source: external pin ( dreq1 ) edge detection bus mode: burst transfer unit: word no interrupt request at end of transfer channel priority order: 2 > 0 > 1 > 3 dmaor h'00000201
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 603 of 1076 sep 24, 2013 14.5 on-demand data transfer mode (ddt mode) 14.5.1 operation setting the ddt bit to 1 in dmaor causes a tran sition to on-demand data transfer mode (ddt mode). in ddt mode, it is possible to specify direct single address mode transfer to channel 0 via the data bus and ddt module, and simultaneously issue a transfer request, using the dbreq , bavl , tr , tdack , and id [1:0] signals between an ex ternal device and the dmac. figure 14.23 shows a block diagram of the dmac, ddt, bsc, and an external device (with dbreq , bavl , tr , tdack , id [1:0], and d [63:0] = dtr pins). dmac ddt memory external device (with dbreq , bavl , tr , tdack , and id [1:0]) dtr bsc sar0 dar0 dmatcr0 chcr0 dreq0?3 data buffer bavl bavl dbreq tdack id[1:0] ddtmode data buffer address bus ddtmode tdack id[1:0] data bus request controller tr fifo or memory figure 14.23 on-demand tr ansfer mode block diagram for channels 0 to 3, after making the settings for normal dma transfer using the cpu, a transfer request can be issued from an external device using the dbreq , bavl , tr , tdack , id [1:0], and d [63:0] = dtr signals (handshake protocol using the data bus). a transfer request can also be issued simply by asserting tr , without using the external bus (handshake protocol without use of the data bus). for channel 2, after making the dma transfer settings in the normal way, a transfer request can be issued dir ectly from an external device (with dbreq , bavl , tr , tdack , id [1:0], and d [63:0] = dtr pins) by asserting dbreq and tr simultaneously. note: dtr format = data transfer request format in ddt mode, there is a choice of five modes for performing dma transfer.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 604 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 1. normal data transfer mode (channel 0) bavl (the data bus available signal) is asserted in response to dbreq (the data bus request signal) from an external device. two ckio-synchronous cycles after bavl is asserted, the external data bus drives the data transfer setting command (dtr command) in synchronization with tr (the transfer request signal). the initial settings are then made in the dmac channel 0 control register, and the dma transfer is processed. 2. normal data transfer mode (channels 1 to 3) in this mode, the data transfer settings are made in the dmac from the cpu, and dma transfer requests only are performed from the external device. as in 1 above, dbreq is asserted from the external devi ce and the external bus is secured, then the dtr format is driven. the transfer request channel can be specified by means of the two id bits in the dtr format. 3. handshake protocol using the data bus (valid for channel 0 only) this mode is only valid for channel 0. after the initial settings have been made in the dmac channel 0 control register by means of normal data transfer mode (channel 0) in the SH7750, or after the initial settings have been made in the dmac channel 0 control register from the cpu or by means of normal data transfer mode (channel 0) in the SH7750s, the ddt module assert s a data transfer request for the dmac by setting dtr format id = 00, md = 00, and sz 101 or 110, and driving the dtr format. 4. handshake protocol without use of the data bus the ddt module includes a function for recording the previously asserted request channel. by using this function, it is possible to assert a tr ansfer request for the channel for which a request was asserted immediatel y before, by asserting tr only from an external device after a transfer request has once been made to the channel for which an initial setting has been made in the dmac control register (dtr format and data transfer setting by th e cpu in the dmac). 5. direct data transfer mode (valid for channel 2 only) a data transfer request can be asserted for channel 2 by asserting dbreq and tr simultaneously from an external device after the initial settings have been made in the dmac channel 2 control register.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 605 of 1076 sep 24, 2013 14.5.2 pins in ddt mode figure 14.24 shows the system configuration in ddt mode. synchronous dram dbreq / dreq0 bavl /drak0 tr / dreq1 tdack /dack0 id1, id0/drak1, dack1 ckio d63?d0=dtr external device SH7750, SH7750s, SH7750r a25?a0, ras, cas, we, dqmn, cke figure 14.24 system configuratio n in on-demand data transfer mode ? dbreq : data bus release request signal for transmitti ng the data transfer request format (dtr format) or a dma request from an external device to the dmac if there is a wait for release of the data bus, an external device can have the data bus released by asserting dbreq . when dbreq is accepted, the bsc asserts bavl . ? bavl : data bus d63?d0 release signal assertion of bavl means that the data bus will be released two cycles later. this lsi does not switch the data pins to output status for a total of three cycles: the cycle in which the data bus is released and th e cycles preceding and following it. ? tr : transfer request signal assertion of tr has the following different meanings. ? in normal data transfer mode (channel 0, except channel 0), tr is asserted, and at the same time the dtr format is output, two cycles after bavl is asserted. ? in the case of the handshake protocol without use of the data bus, asserting tr enables a transfer request to be issued for the channel for which a transfer request was made immediately before. this function can be used only when bavl is not asserted two cycles earlier. ? in the case of direct data tran sfer mode (valid only for channe l 2), a direct transfer request can be made to channel 2 by asserting dbreq and tr simultaneously.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 606 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? tdack : reply strobe signal for external device from dmac the assert timing of this signal is the sa me as the dackn assert timing of the memory interfaces. note that it is a low active signal. ? id1, id0: channel number notification signals ? 00: channel 0 (means demand data transfer) ? 01: channel 1 ? 10: channel 2 ? 11: channel 3 data transfer request format sz id md count address r/w 63 61 60 59 57 55 48 31 0 (reserved) figure 14.25 data tr ansfer request format the data transfer request format (dtr format) consists of 64 bits, with connection to d[63:0]. in the case of normal data transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus, the transfer data size, re ad/write access, channel number, transfer request mode, number of transfers, and transfer source or transfer dest ination address are specified. a specification in bits 47?32 is invalid. in the SH7750, only single address mode can be set in normal data transfer mode (channel 0). with the dtr format, ds = (0: md = 10, 11, 1: md = 01), rl = 0, al = 0, dm[1:0] = 01, sm[1:0] = 01, rs[3:0] = (0010: r/w = 0, 0011: r/w = 1), tm = (0: md = 11, 1: md = 01, 10), ts[2:0] = (sz), and ie = 0 settings are made in dma channel control register 0, count is set in transfer count register 0, and address is set in source/destination address register 0. therefore, in ddt mode, the above control registers cannot be written to by the cpu, but can be read. in the SH7750s, dmac control registers chcr0, sar0, dar0, and dmatcr0 can be written to and read by the cpu even in normal data transf er mode (channel 0). caution is necessary in this case, as a dmac control register written to by the cpu will be overwritten by a subsequent transfer request (md[1:0] = 01, 10, or 11) using the dtr format.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 607 of 1076 sep 24, 2013 bits 63 to 61: transmit size (sz2?sz0) ? 000: byte size (8 -bit) specification ? 001: word size (16-bit) specification ? 010: longword size (32-bit) specification ? 011: quadword size ( 64-bit) specification ? 100: 32-byte block transfer specification ? 101: setting prohibited ? 110: request queue clear specification ? 111: transfer end specification bit 60: read/write (r/w) ? 0: memory read specification ? 1: memory write specification bits 59 and 58: channel number (id1, id0) ? 00: channel 0 (demand data transfer) ? 01: channel 1 ? 10: channel 2 ? 11: channel 3 bits 57 and 56: transfer request mode (md1, md0) ? 00: handshake protocol (data bus used) ? 01: burst mode (edge detection) specification ? 10: burst mode (level detection) specification ? 11: cycle steal mode specification bits 55 to 48: transfer count (count7?count0) ? transfer count: 1 to 255 ? 00000000: maximum number of transfers (16m) bits 47 to 32: reserved bits 31 to 0: address (address31?address0) ? r/w = 0: transfer source address specification ? r/w = 1: transfer destin ation address specification notes: 1. only the id field is valid for channels 1 to 3. 2. to start dma transfer by means of demand data transfer on channel 0, the initial value of md in the dtr format must be 01, 10, or 11.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 608 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3. the count field is ignored if md = 00. 4. in edge-sense burst mode, dma transfer is executed continuously. in level-sense burst mode and cycle steal mode, a ha ndshake protocol is used to transfer each unit of data. 5. the maximum number of transfers can be specified by setting count = 0 as dtr format initialization data. if the amount of data to be transferred is unknown, set count = 0, start dma tran sfer, and transfer the dt r format (id = 00, md 00, sz = 111) when the required amount of data has been transferred. this will terminate dma transfer on channel 0. in this case, the te bit in dma channel contro l register 0 is not se t, but transfer cannot be restarted. 6. when port functions are used (bcr2.por ten = 1) and ddt mode is selected, input the dtr format for d[63:52] and d[31:0]. in this case, if id[1:0] = 00, input md[1:0] and sz 101, 110. 7. for dtr format transfer when id[1:0] = 00, input md[1:0] and sz 101, 110. 14.5.3 transfer request accepta nce on each channel on channel 0, a dma data transfer request can be made by means of the dtr format. no further transfer requests are accepted between dtr format acceptance and the end of the data transfer. on channels 1 to 3, output a transfer request from an external device by means of the dtr format (id = 01, 10, or 11) after making dmac control register settings in the same way as in normal dma mode. each of channels 1 to 3 has a reque st queue that can accept up to four transfer requests. when a request queue is full, the fifth and subsequent transfer requests will be ignored, and so transfer requests must not be output. when chcr.te = 1 when a transfer request rema ins in the request queue and a transfer is completed, the request queue retains it. when another transfer request is sent at that time, the transfer request is added to the request queue if the request queue is vacant.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 609 of 1076 sep 24, 2013 tb tc td te tf th ta row h/l t g tk tj ti tad tm tn to tp tq ts tl tr tv tu tt tw tad tad tcsd tcsd row c1 row tdqmd tdqmd trasd tdtrs tdtrh trds trdh tcasd2 tcasd2 trwd dmac channel tidd tidd tbsd dtr 1ckio cycle (10ns f100mhz) tdbqs [2ckio cycle - tdtrs] ( 18ns f100mhz) ttrh ttrs tbavd ckio bank prechar g e-sel address dqmn id1?id0 d63?d0 (read) cs n casn ras dbreq bavl tr tdack bs rd/ wr ttdad ttdad c1 c2 c3 c4 tdbqh tbavd trasd tbsd figure 14.26 single address mode: synchronous dram external device longword transfer sdram auto-precharge read bus cycle, bur st (rcd[1:0] = 01, cas latency = 3, tpc[2:0] = 001)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 610 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tb tc td te tf th ta row h/l t g tk tj ti tad tm tn to tp tq ts tl tr tv tu tt tw tad tad tcsd tcsd row c1 row tdqmd tdqmd tdtrs tdtrh tcasd2 tcasd2 twdd dmac channel tidd tbsd dtr 1ckio cycle (10ns 100mhz) tdbqs [2ckio cycle - tdtrs] (18ns f100mhz) ttrh ttrs tbavd trasd trasd ttdad ttdad trwd trwd tdbqh tbavd tbsd tidd twdd c1 c2 c3 c4 ckio bank prechar g e-sel address dqmn id1?id0 d63?d0 (read) csn casn ras dbreq bavl tr tdack bs rd/ wr figure 14.27 single address mode: external device synchronous dram longword transfer sdram auto-precharge write bus cycle, bur st (rcd[1:0] = 01, trwl[2:0] = 101, tpc[2:0] = 001)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 611 of 1076 sep 24, 2013 tb tc td te tf th ta t g tk tj ti tm tn to tp tq ts tl tr tt trwd tdbqs ckio bank prechar g e-sel addr dqmn id1-id0 d63-d0 (read) csn casn ras dbreq bavl tr tdack bs rd/ wr tad tcsd tad tcsd row row row tad c1 h/l trasd tdqmd tcasd2 tcasd2 trds tbsd tbsd c1 c2 c4 c3 tdqmd trdh dmac channel ttdad ttrs ttrh tbavd [2ckio cycles - tdtrs] (= 18ns: 100mhz) dtr= 1ckio cycle (= 10ns: 100mhz) tdtrs tdtrh tdbqh tbavd trasd ttdad dmac channel figure 14.28 dual add ress mode/synchronous dram sram longword transfer
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 612 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 clk id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl dbreq ra ca d0 d1 d2 d3 rd ba dtr 00 figure 14.29 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-demand data transfer
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 613 of 1076 sep 24, 2013 ra ca wt ba d0 d1 d2 d3 d5 d4 dtr clk id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl dbreq figure 14.30 single address mode/burst mode/external device external bus 32-byte block transfer/channel 0 on-demand data transfer
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 614 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ra ca ca ca d1 d0 dtr ba rd rd rd 00 00 clk id1, id0 ras, cas, we d63?d0 a25?a0 dqmn figure 14.31 single address mode/burst mode/external bus external device 32-bit transfer/channel 0 on-demand data transfer
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 615 of 1076 sep 24, 2013 ra ca ca d1 d0 dtr ba wt wt clk id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl dbreq dqmn figure 14.32 single address mode/burst mode/external device external bus 32-bit transfer/channel 0 on-demand data transfer
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 616 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ca ca d0 d1 dtr md = 00 d0 d1 d2 d3 wt wt dtr md = 10 or 11 start of data transfer next transfer request clk id1, id0 tdack d63?d0 a25?a0 tr bavl dbreq cmd figure 14.33 handshake protocol using data bus (channel 0 on-demand data transfer)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 617 of 1076 sep 24, 2013 ca ca d0 d1 d2 d3 d0 d1 d2 d3 wt wt md = 10 or 11 start of data transfer next transfer request clk id1, id0 tdack dtr d63?d0 a25?a0 tr bavl dbreq cmd figure 14.34 handshake protocol without use of data bus (channel 0 on-demand data transfer)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 618 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 clk dbreq bavl tr a25?a0 d63?d0 ras, cas, we d0 ra ca d1 d2 d3 ba rd figure 14.35 read from synchronous dram precharge bank clk dbreq bavl tr a25?a0 d63?d0 ras, cas, we ra ca d0 d1 d2 d3 pch ba rd transfer requests can be accepted figure 14.36 read from synchronous dram non-precharge bank (row miss)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 619 of 1076 sep 24, 2013 clk dbreq bavl tr a25?a0 d63?d0 ras, cas, we ca rd d0 d1 d2 d3 figure 14.37 read from synchronous dram (row hit) clk dbreq bavl tr a25?a0 d63?d0 ras, cas, we ra ca ba wt d0 d1 d2 d3 figure 14.38 write to synchronous dram precharge bank
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 620 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 clk dbreq bavl tr a25?a0 d63?d0 ras, cas, we ra ca d0 d1 d2 d3 pch ba wt transfer requests can be accepted figure 14.39 write to synchronous dram non-precharge bank (row miss) clk a25?a0 d63?d0 ras, cas, we d0 ca d1 d2 d3 wt figure 14.40 write to synchronous dram (row hit)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 621 of 1076 sep 24, 2013 00 d0 d1 d2 ra ca rd ba dtr clk id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl dbreq figure 14.41 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-demand data transfer
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 622 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 dma operation register (dmaor) 31 15 9 8 2 1 0 ddt pr[1:0] ae nmif dme cod (SH7750s) 4 ddt: 0: normal dma mode 1: on-demand data transfer mode figure 14.42 ddt mode setting dtr md = 01 ca ca d0 d1 d2 d3 d0 d1 d2 d3 d1 d2 d3 wt wt clk id1, id0 tdack cmd d63?d0 a25?a0 tr bavl dbreq start of data transfer no dma request sampling figure 14.43 single address mo de/burst mode/edge detection/ external device external bus data transfer
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 623 of 1076 sep 24, 2013 ca ca d0 d1 d2 d3 d0 d1 d2 d3 dtr md = 10 rd rd start of data transfer wait for next dma request clk id1, id0 tdack cmd d63?d0 a25?a0 tr bavl dbreq figure 14.44 single address mo de/burst mode/level detection/ external bus external device data transfer
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 624 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ca ca ca rd rd rd dtr d0 d3 d2 clk id1, id0 tdack dqmn d63?d0 a25?a0 tr bavl dbreq cmd idle cycle idle cycle idle cycle md = 01 figure 14.45 single address mode/burst mode/edge detection/by te, word, longword, quadword/external bus external device data transfer
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 625 of 1076 sep 24, 2013 ca ca ca wt dtr d0 d3 d1 clk id1, id0 tdack dqmn d63?d0 a25?a0 tr bavl dbreq cmd idle cycle md = 01 idle cycle idle cycle wt wt figure 14.46 single address mode/burst mode/edge detection/by te, word, longword, quadword/external device external bus data transfer
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 626 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 dtr id = 1, 2, or 3 ra ca ba rd d0 d1 d2 d3 clk id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl dbreq 01 or 10 or 11 figure 14.47 single address mode/burst mode/32-byte block transfer/dma transfer request to channels 1?3 using data bus
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 627 of 1076 sep 24, 2013 ra ca ba rd 10 d0 d1 d2 d3 d4 d5 d6 d7 clk id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl dbreq no dtr cycle, so requests can be made at any time figure 14.48 single address mode/b urst mode/32-byte block transfer/ external bus external device data transfer/ direct data transfer request to ch annel 2 without using data bus
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 628 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 clk id1, id0 d63?d0 a25?a0 ras, cas, we 3rd 4th 5th four requests can be queued handshaking is necessary to send additional requests must be ignored (no request transmitted) ca ca ra ba rd nop rd ca d1 d2 d3 d0 d1 d2 d3 d1 d2 rd d0 d0 no more requests 2nd 1st figure 14.49 single address mode/burst mode/external bus external device data transfer/direct data tran sfer request to channel 2
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 629 of 1076 sep 24, 2013 clk id1, id0 tdack d63?d0 a25?a0 tr bavl dbreq ras, cas, we 3rd 4th 5th four requests can be queued handshaking is necessary to send additional requests ca ca ra ca ca d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 ba wt wt wt wt must be ignored (no request transmitted) 2nd 1st figure 14.50 single address mode/burst mode/external device external bus data transfer/direct data tran sfer request to channel 2
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 630 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 clk id1, id0 tdack d63?d0 a25?a0 tr bavl dbreq ras, cas, we 3rd 4th 5th ca ca ca ca d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 rd rd rd rd four requests can be queued handshaking is necessary to send additional requests must be ignored (no request transmitted) 2nd 1st figure 14.51 single address mode/burst mode/external bus external device data transfer (active bank address)/direct data transfer request to channel 2
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 631 of 1076 sep 24, 2013 clk id1, id0 tdack d63?d0 a25?a0 tr bavl dbreq ras, cas, we 3rd 4th 5th ca ca ca ca d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 wt wt wt wt four requests can be queued handshaking is necessary to send additional requests must be ignored (no request transmitted) 2nd 1st figure 14.52 single address mode/burst mode/external device external bus data transfer (active bank address)/direct data transfer request to channel 2 14.5.4 notes on use of ddt module 1. normal data transfer mode (channel 0) initial settings for channel 0 demand transfer must be dtr.id = 00 and dtr.md = 01, 10, or 11. in this case, only single address mode can be set for channel 0. 2. normal data transfer mode (channels 1 to 3) if a setting of dtr.id = 01, 10, or 11 is made, dtr.md will be ignored. 3. handshake protocol using the data bus (valid on channel 0 only) a. the handshake protocol using the data bus can be executed only on channel 0. (set dtr.id = 00, dtr.md = 00, dtr.sz 101 or 110. operation is not guaranteed if settings of dtr.id = 00, dtr.md = 00, and dtr.sz = 101 or 110 are made.)
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 632 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 b. if, during execution of the handshake protocol using the data bus for channel 0, a request is input for one of channels 1 to 3, and after that dma transfer is executed settings of dtr.id = 00, dtr.md = 00, and dtr, sz 101.110 are input in the handshake protocol using the data bus, a transfer requ est will be asserted for channel 0. c. in the SH7750s and SH7750r, initial settings can be made in the dmac channel 0 control register from the cpu (possible settings are chcr0.rs = 0000, 0010, or 0011). if settings of dtr.id = 00, dtr.md = 00, and dtr.sz 101 or 110 are subsequently input, a transfer request to channel 0 will be asserted. 4. handshake protocol without use of the data bus a. with the handshake protocol without use of the data bus, a dma transfer request can be input to the dmac again for the channel fo r which transfer was requested immediately before by asserting tr only. b. when using the handshake protocol without use of the data bus, first make the necessary settings in the dmac control registers. c. when not using the handshake protocol without use of the data bus, if tr only is asserted without outputting dtr, a request will be issu ed for the channel for which dma transfer was requested immediately before. also, if th e first dma transfer request after a power-on reset is input by asserting tr only, it will be ignored and the dmac will not operate. d. if tr only is asserted by means of the handshake protocol without use of the data bus and a dma transfer request is input when channel 0 dma transfer has ended and chcr0.te = 1, the dmac will freeze. before issuing a dm a transfer request, the te flag must be cleared by writing chcr0.te = 0 after reading chcr0.te = 1. 5. direct data transfer mode (valid on channel 2 only) a. if a dma transfer request for channel 2 is input by simultaneous assertion of dbreq and tr during dma transfer execution with the handshake protocol without use of the data bus, it will be accepted if there is space in the ddt channel 2 request queue. b. in direct data transfer mode (with dbreq and tr asserted simultaneously), dbreq is not interpreted as a bus arbitra tion signal, and therefore the bavl signal is never asserted. 6. request queue tran sfer request acceptance a. the ddt has four request queues for each of channels 1 to 3. when these request queues are full, a dma transfer request from an external device will be ignored. b. if a dma transfer request for channel 0 is input during execution of a channel 0 dma bus cycle, the ddt will ignore that request. conf irm that channel 0 dma transfer has finished (burst mode) or that a dma bus cycle is not in progress (cycle steal mode).
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 633 of 1076 sep 24, 2013 7. dtr format a. the ddt module processes dtr.id , dtr.md, and dtr.sz as follows. when dtr.id= 00 ? md = 00, sz 101, 110: handshake protocol using the data bus ? md 00, sz = 111: chcr0.de = 0 setting (dma transfer end request) ? md 10, sz = 110: ddt request queue clear when dtr.id 00 ? transfer request to channels 1?3 (items other than id ignored) 8. data transfer end request a. a data transfer end request (dtr.id = 00, md 00, sz = 111) cannot be accepted during channel 0 dma transfer. therefore, if edge detection and burst mode are set for channel 0, transfer cannot be ended midway. b. when a transfer end request (dtr.id = 00, md 00, sz = 111) is accepted, the values set in chcr0, sar0, dar0, and dmatcr0 are retained. with the SH7750, execution cannot be restarted from an external device in this case. to restart execution in the SH7750s and SH7750r, set chcr0.de = 1 with an mov instruction. 9. request queue clearance a. when settings of dtr.id = 00, dtr.md = 10, and sz = 110 are accepted by the ddt in normal data transfer mode, ddt channel 0 requests and channel 1 to 3 request queues are all cleared. all external requests held on the dmac side are also cleared. b. in case 4-d, the dmac freeze state can be cleared. c. when settings of dmaor.ddt = 1, dtr.id = 00, dtr.md = 10, and sz = 110 are accepted by the ddt in case 11, the dmac freeze state can be cleared. 10. dbreq assertion a. after dbreq is asserted, do not assert dbreq again until bavl is asserted, as this will result in a discrepancy between the number of dbreq and bavl assertions. b. the bavl assertion period due to dbreq assertion is one cycle. if a row address miss occurs in a read or write in the non-precharged bank during synchronous dram access, bavl is asserted for a number of cycles in accordance with the ras precharge interval set in bsc.mcr.tcp. c. it takes one cycle for dbreq to be accepted by the dmac after being asserted by an external device. if a row address miss occurs at this time in a read or write in the non- precharged bank during sy nchronous dram access, and bavl is asserted, the dbreq signal asserted by the external device is ignored. therefore, bavl is not asserted again due to this signal.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 634 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 11. clearing ddt mode check that dma transfer is not in progress on any channel before setting the dmaor.ddt bit. if the dmaor.ddt setting is changed from 1 to 0 during dma transfer in ddt mode, the dmac will freeze. this also applies when switching from normal dma mode (dmaor.ddt = 0) to ddt mode. 12. confirming dma transfer requests and number of transfers executed the channel associated with a dma bus cycle be ing executed in response to a dma transfer request can be confirmed by determining the level of external pins id1 and id0 at the rising edge of the ckio clock while tdack is asserted. (id = 00: channel 0; id = 01: channel 1; id = 10: channel 2; id = 11: channel 3) 14.6 configuration of the dmac (SH7750r) 14.6.1 block diagram of the dmac figure 14.53 is a block diagram of the dmac in the SH7750r.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 635 of 1076 sep 24, 2013 request 8 dmaqueclr0-7 queclr0?7 sar0, dar0, dmatcr0, chcr0 only ddtmode bavl 48 bits ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 request controller dtr command buffer ddt module ddtd external bus tr dbreq tdack id[2:0] tdack id[1:0] d[63:0] dbreq bavl / id2 sarn darn dmatcrn chcrn dmaor bus interface peripheral bus internal bus dmac module count control registr control activation control request priority control 32b data buffer bus state controller on-chip peripheral module external address/on-chip peripheral module address tmu sci, scif dack0, dack1 drak0, drak1 dreq0 , dreq1 legend: dmaorn: sarn: darn: dmatcrn: chcrn: note: n = 0 to 7 dmac operation register dmac source address register dmac destination address register dmac transfer count register dmac channel control register figure 14.53 block diagram of the dmac
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 636 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.6.2 pin configuration (SH7750r) tables 14.11 and 14.12 show the pin configuration of the dmac. table 14.11 dmac pins channel pin name a bbreviation i/o function 0 dma transfer request dreq0 input dma transfer request input from external device to channel 0 dreq acceptance confirmation drak0 output acceptance of request for dma transfer from channel 0 to external device notification to exte rnal device of start of execution dma transfer end notification dack0 output strobe output to external device of dma transfer request from channel 0 to external device 1 dma transfer request dreq1 input dma transfer request input from external device to channel 1 dreq acceptance confirmation drak1 output acceptance of request for dma transfer from channel 1 to external device notification to exte rnal device of start of execution dma transfer end notification dack1 output strobe output to external device of dma transfer request from channel 1 to external device
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 637 of 1076 sep 24, 2013 table 14.12 dmac pins in ddt mode pin name abbreviation i/o function data bus request dbreq ( dreq0 ) input data bus release request from external device for dtr format input data bus available bavl / id2 (drak0) output data bus release notification data bus can be used 2 cycles after bavl is asserted notification of channel number to external device at same time as tdack output transfer request signal tr ( dreq1 ) input if asserted 2 cycles after bavl assertion, dtr format is sent only tr asserted: dma request dbreq and tr asserted simultaneously: direct request to channel 2 dmac strobe tdack (dack0) output reply strobe signal for external device from dmac channel number notification id[1:0] (drak1, dack1) output notification of channel number to external device at same time as tdack output (id [1] = drak1, id [0] = dack1) requests for dma transfer from external de vices are normally accepte d only on channel 0 ( dreq0 ) and channel 1 ( dreq1 ). in ddt mode, the bavl pin functions as both the data-bus- available pin and channel-number-notification ( id2 ) pin. 14.6.3 register configuration (SH7750r) table 14.13 shows the configuration of the dmac's registers. the dmac of the SH7750r has a total of 33 registers: four regist ers are assigned to each channel, an d there is a control register for the overall control of the dmac.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 638 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 14.13 register configuration chan- nel name abbre- viation read/ write initial value p4 address area 7 address access size dma source address register 0 sar0 r/w * 2 undefined h'ffa00000 h'1fa00000 32 dma destination address register 0 dar0 r/w * 2 undefined h'ffa00004 h'1fa00004 32 dma transfer count register 0 dmatcr0 r/w * 2 undefined h'ffa00008 h'1fa00008 32 0 dma channel control register 0 chcr0 r/w * 1 * 2 h'00000000 h'ffa0000c h'1fa0000c 32 dma source address register 1 sar1 r/w undefined h'ffa00010 h'1fa00010 32 dma destination address register 1 dar1 r/w undefined h'ffa00014 h'1fa00014 32 dma transfer count register 1 dmatcr1 r/w undefined h'ffa00018 h'1fa00018 32 1 dma channel control register 1 chcr1 r/w * 1 h'00000000 h'ffa0001c h'1fa0001c 32 dma source address register 2 sar2 r/w undefined h'ffa00020 h'1fa00020 32 dma destination address register 2 dar2 r/w undefined h'ffa00024 h'1fa00024 32 dma transfer count register 2 dmatcr2 r/w undefined h'ffa00028 h'1fa00028 32 2 dma channel control register 2 chcr2 r/w * 1 h'00000000 h'ffa0002c h'1fa0002c 32 dma source address register 3 sar3 r/w undefined h'ffa00030 h'1fa00030 32 dma destination address register 3 dar3 r/w undefined h'ffa00034 h'1fa00034 32 dma transfer count register 3 dmatcr3 r/w undefined h'ffa00038 h'1fa00038 32 3 dma channel control register 3 chcr3 r/w * 1 h'00000000 h'ffa0003c h'1fa0003c 32 com- mon dma operation register dmaor r/w * 1 h'00000000 h'ffa00040 h'1fa00040 32
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 639 of 1076 sep 24, 2013 chan- nel name abbre- viation read/ write initial value p4 address area 7 address access size dma source address register 4 sar4 r/w undefined h'ffa00050 h'1fa00050 32 dma destination address register 4 dar4 r/w undefined h'ffa00054 h'1fa00054 32 dma transfer count register 4 dmatcr4 r/w undefined h'ffa00058 h'1fa00058 32 4 dma channel control register 4 chcr4 r/w * 1 h'00000000 h'ffa0005c h'1fa0005c 32 dma source address register 5 sar5 r/w undefined h'ffa00060 h'1fa00060 32 dma destination address register 5 dar5 r/w undefined h'ffa00064 h'1fa00064 32 dma transfer count register 5 dmatcr5 r/w undefined h'ffa00068 h'1fa00068 32 5 dma channel control register 5 chcr5 r/w * 1 h'00000000 h'ffa0006c h'1fa0006c 32 dma source address register 6 sar6 r/w undefined h'ffa00070 h'1fa00070 32 dma destination address register 6 dar6 r/w undefined h'ffa00074 h'1fa00074 32 dma transfer count register 6 dmatcr6 r/w undefined h'ffa00078 h'1fa00078 32 6 dma channel control register 6 chcr6 r/w * 1 h'00000000 h'ffa0007c h'1fa0007c 32 7 dma source address register 7 sar7 r/w undefined h'ffa00080 h'1fa00080 32 dma destination address register 7 dar7 r/w undefined h'ffa00084 h'1fa00084 32 dma transfer count register 7 dmatcr7 r/w undefined h'ffa00088 h'1fa00088 32 dma channel control register 7 chcr7 r/w * 1 h'00000000 h'ffa0008c h'1fa0008c 32 notes: longword access should be used for all control registers. if a different access width is used, reads will return all 0s and writes will not be possible. 1. bit 1 of chcr0?chcr7 and bits 2 and 1 of dmaor can only be written with 0 after being read as 1, to clear the flags. 2. in the SH7750r, writes from the cpu a nd writes from external i/o devices using the dtr format are possible in ddt mode.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 640 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.7 register descriptions (SH7750r) 14.7.1 dma source address registers 0 ? 7 (sar0 ? sar7) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dma source address registers 0 ? 7 (sar0 ? sar7) are 32-bit readable /writable registers that specify the source address for a dm a transfer. the functions of thes e registers are the same as on the SH7750 or SH7750s. for more information, see section 14.2.1, dma source address registers 0 ? 3 (sar0 ? sar3). 14.7.2 dma destination address registers 0 ? 7 (dar0 ? dar7) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dma destination address registers 0 ? 7 (dar0 ? dar7) are 32-bit readable /writable registers that specify the destination address fo r a dma transfer. the functions of these registers are the same as on the SH7750 and SH7750s. for more info rmation, see section 14.2.2, dma destination address registers 0 ? 3 (dar0 ? dar3).
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 641 of 1076 sep 24, 2013 14.7.3 dma transfer count registers 0 ? 7 (dmatcr0 ? dmatcr7) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? r/w: r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dma transfer count registers 0 ? 7 (dmatcr0 ? dmatcr7) are 32-bit read able/writable registers that specify the number of transfers in transf er operations for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). functions of these registers are the same as the transfer-count re gisters of the SH7750 or SH7750s. for more information, see sec tion 14.2.3, dma transf er count registers 0 ? 3 (dmatcr0 ? dmatcr3). 14.7.4 dma channel control registers 0 ? 7 (chcr0 ? chcr7) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ssa 2 ssa 1 ssa 0 stc dsa 2 dsa 1 dsa 0 dtc ? ? ? ? ds rl am al initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r r r r r/w (r/w) r/w (r/w) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 tm ts2 ts1 ts0 qcl ie te de initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/( w) r/w r/( w) r/w dma channel control registers 0 ? 7(chcr0 ? chcr7) are 32-bit readable/w ritable registers that specify the operating mode, transfer me thod, etc., for each channel. bits 31 ? 28 and 27 ? 24 correspond to the source address and destination address, respectively; these settings are only valid when the transfer involves the cs5 or cs6 space and the relevant space has been specified as a pcmcia-interface space. in other cases, these bits should be clear ed to 0. for more information
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 642 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 about the pcmcia interface, see section 13.3.7, pcmc ia interface, in section 13, bus state controller (bsc). no function is assigned to bits 18 and 16 of the chcr2?chcr7 registers. writing to these bits of the chcr2?chcr7 registers is invalid. if, however, a value is written to these bits, it should always be 0. these bits are always read as 0. these registers are initialized to h'00000000 by a power-on or manual reset. their values are retained in standby, sleep, and deep-sleep modes. bits 31 to 29?source address space attribute specification (ssa2?ssa0): these bits specify the space attribute for pcmc ia access. these bits are only valid in the case of page mapping to pcmcia connected to areas 5 and 6. for details of the settings, see the description of the ssa2- ssa0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 28?source address wait control select (stc): specifies cs5 or cs6 space wait control for pcmcia access. this bit selects the wait contro l register in the bsc that performs area 5 and 6 wait cycle control. for details of the settings, see the description of the stc bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 27 to 25?destination address space attribute specification (dsa2?dsa0): these bits specify the space attribute for pcmcia access. th ese bits are only valid in the case of page mapping to pcmcia connected to areas 5 and 6. fo r details of the settings, see the description of the dsa2 ? dsa0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 24?destination address wait control select (dtc): specifies cs5 or cs6 space wait cycle control for pcmcia access. this bit selects the wait control register in the bsc that performs area 5 and 6 wait cycle control. for details of the settings, see the description of the dtc bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 23 to 20?reserved: these bits are always read as 0, and should only be written with 0. bit 19? dreq select (ds): specifies either low level detection or falling edge detection as the sampling method for the dreq pin used in external request mode. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, it is valid in chcr0?chcr7. for details of the settings, see the description of the ds bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 18?request check level (rl): selects whether the drak signa l (that notifies an external device of the acceptance of dreq ) is an active-high or active-low output.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 643 of 1076 sep 24, 2013 this bit is valid only in chcr0 and chcr1 in normal mode, and is invalid in ddt mode. for details of the settings, see the description of the rl bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 17?acknowledge mode (am): in dual address mode, selects whether dack is output in the data read cycle or write cycle. in single addre ss mode, dack is always output regardless of the setting of this bit. in normal dma mode, this bit is valid only in chcr0 and chcr1. in ddt mode, it is valid in chcr0?chcr7. (ddt mode: tdack ) for details of the settings, see the description of the am bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 16?acknowledge level (al): specifies the dack (acknowledge) signal as active-high or active-low. this bit is valid only in chcr0 and chcr1 in normal mode, and is invalid in ddt mode. for details of the settings, see the description of the al bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 15 and 14?destination address mode 1 and 0 (dm1, dm0): these bits specify incrementing/decrementing of the dma transfer destination addres s. the specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. for details of the settings, see the description of the dm1 and dm0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 13 and 12?source addre ss mode 1 and 0 (sm1, sm0): these bits specify incrementing/decrementing of the dm a transfer source address. the specification of these bits is ignored when data is transferre d from an external device to ex ternal memory in single address mode. for details of the settings, see the descrip tion of the sm1 and sm0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 11 to 8?resource select 3 to 0 (rs3?rs0): these bits specify the tr ansfer request source. for details of the settings, see the description of the rs3 ? rs0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 7?transmit mode (tm): specifies the bus mode for transfer. for details of the settings, see the description of the tm bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bits 6 to 4?transmit size 2 to 0 (ts2?ts0): these bits specify the transfer data size (access size). for details of the settings, see the description of the ts2 ? ts0 bits in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3).
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 644 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 3 ? request queue clear (qcl): writing a 1 to this bit clears the request queues of the corresponding channel as well as any external requests that have already been accepted. this bit is only functional when dmaor.ddt = 1 and dmaor.dbl = 1. chcr bit 3 qcl description 0 this bit is always read as 0. (initial value) writing a 0 to this bit is invalid. 1 when dmaor.dbl = 1, writing a 1 to th is bit clears the request queues on the ddt side and any external requests stor ed in the dmac. the written value is not retained. bit 2?interrupt enable (ie): when this bit is set to 1, an interrupt request (dmte) is generated after the number of data tran sfers specified in dmatcr (whe n te = 1). for details of the settings, see the description of the ie bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 1?transfer end (te): this bit is set to 1 after the number of transfers specified in dmatcr. if the ie bit is set to 1 at this tim e, an interrupt request (dmte) is generated. if data transfer ends before te is set to 1 (for ex ample, due to an nmi inte rrupt, address error, or clearing of the de bit or the dme bit in dmaor), th e te bit is not set to 1. when this bit is 1, the transfer enabled state is not ente red even if the de bit is set to 1. for details of the settings, see the description of the te bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3). bit 0?dmac enable (de): enables operation of the corresponding channel. for details of the settings, see the description of the de bit in section 14.2.4, dma channel control registers 0 ? 3 (chcr0 ? chcr3).
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 645 of 1076 sep 24, 2013 14.7.5 dma operation register (dmaor) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ddt dbl ? ? ? ? pr1 pr0 ? ? ? ? ? ae nmif dme initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r r r/w r/w r r r r r r/(w) r/(w) r/w dmaor is a 32-bit readable/writable register that specifies the dmac transfer mode. dmaor is initialized to h'00000000 by a power-on or manual reset. they retain their values in standby mode and deep sleep mode. bits 31 to 16?reserved: these bits are always read as 0, and should only be written with 0. bit 15?on-demand data transfer (ddt): specifies on-demand data transfer mode. for details of the settings, see the description of the ddt bit in section 14.2.5, dma operation register (dmaor) bit 14 ? number of ddt-mode channels (dbl): selects the number of channels that are able to accept external requests in ddt mode. bit 14: dbl description 0 four ddt-mode channels (initial value) 1 eight ddt-mode channels note: when dmaor.dbl = 0, channels 4 to 7 cannot accept external requests. when dmaor.dbl = 1, one channel can be selected from among channels 0 ? 7 by the combination of dtr.sz and dtr.id in the dtr format (see figure 14.54). table 14.14 shows the channel selection by dtr format in the ddt mode.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 646 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 14.14 channel selection by dtr format (dmaor.dbl = 1) dtr.id[1:0] dtr.sz[2:0] 101 dtr.sz[2:0] = 101 00 ch0 ch4 01 ch1 ch5 10 ch2 ch6 11 ch3 ch7 sz id md count address r/w (reserved) 63 61 60 59 58 57 56 55 4847 32 31 0 figure 14.54 dtr format (tra nsfer request format) (SH7750r) bits 13 to 10?reserved: these bits are always read as 0, and should only be written with 0. bits 9 and 8?priority mode 1 and 0 (pr1, pr0): these bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. dmaor bit 9 dmaor bit 8 pr1 pr0 description 0 0 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 > ch6 > ch7 (initial value) 0 1 ch0 > ch2 > ch3 > ch4 > ch5 > ch6 > ch7 > ch1 1 0 ch2 > ch0 > ch1 > ch3 > ch4 > ch5 > ch6 > ch7 1 1 round robin mode bits 7 to 3?reserved: these bits are always read as 0, and should only be written with 0. bit 2?address e rror flag (ae): indicates that an address er ror has occurred during dma transfer. if this bit is set duri ng data transfer, tran sfers on all channels are suspended, and an interrupt request (dmae) is generated. the cp u cannot write 1 to ae. this bit can only be cleared by writing 0 after reading 1. for details of the settings, see the description of the ae bit in section 14.2.5, dma oper ation register (dmaor) bit 1?nmi flag (nmif): indicates that nmi has been input. this bit is set regardless of whether or not the dmac is operating. if this b it is set during data tr ansfer, transfers on all channels are suspended. the cpu cannot write 1 to nmif. this bit can only be cleared by writing 0 after reading 1. for details of the settings, see th e description of the nmif bit in section 14.2.5, dma operation register (dmaor)
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 647 of 1076 sep 24, 2013 bit 0?dmac master enable (dme): enables activation of the entire dmac. when the dme bit and the de bit of the chcr register for the co rresponding channe l are set to 1, that channel is enabled for transfer. if this bi t is cleared during data transfer , transfers on all channels are suspended. even if the dme bit has been set, transfer is no t enabled when te is 1 or de is 0 in chcr, or when the nmi or ae bit in dmaor is 1. for details of the settings, see the description of the dme bit in section 14.2.5, dma operation register (dmaor) 14.8 operation (SH7750r) operation specific to the SH7750r is described here. for details of operation, see section 14.3, operation. 14.8.1 channel specification fo r a normal dma transfer in normal dma transfer mode, the dmac always operates with eight channels, and external requests are only accepted on channel 0 ( dreq ) and channel 1 ( dreq1 ). after setting the registers of the channels in use, including chcr, sar, dar, and dmatcr, dma transfer is started on receiving a dma transfer request in the transfer-enabled state (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), in the order of predetermined priority. the transfer ends when the transfer-end condition is satisfied. ther e are three modes for transfer requests: auto- request, external request, and on-chip peripheral module request. the addressing modes for dma transfer are the single-address mode and the dual- address mode. bus mode is selectable between burst mode and cycle steal mode. 14.8.2 channel specification for ddt-mode dma transfer for dma transfer in ddt mode, the dmaor.dbl se tting selects either fo ur or eight channels. external requests are accepted on channels 0 ? 3 when dmaor.dbl = 0, and on channels 0 ? 7 when dmaor.dbl = 1. for further information on these settings, see the entry on the dbl bit in section 14.7.5, dma operation register (dmaor).
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 648 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.8.3 transfer channel notification in ddt mode when the dmac is set up for four-channel external request acceptance in ddt mode (dmaor.dbl = 0), the id [1:0] bits are used to notify the external device of the dmac channel that is to be used. for more details, see section 14.5, on-demand data transfer mode (ddt mode). when the dmac is set up for eight-channe l external request acceptance in ddt mode (dmaor.dbl = 1), the id [1:0] bits and the simultaneous (on the timing of tdack assertion) assertion of id2 from the bavl (data bus available) pin are used to notify the external device of the dmac channel that is to be used (see table 14.15). when the dmac is set up for eight-channe l external request acceptance in ddt mode (dmaor.dbl = 1), it is important to note that the bavl pin has the two functions as shown in table 14.16. table 14.15 notification of transf er channel in eight-channel ddt mode bavl / id2 id[1:0] transfer channel 00 ch0 01 ch1 10 ch2 1 11 ch3 0 00 ch4 01 ch5 10 ch6 11 ch7 table 14.16 function of bavl function of bavl tdack = high bus available tdack = low notification of channel number ( id2 )
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 649 of 1076 sep 24, 2013 14.8.4 clearing request queu es by dtr format in ddt mode, the request queues of any channel can be cleared by using dtr.id, dtr.md, dtr.sz, and dtr.count [7:4] in a dtr format . this function is only available when dmaor.dbl = 1. table 14.17 shows the dtr fo rmat settings for clearing request queues. table 14.17 dtr format for clearing request queues dmaor.dbl dtr.id dtr.md dtr.sz dtr.count[7:4] description 10 clear the request queues of all channels (1 ? 7). clear the ch0 request-accepted flag 0 00 11 110 * setting prohibited 10 * clear the request queues of all channels (1 ? 7). clear the ch0 request-accepted flag. 0001 clear the ch0 request-accepted flag 0010 clear the ch1 request queues. 0011 clear the ch2 request queues. 0100 clear the ch3 request queues. 0101 clear the ch4 request queues. 0110 clear the ch5 request queues. 0111 clear the ch6 request queues. 1 00 11 110 1000 clear the ch7 request queues. note: (SH7750r) dtr.sz = dtr[63:61], dt r.id = dtr[59:58], dtr.md = dtr[57:56], dtr.count[7:4] = dtr[55:52] 14.8.5 interrupt-request codes when the number of transfers sp ecified in dmatcr has been finished and the interrupt request is enabled (chcr.ie = 1), a transf er-end interrupt requ est can be sent to the cpu from each channel. table 14.18 lists the interrupt-request c odes that are associated with these transfer-end interrupts.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 650 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 14.18 dmac interrupt-request codes source of the interrupt descri ption intevt code priority dmte0 ch0 transfer-end interrupt h'640 high dmte1 ch1 transfer-end interrupt h'660 dmte2 ch2 transfer-end interrupt h'680 dmte3 ch3 transfer-end interrupt h'6a0 dmte4 ch4 transfer-end interrupt h'780 dmte5 ch5 transfer-end interrupt h'7a0 dmte6 ch6 transfer-end interrupt h'7c0 dmte7 ch7 transfer-end interrupt h'7e0 dmae address error interrupt h'6c0 low note: dmte4 ? dmte7: these codes are not us ed in the SH7750 or SH7750s. ckio ra dtr ca d1 d2 rd ba 00 id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl / id2 dbreq d0 figure 14.55 single address mode/burst mode/external bus external device 32-byte block transfer/channel 0 on-demand data transfer
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 651 of 1076 sep 24, 2013 ckio ra dtr ca d1 d2 rd ba 00 id1, id0 tdack ras, cas, we d63?d0 a25?a0 tr bavl / id2 dbreq d0 figure 14.56 single address mode/burst mode/external bus external device/32-byte block transfer/ on-demand data transfer on channel 4
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 652 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 14.9 usage notes 1. when modifying sar0?sar3, dar0?dar3, dmatcr0?dmatcr3, and chcr0? chcr3 in the SH7750 or SH7750s or when modifying sar0?sar7, dar0?dar7, dmatcr0?dmatcr7, and chcr0?chcr7 in the sh 7750r, first clear the de bit for the relevant channel. 2. the nmif bit in dmaor is set when an nmi interrupt is input even if the dmac is not operating. confirmation method when dma tran sfer is not executed correctly: with the SH7750 and SH7750s, read the nmif, ae, and dme bits in dmaor, the de and te bits in chcr0?chcr3, and dmatcr0?dmatcr3. with the SH7750r, read the nmif, ae, and dme bits in dmaor, the de and te bits in chcr0?chcr7, and dmatcr0?dmatcr7. if nmif was set before the transfer, the dmatcr transfer count will remain at the set value. if nmif was set during the transfer, when the de bit is 1 and the te bit is 0 in chcr0?chcr3 in the SH7750 or SH7750s or chcr0?chcr7 in the SH7750r, the dmatcr value will indicate the remaining number of transfers. also, the next addresses to be accessed can be found by reading sar0?sar3 and dar0? dar3 in the SH7750 or SH7750s or sar0?sar7 and dar0?dar7 in the SH7750r. if the ae bit has been set, an address error has occu rred. check the set valu es in chcr, sar, and dar. 3. check that dma transfer is not in progress before making a transition to the module standby state, standby mode, or deep sleep mode. either check that te = 1 in the SH7750 or SH7750s's chcr0?chcr3 or in the SH7750r's chcr0?chcr7, or clear dme to 0 in dmaor to terminate dma transfer. when dme is cleared to 0 in dmaor, transfer halts at th e end of the currently executing dma bus cycle. note, therefore, that tr ansfer may not end immediately, depe nding on the transfer data size. dma operation is not guaranteed if the module standby state, standby mode, or deep sleep mode is entered without confirming that dma transfer has ended. 4. do not specify a dmac, ccn, bsc, or ubc cont rol register as the dmac transfer source or destination. 5. when activating the dmac, make the sar, dar, and dmatcr register settings for the relevant channel before setting de to 1 in ch cr, or make the register settings with de cleared to 0 in chcr, then set de to 1. it does not matter whether setting of the dme bit to 1 in dmaor is carried out first or last. to operate the relevant channel, dme and de must both be set to 1. the dmac may not operate normally if the sar, dar, and dmatcr settings are not made (with the exception of the unused register in single address mode). 6. after the dmatcr count reaches 0 and dma tr ansfer ends normally, always write 0 to dmatcr even when executing the maximum number of transfers on the same channel.
SH7750, SH7750s, SH7750r group section 14 direct memory access controller (dmac) r01uh0456ej0702 rev. 7.02 page 653 of 1076 sep 24, 2013 7. when falling edge detection is used for external requests, keep the external request pin high when making dmac settings. 8. when using the dmac in single address mode , set an external addre ss as the address. all channels will halt due to an address error if an on-chip peripheral m odule address is set. 9. in external request ( dreq ) edge detection in the SH7750r, an external request that has been accepted can be cancelled in the following way. firstly, negate dreq and change the value of chcr.ds from 1 to 0. after that, set the chcr.ds bit back to 1, then assert dreq . (though the SH7750r does not have a dmaor.cod bit, similar to when the dmaor.cod bit is 1 in the SH7750s, external requests that have on ce been accepted can be cancelled when the external request ( dreq ) edge is detected.) 10. SH7750 only: when a dma transfer is performed between an on-chip peripheral module and external memory, the data may not be transferred correctly if the following conditions apply. to work around this problem, use the cpu to transfer the data. ? conditions under which problem occurs a. big endian is selected. b. the external memory bus width is 32 bits. c. data is being transferred from an on-chip peripheral module* 1 to external memory. d. the transmit size* 2 of the data to be transferred is 32 bits. conditions a. to d. must all be satisfied. ? description of problem when transferring data from an on-chip peripheral module, bits 15 to 8 of the 32-bit data become misaligned. as a result, the data is not transferred correctly. data that should be transferred: 12 34 56 78 data actually transferred to ex ternal memory: 12 34 12 78 notes: 1. the registers corresponding to the above conditions are the following. tmu.tcor0 tmu.tcnt0 tmu.tcor1 tmu.tcnt1 tmu.tcor2 tmu.tcnt2 tmu.tcpr2 h-udi.sddr 2. set by the transmit size bits in the dma channel control register.
section 14 direct memory access controller (dmac) SH7750, SH7750s, SH7750r group page 654 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 655 of 1076 sep 24, 2013 section 15 serial communication interface (sci) 15.1 overview this lsi is equipped with a single-channel serial communication interface (sci) and a single- channel serial communication in terface with built-in fifo regist ers (sci with fifo: scif). the sci can handle both asynchronous and synchronous serial communication. the sci supports a smart card interface. this is a serial communicati on function supporting a subset of the iso/iec 7816-3 (identification card s) standard. for details, see section 17, smart card interface. the scif is a dedicated asynchronous communicati on serial interface with built-in 16-s tage fifo registers for both transmission an d reception. for details, see s ection 16, serial communication interface with fifo (scif). 15.1.1 features sci features are listed below. ? choice of synchronous or asynchronous serial communication mode ? asynchronous mode serial data communication is executed us ing an asynchronous system in which synchronization is achieved character by ch aracter. serial data communication can be carried out with standard asynchronous co mmunication chips such as a universal asynchronous receiver/transm itter (uart) or asynchrono us communication interface adapter (acia). a multiprocessor communication function is also provided that enables serial data communication w ith a number of processors. there is a choice of 12 serial data transfer formats. data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even/odd/none multiprocessor bit: 1 or 0 receive error detection: parity , overrun, and framing errors break detection: a break can be detected by reading the rxd pin level directly from the serial port register (scsptr1) when a framing error occurs.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 656 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? synchronous mode serial data communication is synchronized with a clock. serial data communication can be carried out with other chips that have a synchronous communication function. there is a single serial data transfer format. data length: 8 bits receive error detecti on: overrun errors ? full-duplex communication capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected. ? choice of serial clock source: internal clock from baud rate generator or external clock from sck pin ? four interrupt sources there are four interrupt sour ces?transmit-data-empty, transm it-end, receive-data-full, and receive-error?that can issue re quests independently. the tran smit-data-empty interrupt and receive-data-full interrupt can ac tivate the dma controller (dmac) to execute a data transfer. ? when not in use, the sci can be stopped by halting its clock supply to reduce power consumption.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 657 of 1076 sep 24, 2013 15.1.2 block diagram figure 15.1 shows a block diagram of the sci. module data bus scrdr1 scrsr1 rxd txd sck sctdr1 sctsr1 scssr1 scscr1 scsmr1 scbrr1 parity generation parity check transmission/ reception control baud rate generator clock external clock pck pck/4 pck/16 pck/64 tei txi rxi eri sci bus interface internal data bus scsptr1 legend: scrsr1: receive shift register scrdr1: receive data register sctsr1: transmit shift register sctdr1: transmit data register scsmr1: serial mode register scscr1: serial control register scssr1: serial status register scbrr1: bit rate register scsptr1: serial port register figure 15.1 block diagram of sci
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 658 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 15.1.3 pin configuration table 15.1 shows the sci pin configuration. table 15.1 sci pins pin name abbreviation i/o function serial clock pin md0/ sck i/o clock input/output receive data pin rxd i nput receive data input transmit data pin md7/txd ou tput transmit data output note: the serial clock pin and transmit data pin function as mode input pins md0 and md7 after a power-on reset. they are made to function as serial pins by performing sci operation settings with the te, re, ckei, and cke0 bits in scscr1 and the c/ a bit in scsmr1. break state transmission and detection, can be set in the sci's scsptr1 register. 15.1.4 register configuration the sci has the internal registers shown in ta ble 15.2. these registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform transmitter/receiver control. with the exception of the serial port register, the sci registers ar e initialized in standby mode and in the module standby st ate as well as after a power-on reset or manual reset. when recovering from standby mode or the module standby state, the registers must be set again.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 659 of 1076 sep 24, 2013 table 15.2 sci registers name abbreviation r/w initial value p4 address area 7 address access size serial mode register scsmr1 r/w h'00 h'ffe00000 h'1fe00000 8 bit rate register scbrr1 r/w h'ff h'ffe00004 h'1fe00004 8 serial control register scs cr1 r/w h'00 h'ffe00008 h'1fe00008 8 transmit data register sctdr1 r/w h'ff h'ffe0000c h'1fe0000c 8 serial status register scssr1 r/(w) * 1 h'84 h'ffe00010 h'1fe00010 8 receive data register scrdr 1 r h'00 h'ffe00014 h'1fe00014 8 serial port register scsptr1 r/w h'00 * 2 h'ffe0001c h'1fe0001c 8 notes: 1. only 0 can be written, to clear flags. 2. the value of bits 2 and 0 is undefined. 15.2 register descriptions 15.2.1 receive shift register (scrsr1) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? scrsr1 is the register used to receive serial data. the sci sets serial data input fr om the rxd pin in scrsr1 in the order received, st arting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to scrdr1 automatically. scrsr1 cannot be directly read or written to by the cpu.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 660 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 15.2.2 receive data register (scrdr1) bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r scrdr1 is the register that stores received serial data. when the sci has received one byte of serial data , it transfers the received data from scrsr1 to scrdr1 where it is stored, and completes the r eceive operation. scrsr1 is then enabled for reception. since scrsr1 and scrdr1 function as a double buffer in this way, it is possible to receive data continuously. scrdr1 is a read-only register, and cannot be written to by the cpu. scrdr1 is initialized to h'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. 15.2.3 transmit shift register (sctsr1) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? sctsr1 is the register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from sctdr1 to sctsr1, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from sctdr1 to sctsr1, and transmission started, automati cally. however, data transfer from sctdr1 to sctsr1 is not performed if the tdre flag in the serial status register (scssr1) is set to 1. sctsr1 cannot be directly read or written to by the cpu.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 661 of 1076 sep 24, 2013 15.2.4 transmit data register (sctdr1) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w sctdr1 is an 8-bit register that st ores data for serial transmission. when the sci detects that sctsr1 is empty, it tr ansfers the transmit data written in sctdr1 to sctsr1 and starts serial transmission. continuo us serial transmission can be carried out by writing the next transmit data to sctdr1 during serial transmission of the data in sctsr1. sctdr1 can be read or written to by the cpu at all times. sctdr1 is initialized to h'ff by a power-on reset or manual reset, in standby mode, and in the module standby state. 15.2.5 erial mode register (scsmr1) bit: 7 6 5 4 3 2 1 0 c/ a chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scsmr1 is an 8-bit register used to set the sci's serial transfer format and select the baud rate generator clock source. scsmr1 can be read or written to by the cpu at all times. scsmr1 is initialized to h'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. bit 7?communication mode (c/ a ): selects asynchronous mode or synchronous mode as the sci operating mode. bit 7: c/ a description 0 asynchronous mode (initial value) 1 synchronous mode
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 662 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 6?character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in synchronous mode, a fixed data length of 8 bi ts is used regardless of the chr setting, bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (b it 7) of sctdr1 is not transmitted. bit 5?parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in synchronous mode, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5: pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in recepti on, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4?parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asyn chronous mode. the o/ e bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. bit 4: o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit additi on is performed in transmission so that the total number of 1-bits in the transmit character pl us the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bi ts in the receive character plus the parity bit is odd.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 663 of 1076 sep 24, 2013 bit 3?stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bit setting is only valid in asynchronous mode. if synchronous mode is set, the stop bit setting is invalid since stop bits are not added. bit 3: stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1-bit (stop bi t) is added to the end of a transmit character before it is sent. 2. in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the star t bit of the next transmit character. bit 2?multiprocessor mode (mp): selects a multiprocessor format. when a multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. for details of the multiprocessor communication fu nction including notes on use, see section 15.3.3, multiprocessor communication function. bit 2: mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. the clock source can be selected from pck, pck/4, pck/16, and pck/64, according to the setting of bits cks1 and cks0.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 664 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 for the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.9, bit rate register (scbrr1). bit 1: cks1 bit 0: cks0 description 0 0 pck clock (initial value) 1 pck/4 clock 1 0 pck/16 clock 1 pck/64 clock note: pck: peripheral clock 15.2.6 serial control register (scscr1) bit: 7 6 5 4 3 2 1 0 tie rie te re mpie teie cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the scscr1 register performs enabling or disabl ing of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scscr1 can be read or written to by the cpu at all times. scscr1 is initialized to h'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. bit 7?transmit interrupt enable (tie): enables or disables transmit-data-empty interrupt (txi) request generation when serial transmit data is transferred from sctdr1 to sctsr1 and the tdre flag in scssr1 is set to 1. bit 7: tie description 0 transmit-data-empty interrupt (txi) request disabled * (initial value) 1 transmit-data-empty interrupt (txi) request enabled note: * txi interrupt requests can be cleared by read ing 1 from the tdre flag, then clearing it to 0, or by clearing the tie bit to 0.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 665 of 1076 sep 24, 2013 bit 6?receive interrupt enable (rie): enables or disables receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request ge neration when serial recei ve data is transferred from scrsr1 to scrdr1 and the rdrf flag in scssr1 is set to 1. bit 6: rie description 0 receive-data-full interrupt (rxi) r equest and receive-error interrupt (eri) request disabled * (initial value) 1 receive-data-full interrupt (rxi) r equest and receive-error interrupt (eri) request enabled note: * rxi and eri interrupt requests can be cleare d by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the fl ag to 0, or by clearing the rie bit to 0. bit 5?transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5: te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in scssr1 is fixed at 1. 2. in this state, serial transmission is st arted when transmit data is written to sctdr1 and the tdre flag in scssr1 is cleared to 0. scsmr1 setting must be performed to decide the transmit format before setting the te bit to 1. bit 4?receive enable (re): enables or disables the start of serial reception by the sci. bit 4: re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not a ffect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this stat e when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. scsmr1 setting must be performed to decide the receive format before setting the re bit to 1.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 666 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 3?multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when the mp bit in scsmr1 is set to 1. the mpie bit setting is invalid in synchronous mode or when the mp bit is cleared to 0. bit 3: mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] ? when the mpie bit is cleared to 0 ? when data with mpb = 1 is received 1 multiprocessor interrupts enabled * note: * when receive data including mpb = 1 is received, the mpie bit is cleared to 0 automatically, and generation of rxi and eri in terrupts (when the tie and rie bits in scscr1 are set to 1) and fer and orer flag setting is enabled. bit 2?transmit-end inte rrupt enable (teie): enables or disables transmit-end interrupt (tei) request generation when there is no valid tr ansmit data in sctdr1 at the time for msb data transmission. bit 2: teie description 0 transmit-end interrupt (tei) request disabled * (initial value) 1 transmit-end interrupt (tei) request enabled * note: * tei interrupt requests can be cleared by reading 1 from the tdre flag in scssr1, then clearing it to 0 and clearing the tend flag to 0, or by clearing the teie bit to 0. bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as the serial clock output pin or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in synchronous mode and in the case of external clock operation (cke1 = 1). the cke1 and cke0 bits must be set before determining the sci's operating mode with scsmr1. for details of clock source selection, see table 15.9 in section 15.3, operation.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 667 of 1076 sep 24, 2013 bit 1: cke1 bit 0: cke0 description 0 0 asynchronous mode internal clock/sck pin functions as input pin (input signal ignored) * 1 synchronous mode internal clock/sck pin functions as serial clock output * 1 1 asynchronous mode internal clock/sck pin functions as clock output * 2 synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate. 15.2.7 serial status re gister (scssr1) bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer per tend mpb mpbt initial value: 1 0 0 0 0 1 ? 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only 0 can be written, to clear the flag. scssr1 is an 8-bit register containing status flag s that indicate the operat ing status of the sci, and multiprocessor bits. scssr1 can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. scssr1 is initialized to h'84 by a power-on reset or manual reset, in standby mode, and in the module standby state.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 668 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 7?transmit data register empty (tdre): indicates that data has been transferred from sctdr1 to sctsr1 and the next serial transmit data can be written to sctdr1. bit 7: tdre description 0 valid transmit data has been written to sctdr1 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when data is written to sctdr1 by the dmac 1 there is no valid transmit data in sctdr1 (initial value) [setting conditions] ? power-on reset, manual reset, standby mode, or module standby ? when the te bit in scscr1 is 0 ? when data is transferred from sctdr1 to sctsr1 and data can be written to sctdr1 bit 6?receive data register full (rdrf): indicates that the received data has been stored in scrdr1. bit 6: rdrf description 0 there is no valid receive data in scrdr1 (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to rdrf after reading rdrf = 1 ? when data in scrdr1 is read by the dmac 1 there is valid receive data in scrdr1 [setting condition] when serial reception ends normally and receive data is transferred from scrsr1 to scrdr1 note: scrdr1 and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scscr1 is cleared to 0. if reception of the next data is completed whil e the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 669 of 1076 sep 24, 2013 bit 5?overrun error (orer): indicates that an overrun erro r occurred during reception, causing abnormal termination. bit 5: orer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to orer after reading orer = 1 1 an overrun error occurred during reception * 2 [setting condition] when the next serial reception is completed while rdrf = 1 notes: 1. the orer flag is not affected and re tains its previous state when the re bit in scscr1 is cleared to 0. 2. the receive data prior to the overrun error is retained in scrdr1, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission cannot be continued either. bit 4?framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4: fer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to fer after reading fer = 1 1 a framing error occurred during reception [setting condition] when the sci checks whether the stop bi t at the end of the receive data is 1 when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scscr1 is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to scrdr1 but the rdrf flag is not set. serial reception cannot be continued while the fer flag is set to 1.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 670 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 3?parity error (per): indicates that a parity error occu rred during reception with parity addition in asynchronous mode, causing abnormal termination. bit 3: per description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to per after reading per = 1 1 a parity error occurred during reception * 2 [setting condition] when, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in scsmr1 notes: 1. the per flag is not affected and retains its previous state when the re bit in scscr1 is cleared to 0. 2. if a parity error occurs, the receive data is transferred to scrdr1 but the rdrf flag is not set. serial reception cannot be continued while the per flag is set to 1. bit 2?transmit end (tend): indicates that there is no valid data in sctdr1 when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified. bit 2: tend description 0 transmission is in progress [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when data is written to sctdr1 by the dmac 1 transmission has been ended (initial value) [setting conditions] ? power-on reset, manual reset, standby mode, or module standby ? when the te bit in scscr1 is 0 ? when tdre = 1 on transmission of t he last bit of a 1-byte serial transmit character bit 1?multiprocessor bit (mpb)*: this bit is read-only and cannot be written to. the read value is undefined.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 671 of 1076 sep 24, 2013 note: * this bit is prepared for storing a multi-processor bit in the received data when the receipt is carried out with a multi-processo r format in asynchronous mode. this bit does not function correctly in this lsi. however, do not use the read value from this bit. bit 0?multiprocessor bit transfer (mpbt): when transmission is performed using a multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid in synchronous mode, when a multiprocessor format is not used, and when the operation is not transmission. unlike transmit data, the mpbt bit is not double-b uffered, so it is necessary to check whether transmission has been completed before changing its value. bit 0: mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted 15.2.8 serial port register (scsptr1) bit: 7 6 5 4 3 2 1 0 eio ? ? ? spb1io spb1dt spb0io spb0dt initial value: 0 0 0 0 0 ? 0 ? r/w: r/w ? ? ? r/w r/w r/w r/w scsptr1 is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (sci) pins. input data can be read from the rxd pin, output data written to the txd pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. sck pin data reading and output data writing can be performed by means of bits 3 and 2. bit 7 controls enabling and disabling of the rxi interrupt. scsptr1 can be read or written to by the cpu at all times. all scsptr1 bits except bits 2 and 0 are initialized to h'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. scsptr1 is not initialized in the module standby state or standby mode. bit 7?error interrupt only (eio): when the eio bit is 1, an rxi interrupt request is not sent to the cpu even if the rie bit is set to 1. when the dmac is used, this setting means that only eri interrupts are handled by the cpu. the dmac transfers read data to memory or another peripheral module. this bit specifies enabling or disabling of the rxi interrupt.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 672 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 7: eio description 0 when the rie bit is 1, rxi and eri interrupts are sent to intc (initial value) 1 when the rie bit is 1, only eri interrupts are sent to intc bits 6 to 4?reserved: these bits are always read as 0, and should only be written with 0. bit 3?serial port clock port i/o (spb1io): specifies serial port sck pin input/output. when the sck pin is actually set as a port output pin and outputs the value set by the spb1dt bit, the c/ a bit in scsmr1 and the cke1 and cke0 bi ts in scscr1 should be cleared to 0. bit 3: spb1io description 0 spb1dt bit value is not output to the sck pin (initial value) 1 spb1dt bit value is output to the sck pin bit 2?serial port cloc k port data (spb1dt): specifies the serial port sck pin input/output data. input or output is specified by the spb1io bit (see the description of bit 3, spb1io, for details). when output is specified, the value of the spb1dt bit is output to the sck pin. the sck pin value is read from the spb1dt bit regardless of the value of the spb1io bit. the initial value of this bit after a power-on or manual reset is undefined. bit 2: spb1dt description 0 input/output data is low-level 1 input/output data is high-level bit 1?serial port break i/o (spb0io): specifies the serial port txd pin output condition. when the txd pin is actually set as a port output pin and outputs the value set by the spb0dt bit, the te bit in scscr1 should be cleared to 0. bit 1: spb0io description 0 spb0dt bit value is not output to the txd pin (initial value) 1 spb0dt bit value is output to the txd pin bit 0?serial port break data (spb0dt): specifies the serial port rxd pin input data and txd pin output data. the txd pin output condition is specified by the spb0io bit (see the description of bit 1, spb0io, for details). when the txd pin is designated as an output, the value of the spb0dt bit is output to the txd pin. the rxd pin value is read from the spb0dt bit regardless of the value of the spb0io bit. the initial value of this bit after a power-on or manual reset is undefined.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 673 of 1076 sep 24, 2013 bit 0: spb0dt description 0 input/output data is low-level 1 input/output data is high-level sci i/o port block diagrams are shown in figures 15.2 to 15.4.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 674 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 reset reset internal data bus sptrw sptrw sci r q d spb1io c r q d spb1dt c sptrr clock output enable si g nal serial clock output si g nal serial clock input si g nal clock input enable si g nal * md0/sck mode settin g re g ister le g end: sptrw: write to sptr sptrr: read sptr note: * si g nals that set the sck pin function as internal clock output or external clock input accordin g to the cke0 and cke1 bits in scscr1 and the c/ a bit in scsmr1. figure 15.2 md0/sck pin
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 675 of 1076 sep 24, 2013 reset internal data bus sptrw sci r q d spb0io c reset sptrw r q d spb0dt c md7/txd mode settin g re g ister transmit enable si g nal serial transmit data le g end: sptrw: write to sptr figure 15.3 md7/txd pin internal data bus sci rxd sptrr serial receive data le g end: sptrr: read sptr figure 15.4 rxd pin
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 676 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 15.2.9 bit rate register (scbrr1) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scbrr1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr1. scbrr1 can be read or written to by the cpu at all times. scbrr1 is initialized to h'ff by a power-on reset or manual reset, in standby mode, and in the module standby state. the scbrr1 setting is found from the following equations. asynchronous mode: n = 10 6 ? 1 64 2 2n ? 1 b pck synchronous mode: n = 10 6 ? 1 8 2 2n ? 1 b pck where b: bit rate (bits/s) n: scbrr1 setting for baud rate generator (0 n 255) pck: peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr1 setting n clock cks1 cks0 0 pck 0 0 1 pck/4 0 1 2 pck/16 1 0 3 pck/64 1 1
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 677 of 1076 sep 24, 2013 the bit rate error in asynchronous mode is found from the following equation: error ( % ) = 100 pck 10 6 (n + 1) b 64 2 2n ? 1 ? 1 table 15.3 shows sample scbrr1 settings in asynchronous mode, and table 15.4 shows sample scbrr1 settings in synchronous mode. table 15.3 examples of bi t rates and scbrr1 settings in asynchronous mode pck (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 0 19 ?2.34 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 0 9 ?2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 ?2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 ?18.62 0 1 ?14.67 0 1 0.00
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 678 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 pck (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 ?6.99 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 pck (mhz) 6 6.144 7.37288 8 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 0 6 ?6.99
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 679 of 1076 sep 24, 2013 pck (mhz) 9.8304 10 12 12.288 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00 pck (mhz) 14.7456 16 19.6608 20 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 ?0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 31250 0 14 ?1.70 0 15 0.00 0 19 ?1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 680 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 pck (mhz) 24 24.576 28.7 30 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 106 ?0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 ?0.35 300 2 155 0.16 2 159 0.00 2 186 ?0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 ?0.35 1200 1 155 0.16 1 159 0.00 1 186 ?0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 ?0.35 4800 0 155 0.16 0 159 0.00 0 186 ?0.08 0 194 ?1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 ?0.35 19200 0 38 0.16 0 39 0.00 0 46 ?0.61 0 48 ?0.35 31250 0 23 0.00 0 24 ?1.70 0 28 ?1.03 0 29 0.00 38400 0 19 ?2.34 0 19 0.00 0 22 1.55 0 23 1.73 legend: blank: no setting is available. ?: a setting is available but error occurs.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 681 of 1076 sep 24, 2013 table 15.4 examples of bit rates and scbrr1 settings in synchronous mode pck (mhz) 4 8 16 28.7 30 bit rate (bits/s) n n n n n n n n n n 10 ? ? ? ? ? ? ? ? ? ? 250 2 249 3 124 3 249 ? ? ? ? 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 ? ? 0 29 500k 0 1 0 3 0 7 ? ? 0 14 1m 0 0 * 0 1 0 3 ? ? ? ? 2m 0 0 * 0 1 ? ? ? ? legend: blank: no setting is available. ?: a setting is available but error occurs. * continuous transmission/reception is not possible. note: as far as possible, the setting shoul d be made so that the error is within 1 % .
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 682 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. tables 15.6 and 15.7 show the maximum bit rates with external clock input. table 15.5 maximum bit rate for various frequencies with baud rate generator (asynchronous mode) settings pck (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 683 of 1076 sep 24, 2013 table 15.6 maximum bit rate with external clock input (asynchronous mode) pck (mhz) external input clock (mh z) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 table 15.7 maximum bit rate with ext ernal clock input (synchronous mode) pck (mhz) external input clock (mh z) maximum bit rate (bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 684 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 15.3 operation 15.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or synchronous mode and the transmission format is made using scsmr1 as shown in table 15.8. the sci clock so urce is determined by a combination of the c/ a bit in scsmr1 and the cke1 and cke0 bits in scscr1, as shown in table 15.9. ? asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addi tion, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing, parity, and overru n errors, and breaks, during reception ? choice of internal or external clock as sci clock source when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output. when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). ? synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip. when external clock is selected: the on-chip baud rate generator is not used, and the sci operates on the input serial clock.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 685 of 1076 sep 24, 2013 table 15.8 scsmr1 settings for serial transfer format selection scsmr1 settings sci transfer format bit 7: c/ a bit 6: chr bit 2: mp bit 5: pe bit 3: stop mode data length multi- processor bit parity bit stop bit length 0 0 0 0 0 8-bit data no no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 asynchronous mode 2 bits 0 1 * 0 8-bit data yes no 1 bit 1 2 bits 1 0 7-bit data 1 bit 1 asynchronous mode (multiprocessor format) 2 bits 1 * * * * synchronous mode 8-bit data no none note: an asterisk in the table means ?don't care.?
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 686 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 15.9 scsmr1 and scscr1 settings for sci clock source selection scsmr1 scscr1 setting sci transmit/receive clock bit 7: c/ a bit 1: cke1 bit 0: cke0 mode clock source sck pin function 0 0 0 internal sci does not use sck pin 1 outputs clock with same frequency as bit rate 1 0 external inputs clock with frequency of 16 times the bit rate 1 asynchronous mode 1 0 0 internal outputs serial clock 1 1 0 synchronous mode external inputs serial clock 1 15.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or r eceived, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by- character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receive r also have a double-buffered structure, so that data can be read or written during transm ission or reception, enabling continuous data transfer. figure 15.5 shows the general format for asynchronous serial communication. in asynchronous serial co mmunication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, an d when it goes to the space state (low level), recognizes a start bit and st arts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the eighth pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 687 of 1076 sep 24, 2013 serial data (lsb) 7 or 8 bits one unit of transfer data (character or frame) parity bit 1 bit, or none 1 or 2 bits stop bit(s) 1 1 0 d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 idle state (mark state) start bit 1 bit (msb) transmit/receive data figure 15.5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) data transfer format table 15.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the scsmr1 setting.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 688 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 15.10 serial transfer formats (asynchronous mode) scsmr1 settings serial transfer format and frame length chr pe mp stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 s 8-bit data stop 0 0 0 1 s 8-bit data stop stop 0 1 0 0 s 8-bit data p stop 0 1 0 1 s 8-bit data p stop stop 1 0 0 0 s 7-bit data stop 1 0 0 1 s 7-bit data stop stop 1 1 0 0 s 7-bit data p stop 1 1 0 1 s 7-bit data p stop stop 0 * 1 0 s 8-bit data mpb stop 0 * 1 1 s 8-bit data mpb stop stop 1 * 1 0 s 7-bit data mpb stop 1 * 1 1 s 7-bit data mpb stop stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit note: an asterisk in the table means ?don't care.?
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 689 of 1076 sep 24, 2013 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci's seri al clock, according to the setting of the c/ a bit in scsmr1 and the cke1 and cke0 bits in scscr1. for details of sci clock source selection, see table 15.9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6. d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 one frame 0 figure 15.6 relation between outp ut clock and transfer data phase (asynchronous mode) data transfer operations sci initialization (asynchronous mode): before transmitting and receiving data, it is necessary to clear the te and re bits in scscr1 to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and sctsr1 is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, pe r, fer, and orer flags, or the contents of scrdr1. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. figure 15.7 shows a sample sci initialization flowchart.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 690 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 initialization clear te and re bits in scscr1 to 0 set cke1 and cke0 bits in scscr1 (leavin g te and re bits cleared to 0) set transmit/receive format in scsmr1 set value in scbrr1 1-bit interval elapsed? set te and re bits in scscr1 to 1, and set rie, tie, teie, and mpie bits end yes wait no 1. set the clock selection in scscr1. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when clock output is selected in asynchronous mode, it is output immediately after scscr1 settin g s are made. 2. set the transmit/receive format in scsmr1. 3. write a value correspondin g to the bit rate into scbrr1. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr1 to 1. also set the rie, tie, teie, and mpie bits. settin g the te and re bits enables the txd and rxd pins to be used. when transmittin g , the sci will g o to the mark state; when receivin g , it will g o to the idle state, waitin g for a start bit. figure 15.7 sample sci initialization flowchart serial data transmission (asynchronous mode): figure 15.8 shows a sample flowchart for serial transmission. use the following procedure for serial data transm ission after enabling the sci for transmission.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 691 of 1076 sep 24, 2013 start of transmission read tdre fla g in scssr1 tdre = 1? all data transmitted? tend = 1? break output? clear te bit in scscr1 to 0 end of transmission yes no yes no yes no yes no write transmit data to sctdr1 and clear tdre fla g in scssr1 to 0 read tend fla g in scssr1 clear spb0dt to 0 and set spb0io to 1 1. sci status check and transmit data write: read scssr1 and check that the tdre fla g is set to 1, then write transmit data to sctdr1 and clear the tdre fla g to 0. 2. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre fla g to confirm that writin g is possible, then write data to sctdr1, and then clear the tdre fla g to 0. (checkin g and clearin g of the tdre fla g is automatic when the direct memory access controller (dmac) is activated by a transmit-data-empty interrupt (txi) request, and data is written to sctdr1.) 3. break output at the end of serial transmission: to output a break in serial transmission, clear the spb0dt bit to 0 and set the spb0io bit to 1 in scsptr, then clear the te bit in scscr1 to 0. figure 15.8 sample serial transmission flowchart
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 692 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in scssr1. wh en tdre is cleared to 0, the sci recognizes that data has been written to sctdr1, and transfers the data from sctdr1 to sctsr1. 2. after transferring data from sctdr1 to scts r1, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit-data-empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit or multiprocessor bit: one parity b it (even or odd parity), or one multiprocessor bit is output. (a format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from sctdr1 to sctsr1, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in sc ssr1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is outp ut continuously. if the teie bit in scscr1 is set to 1 at this time, a tei in terrupt request is generated. figure 15.9 shows an example of the operation for transmission in asynchronous mode.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 693 of 1076 sep 24, 2013 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 tdre tend serial data start bit data parity bit stop bit start bit idle state (mark state) data parity bit stop bit txi interrupt request data written to sctdr1 and tdre fla g cleared to 0 by txi interrupt handler one frame tei interrupt request txi interrupt request figure 15.9 example of transmit operation in asynchronous mode (example with 8-bit data, parity, one stop bit) serial data reception (asynchronous mode): figure 15.10 shows a sample flowchart for serial reception. use the following procedure for serial data r eception after enabling th e sci for reception.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 694 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 start of reception read orer, per, and fer fla g s in scssr1 read rdrf fla g in scssr1 per or fer or orer = 1? rdrf = 1? all data received? clear re bit in scscr1 to 0 end of reception error handlin g yes no yes no yes no read receive data in scrdr1, and clear rdrf fla g in scssr1 to 0 1. receive error handlin g and break detection: if a receive error occurs, read the orer, per, and fer fla g s in scssr1 to identify the error. after performin g the appropriate error handlin g , ensure that the orer, per, and fer fla g s are all cleared to 0. reception cannot be resumed if any of these fla g s are set to 1. in the case of a framin g error, a break can be detected by readin g the value of the rxd pin. 2. sci status check and receive data read : read scssr1 and check that rdrf = 1, then read the receive data in scrdr1 and clear the rdrf fla g to 0. 3. serial reception continuation procedure: to continue serial reception, complete zero- clearin g of the rdrf fla g before the stop bit for the current frame is received. (the rdrf fla g is cleared automatically when the direct memory access controller (dmac) is activated by an rxi interrupt and the scrdr1 value is read.) figure 15.10 sample serial reception flowchart (1)
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 695 of 1076 sep 24, 2013 error handlin g orer = 1? fer = 1? break? per = 1? end yes yes no yes no no no yes clear orer, per, and fer fla g s in scssr1 to 0 parity error handlin g framin g error handlin g clear re bit in scscr1 to 0 overrun error handlin g figure 15.10 sample serial reception flowchart (2)
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 696 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 in serial reception, the sci operates as described below. 1. the sci monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr1 in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the sci carries out the fo llowing checks. a. parity check: the sci checks whether the numbe r of 1-bits in the recei ve data agrees with the parity (even or odd) set in the o/ e bit in scsmr1. b. stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. c. status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from scrsr1 to scrdr1. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in scrdr1. if a receive error is detected in the error chec k, the operation is as shown in table 15.11. note: no further receive operations can be pe rformed when a receive error has occurred. also note that the rdrf flag is not set to 1 in rece ption, and so the error flags must be cleared to 0. 4. if the eio bit in scsptr1 is cleared to 0 an d the rie bit in scscr1 is set to 1 when the rdrf flag changes to 1, a receive-data-full interrupt (rxi) request is generated. if the rie bit in scscr1 is set to 1 when the orer, per, or fer flag changes to 1, a receive-error interrupt (eri) request is generate d. a receive-data-full re quest is always output to the dmac when the rdrf flag changes to 1. table 15.11 receive error conditions receive error abbreviation condition data transfer overrun error orer reception of next data is completed while rdrf flag in scssr1 is set to 1 receive data is not transferred from scrsr1 to scrdr1 framing error fer stop bit is 0 receive data is transferred from scrsr1 to scrdr1 parity error per received data parity differs from that (even or odd) set in scsmr1 receive data is transferred from scrsr1 to scrdr1
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 697 of 1076 sep 24, 2013 figure 15.11 shows an example of the operation for reception in asynchronous mode. 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0/1 0 rdrf fer serial data start bit data parity bit stop bit start bit data parity bit stop bit rxi interrupt request one frame scrdr1 data read and rdrf fla g cleared to 0 by rxi interrupt handler eri interrupt request g enerated by framin g error figure 15.11 example of sci receive operation (example with 8-bit data, parity, one stop bit)
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 698 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 15.3.3 multiprocessor communi cation function the multiprocessor communication function pe rforms serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing a serial tr ansmission line. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two cy cles: an id transmission cycle which specifies the receiving station , and a data transmission cycl e. the multiproces sor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the r eceiving station with whic h it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips th e data until data with a 1 multiprocessor bit is sent*. when data with a 1 multiprocessor bi t is received, the receiving statio n compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received*. in this way, data communication is carried out among a number of processors. figure 15.12 shows an example of inter-proce ssor communication using a multiprocessor format. note: * with this lsi, the rdrf flag in sc ssr1 is also set to 1 when data with a 0 multiprocessor b it transmitted to another station is r eceived. when the rdrf flag in scssr1 is set to 1, check the state of th e mpie bit in scscr1 with the exception handling routine, and if the mpie bit is 1, skip the data. that is to say, data skipping is implemented in cooperation with the exception handling routine.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 699 of 1076 sep 24, 2013 transmittin g station receivin g station a receivin g station b receivin g station c receivin g station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line (mpb = 1) (mpb = 0) h'01 h'aa le g end: mpb: multiprocessor bit serial data id transmission cycle: receivin g station specification data transmission cycle: data transmission to receivin g station specified by id figure 15.12 example of in ter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) data transfer formats there are four data transfer formats. when the multiprocesso r format is specified, the parity bit specification is invalid. for details, see table 15.10. clock see the description under clock in section 15.3.2, operation in asynchronous mode. data transfer operations multiprocessor serial data transmission: figure 15.13 shows a sample flowchart for multiprocessor serial data transmission. use the following procedure for multiprocessor serial data transmission after enabling the sci for transmission.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 700 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 start of transmission read tend flag in scssr1 tend = 1 ? clear tdre flag to 0 read tend flag in scssr1 tend = 1 ? clear mpbt bit in scssr1 to 0 write data to sctdr1 clear tdre flag to 0 read tdre flag in scssr1 end of transmission no yes no yes all data transmitted ? tdre = 1 ? yes yes no no set mpbt bit in scssr1 to 1 and write id data to sctdr1 1. sci status check and id data write: read scssr1 and check that the tend flag is set to 1, then set the mpbt bit in scssr1 to 1 and write id data to sctdr1. finally, clear the tdre flag to 0. 2. preparation for data transfer: read scssr1 and check that the tend flag is set to 1, then set the mpbt bit in scssr1 to 1. 3. serial data transmission: write the first transmit data to sctdr1, then clear the tdre flag to 0. to continue data transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to sctdr1, and then clear the tdre flag to 0. (checking and clearing of the tdre flag is automatic when the direct memory access controller (dmac) is activated by a transmit-data-empty interrupt (txi) request, and data is written to sctdr1.) figure 15.13 sample multiprocessor serial tr ansmission flowchart
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 701 of 1076 sep 24, 2013 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in scssr1. wh en tdre is cleared to 0, the sci recognizes that data has been written to sctdr1, and transfers the data from sctdr1 to sctsr1. 2. after transferring data from sctdr1 to sctsr1, the sci sets the tdre flag to 1 and starts transmission. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is set to 1, the tend flag in scssr1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. if the teie bit in sc scr1 is set to 1 at this time, a transmit-end interrupt (tei) request is generated. 4. the sci monitors the tdre flag. when tdre is cleared to 0, the sci recognizes that data has been written to sctdr1, and transfer s the data from sctdr1 to sctsr1. 5. after transferring data from sctdr1 to sctsr1, the sci sets the tdre flag to 1 and starts transmitting. if the transmit-data-em pty interrupt enable bit (tie bit) in scscr1 is set to 1 at this time, a transmit-data-empty interrupt (txi) request is generated. the order of transmission is the same as in step 2. figure 15.14 shows an example of sci operation for transmission using a multiprocessor format.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 702 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 serial data mpbt bit cleared to 0, data written to sctdr1, and tdre flag cleared to 0 by tei interrupt handler data written to sctdr1 and tdre flag cleared to 0 by txi interrupt handler txi interrupt request tei interrupt request 1 1 0d0d1 d7 0 0 0 d0 d1 d7 0 d0 d1 d7 11 1 multi- proces- sor bit multi- proces- sor bit multi- proces- sor bit stop bit start bit stop bit stop bit start bit data data data start bit tdre tend one frame idle state (mark state) figure 15.14 example of sci transmit operation (example with 8-bit data, multiprocessor bit, one stop bit) multiprocessor serial data reception: figure 15.15 shows a sample flowchart for multiprocessor seri al reception. use the following procedure for mu ltiprocessor serial data recepti on after enabling the sci for reception. 1. method for determining wh ether an interrupt generated during receive operation is a multiprocessor interrupt when an interrupt such as rxi occurs du ring receive operation using the on-chip sci multiprocessor communication function, check the state of the mpie bit in the scscr1 register as part of the interrupt handling routine. a. if the mpie bit in the scscr1 register is set to 1 ignore the received data. data with the multiprocessor bit (mpb) set to 0 and intended for another station was received, and the rdrf bit in the scscr1 re gister was set to 1. therefore, clear the rdrf bit in the scscr1 register to 0.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 703 of 1076 sep 24, 2013 b. if the mpie bit in the scsc r1 register is cleared to 0 a multiprocessor interrupt indicating that data (id) with the multiprocessor bit (mpb) set to 1 was received, or a receive data full in terrupt (rxi) occurred when data with the multiprocessor bit (mpb) se t to 0 and intended for this station was received. 2. method for determining whethe r received data is id or data do not use the mpb bit in the scssr1 register for software processing. when using software processing to determine wh ether received data is id (mpb = 1) or data (mpb = 0), use a procedur e such as saving a user-defined fl ag in memory to indicate receive start.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 704 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 start of reception set mpie bit to 1 no no no no no no no yes yes yes yes yes yes yes rxi = 1? user-defined receive start flag = 1? read orer and fer flags in scssr1 fer or orer = 1? read rdrf flag in scssr1 mpie = 0? this station's id? set user-defined receive start flag to 1 end of id reception handling read receive data in scrdr1 fer or orer = 1? end of data reception error handling rte clear user-defined receive start flag to 0 all data received? read orer and fer flags in scssr1 set rdrf = 0 and mpie = 1 read receive data in scrdr1 figure 15.15 sample multiprocessor serial reception flowchart (1)
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 705 of 1076 sep 24, 2013 orer = 1? fer = 1? error handling overrun error handling break? framing error handling clear re bit in scscr1 to 0 clear orer and fer flags in scssr1 to 0 end yes no no yes yes no figure 15.15 sample multiprocessor serial reception flowchart (2)
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 706 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 15.16 shows an exampl e of sci operation for multi processor form at reception. 1 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 mpb mpie rdrf id1 id2 data2 1 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 mpb mpb mpie rdrf scrdr1 value id1 serial data start bit data (id1) stop bit start bit idle state (mark state) data (data1) stop bit (b) data matches station's id rxi interrupt request (multiprocessor interrupt) mpie = 0 scrdr1 data read and rdrf flag cleared to 0 by rxi interrupt handler as data is not this station's id, mpie bit is set to 1 again rxi interrupt request mpie = 1 the rdrf flag is cleared to 0 by the rxi interrupt handler. mpb serial data start bit data (id2) stop bit start bit data (data2) stop bit idle state (mark state) (a) data does not match station's id scrdr1 value rxi interrupt request (multiprocessor interrupt) mpie = 0 scrdr1 data read and rdrf flag cleared to 0 by rxi interrupt handler as data matches this station's id, reception continues and data is received by rxi interrupt handler mpie bit set to 1 again figure 15.16 example of sci receive operation (example with 8-bit data, multiprocessor bit, one stop bit)
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 707 of 1076 sep 24, 2013 in multiprocessor mode serial reception, the sci operates as described below. 1. the sci monitors the transmission line, and if a 0 start bit is det ected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr1 in lsb-to-msb order. 3. if the mpie bit is 1, mpie is cleared to 0 when a 1 is received in the multiprocessor bit position. if the multiprocessor bit is 0, the mpie bit is not changed. 4. if the mpie bit is 0, rdrf is checked at the stop bit position, and if rdrf is 1 the overrun error bit is set. if the stop bit is not 0, the framing error bit is set. if rdrf is 0, the value in scrsr1 is transferred to scrdr1, and if the stop bit is 0, rdrf is set to 1. 15.3.4 operation in synchronous mode in synchronous mode, data is tran smitted or received in synchroni zation with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receive r also have a double-buffered structure, so that data can be read or written during tran smission or reception, enabling continuous data transfer. figure 15.17 shows the general format for synchronous serial communication. one unit of transfer data (character or frame) note: * high except in continuous transmission/reception serial clock serial data lsb bit 0 msb * * bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 don't care don't care figure 15.17 data format in synchronous communication in synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data confirmation is guaranteed at the rising edge of the serial clock.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 708 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 in serial communication, one charact er consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in synchronous mode, the sci receives data in sync hronization with the falling edge of the serial clock. data transfer format a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck pin can be selected , according to the setting of the c/ a bit in scsmr1 and the cke1 and cke0 bits in scscr1. for details of sci clock source selection, see table 15.9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transf er of one character, and when no transfer is performed the clock is fixed high. in reception only, if an on-chi p clock source is selected, clock pulses are output while re = 1. wh en the last data is received, re should be cleared to 0 before the end of bit 7. data transfer operations sci initialization (synchronous mode): before transmitting and receiving data, it is necessary to clear the te and re bits in scscr1 to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and sctsr1 is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, pe r, fer, and orer flags, or the contents of scrdr1.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 709 of 1076 sep 24, 2013 figure 15.18 shows a sample sci initialization flowchart. set transmit/receive format in scsmr1 1-bit interval elapsed? end no wait yes set te and re bits in scscr1 to 1, and set rie, tie, teie, and mpie bits set value in scbrr1 set rie, tie, teie, mpie, cke1, and cke0 bits in scscr1 (leaving te and re bits cleared to 0) clear te and re bits in scscr1 to 0 initialization 1. set the clock selection in scscr1. be sure to clear bits rie, tie, teie, and mpie, te and re, to 0. 2. set transmit/receive format in scsmr1. 3. write a value corresponding to the bit rate into scbrr1. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr1 to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. figure 15.18 sample sci initialization flowchart
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 710 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 serial data transmission (synchronous mode): figure 15.19 shows a sample flowchart for serial transmission. use the following procedure for serial data transm ission after enabling the sci for transmission. start of transmission read tdre flag in scssr1 tdre = 1? all data transmitted? read tend flag in scssr1 clear te bit in scscr1 to 0 end tend = 1? no yes no yes yes no write transmit data to sctdr1 and clear tdre flag in scssr1 to 0 1. sci status check and transmit data write: read scssr1 and check that the tdre flag is set to 1, then write transmit data to sctdr1 and clear the tdre flag to 0. 2. to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to sctdr1, and then clear the tdre flag to 0. (checking and clearing of the tdre flag is automatic when the direct memory access controller (dmac) is activated by a transmit-data-empty interrupt (txi) request, and data is written to sctdr1.) figure 15.19 sample serial transmission flowchart
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 711 of 1076 sep 24, 2013 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in scssr1. wh en tdre is cleared to 0, the sci recognizes that data has been written to sctdr1, and transfers the data from sctdr1 to sctsr1. 2. after transferring data from sctdr1 to sctsr1, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at th is time, a transmit-data-empty interrupt (txi) request is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). 3. the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is tr ansferred from sctdr1 to sctsr1, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in sc ssr1 is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scscr1 is set to 1 at this time, a transmit-end interrupt (tei) request is generated. 4. after completion of serial transmission, the sck pin is fixed high. figure 15.20 shows an example of sci operation in transmission.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 712 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 lsb msb tdre tend bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 serial clock serial data transfer direction txi interrupt request data written to sctdr1 and tdre flag cleared to 0 in txi interrupt handler tei interrupt request one frame txi interrupt request figure 15.20 example of sci transmit operation
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 713 of 1076 sep 24, 2013 serial data reception (synchronous mode): figure 15.21 shows a sample flowchart for serial reception. use the following procedure for serial data r eception after enab ling the sci for reception. when changing the operating mode from asynchronous to synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. th e rdrf flag will not be set if the fer or per flag is set to 1, and ne ither transmit nor receive operations will be possible. start of reception read orer flag in scssr1 orer = 1? read rdrf flag in scssr1 rdrf = 1? read receive data in scrdr1, and clear rdrf flag in scssr1 to 0 all data received? clear re bit in scscr1 to 0 end of reception yes no yes yes no no error handling 1. receive error handling: if a receive error occurs, read the orer flag in scssr1 , and after performing the appropriate error handling, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. 2. sci status check and receive data read: read scssr1 and check that the rdrf flag is set to 1, then read the receive data in scrdr1 and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. 3. serial reception continuation procedure: to continue serial reception, finish reading the rdrf flag, reading scrdr1, and clearing the rdrf flag to 0, before the msb (bit 7) of the current frame is received. (the rdrf flag is cleared automatically when the direct memory access controller (dmac) is activated by a receive-data-full interrupt (rxi) request and the scrdr1 value is read.) figure 15.21 sample serial reception flowchart (1)
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 714 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 error handling overrun error handling clear orer flag in scssr1 to 0 orer = 1? end yes no figure 15.21 sample serial reception flowchart (2) in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with serial clock input or output. 2. the received data is stored in scrsr1 in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0, in dicating that the receive data can be transferred from scrsr1 to scrdr1. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in scrdr1. if a receive error is detected in the error check, the operation is as shown in table 15.11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. also, as the rdrf flag is not set to 1 when receiving, the flag mu st be cleared to 0. 3. if the rie bit in scrsr1 is set to 1 when the rdrf flag ch anges to 1, a receive-data-full interrupt (rxi) request is generated. if the rie bit in scrsr1 is set to 1 when the orer flag changes to 1, a receive-error interr upt (eri) request is generated.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 715 of 1076 sep 24, 2013 figure 15.22 shows an example of sci operation in reception. rdrf orer transfer direction serial clock serial data bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request data read from scrdr1 and rdrf flag cleared to 0 in rxi interrupt handler one frame rxi interrupt request eri interrupt request due to overrun error figure 15.22 example of sci receive operation simultaneous serial data transmission and reception (syn chronous mode): figure 15.23 shows a sample flowchart for simultaneous serial transmit and receive operations. use the following procedure for simultaneous seri al data transmit and receive operations after enabling the sci for tran smission and reception.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 716 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 read tdre flag in scssr1 tdre = 1? write transmit data to sctdr1 and clear tdre flag in scssr1 to 0 read orer flag in scssr1 orer = 1? error handling read rdrf flag in scssr1 rdrf = 1? read receive data in scrdr1, and clear rdrf flag in scssr1 to 0 all data transferred? clear te and re bits in scrsr1 to 0 end of transmission/reception start of transmission/reception no yes yes no no yes yes no 1. sci status check and transmit data write: read scssr1 and check that the tdre flag is set to 1, then write transmit data to sctdr1 and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. 2. receive error handling: if a receive error occurs, read the orer flag in scssr1 , and after performing the appropriate error handling, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. 3. sci status check and receive data read: read scssr1 and check that the rdrf flag is set to 1, then read the receive data in scrdr1 and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. 4. serial transmission/reception continuation procedure: to continue serial transmission/ reception, finish reading the rdrf flag, reading scrdr1, and clearing the rdrf flag to 0, before the msb (bit 7) of the current frame is received. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible, then write data to sctdr1 and clear the tdre flag to 0. (checking and clearing of the tdre flag is automatic when the dmac is activated by a transmit-data-empty interrupt (txi) request, and data is written to sctdr1. similarly, the rdrf flag is cleared automatically when the dmac is activated by a receive-data-full interrupt (rxi) request and the scrdr1 value is read.) note: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1. figure 15.23 sample flowchart for serial data transmission and reception
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 717 of 1076 sep 24, 2013 15.4 sci interrupt sources and dmac the sci has four interrupt sources : the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full in terrupt (rxi) request, and tran smit-data-empty interrupt (txi) request. table 15.12 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in scrsr1, and the eio bit in scsptr1. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in the serial status register (scssr1) is set to 1, a tdr-empty request is generated separately from the interrupt request . a tdr-empty request can activate the direct memory access controller (dmac) to perform data transfer. the tdre flag is cleared to 0 automatically when a write to the transmit data register (sctdr1) is performed by the dmac. when the rdrf flag in scssr1 is set to 1, an rdr-full request is generated separately from the interrupt request. an rdr-full request can activate the dmac to perform data transfer. the rdrf flag is cleared to 0 automatically wh en a receive data register (scrdr1) read is performed by the dmac. when the orer, fer, or per flag in scssr1 is se t to 1, an eri interrupt request is generated. the dmac cannot be activated by an eri interrupt request. when receive data processing is to be carried out by the dmac and receive error handling is to be performed by means of an interrupt to the cpu, set the rie bit to 1 and also set the eio bit in scsptr1 to 1 so that an interrupt error occurs only for a receive error. if the eio bit is cleared to 0, interrupts to the cpu will be generated even during normal data reception. when the tend flag in scssr1 is set to 1, a tei interrupt request is generated. the dmac cannot be activated by a tei interrupt request. a txi interrupt indicates that transmit data can be written, and a tei inte rrupt indicates that the transmit operation has ended.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 718 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 15.12 sci interrupt sources interrupt source description dmac activation priority on reset release eri receive error (orer, fer, or per) not possible high rxi receive data register full (rdrf) possible txi transmit data register empty (tdre) possible tei transmit end (tend) not possible low see section 5, exceptions, for the priority order and relation to non-sci interrupts. 15.5 usage notes the following points should be noted when using the sci. sctdr1 writing and the tdre flag: the tdre flag in scssr1 is a status flag that indicates that transmit data has been transferred from sc tdr1 to sctsr1. when the sci transfers data from sctdr1 to sctsr1, the tdre flag is set to 1. data can be written to sctdr1 regardless of the state of the tdre flag. however, if new data is written to sctdr1 when the tdre flag is cleared to 0, the data stored in sctdr1 will be lost since it has not yet been transferred to sctsr1. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to sctdr1. simultaneous multip le receive errors: if a number of receive errors occur at the same time, the state of the status flags in scssr1 is as shown in table 15.13. if there is an overrun error, data is not transferred from scrsr1 to scrd r1, and the receive data is lost.
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 719 of 1076 sep 24, 2013 table 15.13 scssr1 status flags and transfer of receive data scssr1 status flags receive errors rdrf orer fer per receive data transfer scrsr1 scrdr1 overrun error 1 1 0 0 x framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 x overrun error + parity error 1 1 0 1 x framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1 1 1 1 x legend: o: receive data is transferred from scrsr1 to scrdr1. x: receive data is not transferred from scrsr1 to scrdr1. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the br eak state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity erro r flag (per) may also be set. note that the sci receiver continues to operate in the br eak state, so if the fer flag is cleared to 0 it will be set to 1 again. sending a break signal: the input/output condition and level of the txd pin are determined by bits spb0io and spb0dt in the serial port register (scsptr1). this feature can be used to send a break signal. after the serial transmitter is initialized, the txd pin function is not selected and the value of the spb0dt bit substitutes for the mark state until the te bit is set to 1 (i.e. transmission is enabled). the spb0io and spb0dt bits should therefore be set to 1 (designating output and high level) beforehand. to send a break signal during serial transmissi on, clear the spb0dt bit to 0 (designating low level), then clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of its current state, and the txd pin becomes an output port outputting the value 0.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 720 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 handling of tend flag and te bit: the tend flag is set to 1 when the stop bit of the final data segment is transmitted. if the te bit is cl eared immediately after confirming that the tend flag was set, transmission may not complete properly because stop bit transmission processing is still underway. therefore, wait at least 0.5 serial clock cycles (1.5 cycles if two stop bits are used) after confirming that the tend flag was set before clearing the te bit. receive error flags and transmit op erations (synchronous mode only): transmission cannot be started when a receive er ror flag (orer, per, or fer) is set to 1, even if the tdre flag is set to 1. be sure to clear the receive error flags to 0 before starting transmission. note also that the receive error flags are not cleared to 0 by clearing the re bit to 0. receive data sampling timi ng and receive margin in asynchronous mode: the sci operates on a base clock with a frequency of 16 times the bit rate. in reception, the sci synchronizes internally w ith the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 15.24. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 d0 d1 16 clocks 8 clocks base clock receive data (rxd) start bit ?7.5 clocks +7.5 clocks synchronization sampling timing data sampling timing figure 15.24 receive data sampling timing in asynchronous mode
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 721 of 1076 sep 24, 2013 the receive margin in asynchron ous mode can therefore be expres sed as shown in equation (1). m = (0.5 ? ) ? (l ? 0.5) f ? (1 + f) 100 % 1 2n | d ? 0.5 | n ................ (1) m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875 % , as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 1/(2 16)) 100 % = 46.875 % ............................................ (2) this is a theoretical value. a reasonable margin to allow in system designs is 20 % to 30 % . when using the dmac: ? when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 peripheral operating clock cycles after sctdr1 is updated by the dmac. incorrect operation may result if the transmit clock is input within 4 cycles after sctdr1 is updated. (see figure 15.25) sck tdre txd d0 d1 d2 d3 d4 d5 d6 d7 t note: when operating on an external clock, set t > 4. figure 15.25 example of synchronous transmission by dmac ? when scrdr1 is read by the dmac, be sure to set the sci receive-data-full interrupt (rxi) as the activation source with bits rs3 to rs0 in chcr.
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 722 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? when using the dmac for transmission/reception, making a setting to disable rxi and txi interrupt requests to the interrupt controller. ev en if issuance of interrupt requests is set, interrupt requests to the interrupt controller will be cleared by the dmac independently of the interrupt handling program. when using synchronous external clock mode: ? do not set te or re to 1 until at least 4 peripheral operating clock cycles after external clock sck has changed from 0 to 1. ? only set both te and re to 1 when external clock sck is 1. ? in reception, note that if re is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles after the rising edge of the rxd d7 bit sck input, rdrf will be set to 1 but copying to scrdr1 will not be possible. when using synchronous internal clock mode: in reception, note that if re is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the rxd d7 bit sck output, rdrf will be set to 1 but copying to scrdr1 will not be possible. when using dmac: when using the dmac for transmission/reception, make a setting to suppress output of rxi and txi interrupt requests to the interrupt controller. even if a setting is made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by the dmac independently of the interrupt handling program. SH7750 only: when the following conditions are satisfied, the same data may be transmitted multiple times. ? conditions under which problem occurs a. external sck clock input mode is selected (scscr1.cke1 = 1). b. synchronous mode is selected (scsmr1c/a = 1). c. transmit or receive is in progress (scscr1.te = 1). conditions a. to c. must all be satisfied. ? workarounds workaround 1 ? pll2 on as shown in figure 15.26, after synchronizing asynchronous input external clock sck with ckio, input it to the sck pin of the SH7750. in this case the sck clock cycle minimum value will be: peripheral clock cycle (pck) 8. note that this wo rkaround will reduce the timing margins of the txd and rxd pins synchronized with the sck pin. ? pll2 off operation cannot be guaranteed. (usage prohibited.)
SH7750, SH7750s, SH7750r group section 15 serial communication interface (sci) r01uh0456ej0702 rev. 7.02 page 723 of 1076 sep 24, 2013 workaround 2 do not select settings a., b., and c. at the same time. md0/sck SH7750 ckio a dq b edge trigger ff multiplexer (switches between clock mode and sck input) mode setting signal figure 15.26 example co untermeasure on SH7750 ? clock timing make sure that the timing of the clock input to the sck pin, including the delay from edge trigger ff and the multiplexer in figure 15.26, conforms to that shown below. ckio sck tscks tsckh tscks tsckh figure 15.27 clock input timing of sck pin
section 15 serial communication in terface (sci) SH7750, SH7750s, SH7750r group page 724 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 15.14 peripheral module signal timing tscks tsckh product min max min max unit hd6417750bp200 5 ? 0 ? ns hd6417750bp200m 5 ? 0 ? ns hd6417750f167 5 ? 0 ? ns hd6417750f167i 5 ? 0 ? ns hd6417750vf128 8 ? 0 ? ns
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 725 of 1076 sep 24, 2013 section 16 serial communi cation interface with fifo (scif) 16.1 overview this lsi is equipped with a single-channel serial communication interface with built-in fifo buffers (serial communication in terface with fifo: scif ). the scif can perform asynchronous serial communication. sixteen-stage fifo registers ar e provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1.1 features scif features are listed below. ? asynchronous serial communication serial data communication is executed us ing an asynchronous system in which synchronization is achieved character by charact er. serial data commun ication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchrono us communication interface adapter (acia). there is a choice of 8 serial data transfer formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? receive error detection: parity , framing, and overrun errors ? break detection: if the receive data following that in which a framing error occurred is also at the space ?0? level, and there is a frame erro r, a break is detected. when a framing error occurs, a break can also be det ected by reading the rxd2 pin le vel directly from the serial port register (scsptr2). ? full-duplex communication capability the transmitter and receiver are independent units , enabling transmission and reception to be performed simultaneously. the transmitter and receiver both have a 16-stage fifo buffer structure, enabling fast and continuous serial data transmission and reception. ? on-chip baud rate generator allows any bit rate to be selected. ? choice of serial clock source: internal clock from baud rate generator or external clock from sck2 pin
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 726 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? four interrupt sources there are four interrupt sour ces?transmit-fifo-dat a-empty, break, receive-fifo-data-full, and receive-error?that can issu e requests independently. ? the dma controller (dmac) can be activated to execute a data transfer by issuing a dma transfer request in the event of a transmit-fifo-data-empty or receive-fifo-data-full interrupt. ? when not in use, the scif can be stopped by halting its clock supply to reduce power consumption. ? modem control functions ( rts2 and cts2 ) are provided. ? the amount of data in the transm it/receive fifo registers, and the number of receive errors in the receive data in the receive fi fo register, can be ascertained. ? a timeout error (dr) can be detected during reception.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 727 of 1076 sep 24, 2013 16.1.2 block diagram figure 16.1 shows a block diagram of the scif. module data bus scfrdr2 (16-stage) scrsr2 rxd2 txd2 sck2 cts2 rts2 scftdr2 (16-stage) sctsr2 scsmr2 sclsr2 scfdr2 scfcr2 scfsr2 scbrr2 parity generation parity check transmission/ reception control baud rate generator clock external clock pck pck/4 pck/16 pck/64 txi rxi eri bri scif bus interface internal data bus scscr2 scsptr2 legend: scrsr2: receive shift register scfrdr2: receive fifo data register sctsr2: transmit shift register scftdr2: transmit fifo data register scsmr2: serial mode register scscr2: serial control register scfsr2: serial status register scbrr2: bit rate register scsptr2: serial port register scfcr2: fifo control register scfdr2: fifo data count register sclsr2: line status register figure 16.1 block diagram of scif
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 728 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 16.1.3 pin configuration table 16.1 shows the scif pin configuration. table 16.1 scif pins pin name abbreviation i/o function serial clock pin sck2/ mreset input clock input receive data pin md2/rxd2 input receive data input transmit data pin md1/txd2 output transmit data output modem control pin cts2 i/o transmission enabled modem control pin md8/ rts2 i/o transmission request note: after a power-on reset, these pins function as mode input pins md1, md2, and md8. these pins can function as serial pins by setti ng the scif operation with the te, re, and cke1 bits in scscr2 and the mce bit in scfcr2. these pins are made to function as serial pins by performing scif operation settings with the te, re, and cke1 bits in scscr2 and the mce bit in scfcr2. break state transmissi on and detection can be set in the scif's scsptr2 register.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 729 of 1076 sep 24, 2013 16.1.4 register configuration the scif has the internal regist ers shown in table 16.2. these re gisters are used to specify the data format and bit rate, and to pe rform transmitter/receiver control. table 16.2 scif registers name abbrevia- tion r/w initial value p4 address area 7 address access size serial mode register scsmr2 r/w h'0000 h'ffe 80000 h'1fe80000 16 bit rate register scbrr2 r/w h'ff h'ffe80004 h'1fe80004 8 serial control register scscr2 r/w h'0000 h'ffe 80008 h'1fe80008 16 transmit fifo data register scftdr2 w undefined h'ffe8000c h'1fe8000c 8 serial status register scfsr2 r/(w) * 1 h'0060 h'ffe80010 h'1fe80010 16 receive fifo data register scfrdr2 r undefined h'ffe80014 h'1fe80014 8 fifo control register scfcr2 r/w h'0000 h'ffe 80018 h'1fe80018 16 fifo data count register scfdr2 r h'0000 h'ffe8001c h'1fe8001c 16 serial port register scsptr2 r/w h'0000 * 2 h'ffe80020 h'1fe80020 16 line status register sclsr2 r/(w) * 3 h'0000 h'ffe80024 h'1fe80024 16 notes: 1. only 0 can be written, to clear flags. bits 15 to 8, 3, and 2 are read-only, and cannot be modified. 2. the value of bits 6, 4, and 0 is undefined. 3. only 0 can be written, to clear flags. bits 15 to 1 are read-only, and cannot be modified. 16.2 register descriptions 16.2.1 receive shift register (scrsr2) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? scrsr2 is the register used to receive serial data. the scif sets serial data input from the rxd2 pi n in scrsr2 in the orde r received, starting with the lsb (bit 0), and converts it to parallel data. wh en one byte of data has been received, it is transferred to the recei ve fifo register, scfrdr2, automatically.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 730 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 scrsr2 cannot be directly read or written to by the cpu. 16.2.2 receive fifo data register (scfrdr2) bit: 7 6 5 4 3 2 1 0 r/w: r r r r r r r r scfrdr2 is a 16-stage fifo register that stores received serial data. when the scif has received one byte of serial da ta, it transfers the receive d data from scrsr2 to scfrdr2 where it is stored, and completes the r eceive operation. scrsr2 is then enabled for reception, and consecutive receive op erations can be performed until the receive fifo register is full (16 data bytes). scfrdr2 is a read-only register, and cannot be written to by the cpu. if a read is performed when there is no receive data in the receive fifo register, an undefined value will be returned. when the r eceive fifo register is full of receive data, subsequent serial data is lost. the contents of scfrdr2 are undefined after a power-on reset or manual reset. 16.2.3 transmit shift register (sctsr2) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? sctsr2 is the register used to transmit serial data. to perform serial data transmission, the scif first transfers transmit data from scftdr2 to sctsr2, then sends the data to the txd2 pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from scftdr2 to sctsr2, and transmission started, automatically. sctsr2 cannot be directly read or written to by the cpu.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 731 of 1076 sep 24, 2013 16.2.4 transmit fifo data register (scftdr2) bit: 7 6 5 4 3 2 1 0 r/w: w w w w w w w w scftdr2 is an 8-bit 16-stage fifo register that stores da ta for serial transmission. if sctsr2 is empty when transmit data has been written to scftdr2, the scif transfers the transmit data written in scftdr2 to scts r2 and starts serial transmission. scftdr2 is a write-only register, and cannot be read by the cpu. the next data cannot be written when scftdr2 is filled with 16 bytes of transmit data. data written in this case is ignored. the contents of scftdr2 are undefined after a power-on reset or manual reset. 16.2.5 serial mode register (scsmr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? chr pe o/ e stop ? cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r r/w r/w scsmr2 is a 16-bit register used to set the scif's serial transfer format and select the baud rate generator clock source. scsmr2 can be read or written to by the cpu at all times. scsmr2 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in th e module standby state. bits 15 to 7?reserved: these bits are always read as 0, and should only be written with 0.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 732 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 6?character length (chr): selects 7 or 8 bits as the asynchronous mode data length. bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (b it 7) of scftdr2 is not transmitted. bit 5?parity enable (pe): selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. bit 5: pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in recepti on, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4?parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking. the o/ e bit setting is invalid when parity addition and checking is disabled. bit 4: o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit additi on is performed in transmission so that the total number of 1-bits in the transmit character pl us the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bi ts in the receive character plus the parity bit is odd.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 733 of 1076 sep 24, 2013 bit 3?stop bit length (stop): selects 1 or 2 bits as the stop bit length. bit 3: stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1-bit (stop bi t) is added to the end of a transmit character before it is sent. 2. in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the star t bit of the next transmit character. bit 2?reserved: this bit is always read as 0, and should only be written with 0. bits 1 and 0?clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. the clock source can be selected from pck, pck/4, pck/16, and pck/64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, bit rate register (scbrr2). bit 1: cks1 bit 0: cks0 description 0 0 pck clock (initial value) 1 pck/4 clock 1 0 pck/16 clock 1 pck/64 clock note: pck: peripheral clock
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 734 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 16.2.6 serial control register (scscr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 tie rie te re reie ? cke1 ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r r/w r the scscr2 register performs enabling or disabling of scif transfer operations, and interrupt requests, and selection of the serial clock source. scscr2 can be read or written to by the cpu at all times. scscr2 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in th e module standby state. bits 15 to 8, 2, and 0?reserved: these bits are always read as 0, and should only be written with 0. bit 7?transmit interrupt enable (tie): enables or disables transmit-fifo-data-empty interrupt (txi) request generation when serial tr ansmit data is transferred from scftdr2 to sctsr2, the number of data bytes in the transmit fifo register falls to or below the transmit trigger set number, and the tdfe flag in the se rial status register (scfsr2) is set to 1. bit 7: tie description 0 transmit-fifo-data-empty in terrupt (txi) request disabled * (initial value) 1 transmit-fifo-data-empty in terrupt (txi) request enabled note: * txi interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to scftdr2 after reading 1 from the tdfe flag, then clearing it to 0, or by clearing the tie bit to 0.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 735 of 1076 sep 24, 2013 bit 6?receive interrupt enable (rie): enables or disables genera tion of a receive-data-full interrupt (rxi) request when the rdf flag or dr flag in scfsr2 is set to 1, a receive-error interrupt (eri) request when the er flag in scfsr2 is set to 1, and a break interrupt (bri) request when the brk flag in scfsr2 or the orer flag in sclsr2 is set to 1. bit 6: rie description 0 receive-data-full interrupt (rxi) request, receive-error interrupt (eri) request, and break interrupt (bri) request disabled * (initial value) 1 receive-data-full interrupt (rxi) request, receive-error interrupt (eri) request, and break interrupt (bri) request enabled note: * an rxi interrupt request can be cleared by reading 1 from the rdf or dr flag, then clearing the flag to 0, or by clearing the ri e bit to 0. eri and bri interrupt requests can be cleared by reading 1 from the er, brk, or orer flag, then clearing the flag to 0, or by clearing the rie and reie bits to 0. bit 5?transmit enable (te): enables or disables the start of serial transmission by the scif. bit 5: te description 0 transmission disabled (initial value) 1 transmission enabled * note: * serial transmission is started when transmit data is written to scftdr2 in this state. serial mode register (scsmr2) and fifo control register (scfcr2) settings must be made, the transmission format decided, and t he transmit fifo reset, before the te bit is set to 1. bit 4?receive enable (re): enables or disables the start of serial reception by the scif. bit 4: re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not a ffect the dr, er, brk, rdf, fer, per, and orer flags, which retain their states. 2. serial transmission is started when a start bit is detected in this state. serial mode register (scsmr2) and fifo control register (scfcr2) settings must be made, the reception format decided, and the re ceive fifo reset, before the re bit is set to 1.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 736 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 3?receive error interrupt enable (reie): enables or disables gene ration of receive-error interrupt (eri) and break interrupt (bri) requests. the reie bit setting is valid only when the rie bit is 0. bit 3: reie description 0 receive-error interrupt (eri) and break interrupt (bri) requests disabled * (initial value) 1 receive-error interrupt (eri) and br eak interrupt (bri) requests enabled note: * receive-error interrupt (eri) and break in terrupt (bri) requests can be cleared by reading 1 from the er, brk, or orer flag, t hen clearing the flag to 0, or by clearing the rie and reie bits to 0. when reie is set to 1, eri and bri interrupt requests will be generated even if rie is cleared to 0. in dmac transfer, this setting is made if the interrupt controller is to be notified of eri and bri interrupt requests. bit 1?clock enable 1 (cke1): selects the scif clock source. th e cke1 bit must be set before determining the scif's operating mode with scsmr2. bit 1: cke1 description 0 internal clock/sck2 pin functions as port (initial value) 1 external clock/sck2 pin functions as clock input * note: * inputs a clock with a frequency 16 times the bit rate.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 737 of 1076 sep 24, 2013 16.2.7 serial status re gister (scfsr2) bit: 15 14 13 12 11 10 9 8 per3 per2 per1 per0 fer3 fer2 fer1 fer0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 er tend tdfe brk fer per rdf dr initial value: 0 1 1 0 0 0 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r r r/(w) * r/(w) * note: * only 0 can be written, to clear the flag. scfsr2 is a 16-bit register. the lower 8 bits co nsist of status flags that indicate the operating status of the scif, and the upper 8 bits indicate th e number of receive erro rs in the data in the receive fifo register. scfsr2 can be read or written to by the cpu at all times. however, 1 cannot be written to flags er, tend, tdfe, brk, rdf, and dr. also note that in order to cl ear these flags they must be read as 1 beforehand. the fer flag and per fl ag are read-only flags and cannot be modified. scfsr2 is initialized to h'0060 by a power-on reset or manual reset. it is not initialized in standby mode or in th e module standby state. bits 15 to 12?number of parity errors (per3?per0): these bits indicate the number of data bytes in which a parity erro r occurred in the receive data stored in scfrdr2. after the er bit in scfsr2 is set, the value indicated by bits 15 to 12 is the number of data bytes in which a parity error occurred. if all 16 bytes of receive data in scfrdr2 have pa rity errors, the value indicated by bits per3 to per0 will be 0. bits 11 to 8?number of framing errors (fer3?fer0): these bits indicate the number of data bytes in which a framing error occurred in the receive data stored in scfrdr2. after the er bit in scfsr2 is set, the value indicated by bits 11 to 8 is the number of data bytes in which a framing error occurred.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 738 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 if all 16 bytes of receive data in scfrdr2 have framing errors, the value indicated by bits fer3 to fer0 will be 0. bit 7?receive error (er): indicates that a framing error or parity error occurred during reception.* note: * the er flag is not affected and retains its previous state when the re bit in scscr2 is cleared to 0. when a receive error occurs, the receive data is still transferred to scfrdr2, and reception continues. the fer and per bits in scfsr2 can be used to determine whether there is a receive error that is to be from scfrdr2. bit 7: er description 0 no framing error or parity error occurred during reception (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to er after reading er = 1 1 a framing error or parity error occurred during reception [setting conditions] ? when the scif checks whether the st op bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 * ? when, in reception, the number of 1- bits in the receive data plus the parity bit does not match the parity se tting (even or odd) specified by the o/ e bit in scsmr2 note: * in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 739 of 1076 sep 24, 2013 bit 6?transmit end (tend): indicates that there is no valid data in scftdr2 when the last bit of the transmit character is sent , and transmission has been ended. bit 6: tend description 0 transmission is in progress [clearing conditions] ? when transmit data is written to scftdr2, and 0 is written to tend after reading tend = 1 ? when data is written to scftdr2 by the dmac 1 transmission has been ended (initial value) [setting conditions] ? power-on reset or manual reset ? when the te bit in scscr2 is 0 ? when there is no transmit data in sc ftdr2 on transmission of the last bit of a 1-byte serial transmit character
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 740 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 5?transmit fifo data empty (tdfe): indicates that data ha s been transferred from scftdr2 to sctsr2, the number of data bytes in scftdr2 has fallen to or below the transmit trigger data number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr2), and new transmit data can be written to scftdr2. bit 5: tdfe description 0 a number of transmit data bytes exceeding the transmit trigger set number have been written to scftdr2 [clearing conditions] ? when transmit data exceeding the transmit trigger set number is written to scftdr2 after reading tdfe = 1, and 0 is written to tdfe ? when transmit data exceeding the transmit trigger set number is written to scftdr2 by the dmac 1 the number of transmit data bytes in scftdr2 does not exceed the transmit trigger set number (initial value) [setting conditions] ? power-on reset or manual reset ? when the number of scftdr2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation * note: * as scftdr2 is a 16-byte fifo register , the maximum number of bytes that can be written when tdfe = 1 is 16 - (transmit trigger set number). data written in excess of this will be ignored. the number of data bytes in scftdr2 is indicated by the upper bits of scfdr2.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 741 of 1076 sep 24, 2013 bit 4?break detect (brk): indicates that a receive data break signal has been detected. bit 4: brk description 0 a break signal has not been received (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to brk after reading brk = 1 1 a break signal has been received * [setting condition] when data with a framing error is received, followed by the space ?0? level (low level ) for at least one frame length note: * when a break is detected, the receive data (h'00) following detection is not transferred to scfrdr2. when the break ends and the rece ive signal returns to mark ?1?, receive data transfer is resumed. bit 3?framing error (fer): indicates whether or not a framing error has been found in the data that is to be read next from scfrdr2. bit 3: fer description 0 there is no framing error that is to be read from scfrdr2 (initial value) [clearing conditions] ? power-on reset or manual reset ? when there is no framing error in the data that is to be read next from scfrdr2 1 there is a framing error that is to be read from scfrdr2 [setting condition] when there is a framing error in t he data that is to be read next from scfrdr2
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 742 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 2?parity error (per): indicates whether or not a parity error has been found in the data that is to be read next from scfrdr2. bit 2: per description 0 there is no parity error that is to be read from scfrdr2 (initial value) [clearing conditions] ? power-on reset or manual reset ? when there is no parity error in the data that is to be read next from scfrdr2 1 there is a parity error in the receive data that is to be read from scfrdr2 [setting condition] when there is a parity error in the data that is to be read next from scfrdr2
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 743 of 1076 sep 24, 2013 bit 1?receive fifo data full (rdf): indicates that the received data has been transferred from scrsr2 to scfrdr2, and th e number of receive data byte s in scfrdr2 is equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr2). bit 1: rdf description 0 the number of receive data bytes in scfrdr2 is less than the receive trigger set number (initial value) [clearing conditions] ? power-on reset or manual reset ? when scfrdr2 is read until the number of receive data bytes in scfrdr2 falls below the receive trigger set number after reading rdf = 1, and 0 is written to rdf ? when scfrdr2 is read by the dmac until the number of receive data bytes in scfrdr2 falls below the receive trigger set number 1 the number of receive data bytes in scfrdr2 is equal to or greater than the receive trigger set number [setting condition] when scfrdr2 contains at least the re ceive trigger set number of receive data bytes * note: * scfrdr2 is a 16-byte fifo register. when rdf = 1, at least the receive trigger set number of data bytes can be read. if all the data in scfrdr2 is read and another read is performed, the data value will be undefin ed. the number of receive data bytes in scfrdr2 is indicated by the lower bits of scfdr2.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 744 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 0?receive data ready (dr): indicates that there are fewer than the receive trigger set number of data bytes in scfrdr2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. bit 0: dr description 0 reception is in progress or has ended normally and there is no receive data left in scfrdr2 (i nitial value) [clearing conditions] ? power-on reset or manual reset ? when all the receive data in scfrdr2 has been read after reading dr = 1, and 0 is written to dr ? when all the receive data in scfrdr2 has been read by the dmac 1 no further receive data has arrived [setting condition] when scfrdr2 contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received * note: * equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: elementary time unit (time for transfer of 1 bit) 16.2.8 bit rate register (scbrr2) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scbrr2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr2. scbrr2 can be read or written to by the cpu at all times. scbrr2 is initialized to h'ff by a power-on reset or manual reset. it is not initialized in standby mode or in the module standby state.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 745 of 1076 sep 24, 2013 the scbrr2 setting is found from the following equation. asynchronous mode: n = 10 6 ? 1 64 2 2n ? 1 b pck where b: bit rate (bits/s) n: scbrr2 setting for baud rate generator (0 n 255) pck: peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr2 setting n clock cks1 cks0 0 pck 0 0 1 pck/4 0 1 2 pck/16 1 0 3 pck/64 1 1 the bit rate error in asynchronous mode is found from the following equation: error ( % ) = ? 1 100 pck 10 6 (n + 1) b 64 2 2n ? 1 16.2.9 fifo control register (scfcr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? rstrg2 * rstrg1 * rstrg0 * initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bit: 7 6 5 4 3 2 1 0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * reserved bit in the SH7750.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 746 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 scfcr2 performs data count resetting and trigger da ta number setting for the transmit and receive fifo registers, and also contai ns a loopback test enable bit. scfcr2 can be read or written to by the cpu at all times. scfcr2 is initialized to h'0000 by a power-on reset or manual reset. it is not initialized in standby mode or in th e module standby state. bits 15 to 11?reserved: these bits are always read as 0, and should only be written with 0. bits 10 to 8 (SH7750)?reserved: these bits are always read as 0, and should only be written with 0. bits 10 to 8 (SH7750s, SH7750r)? rts2 output active trigger (rstrg2, rstg1, and rstg0): these bits output the high level to the rts2 signal when the number of received data stored in the receive fifo data register (scf rdr2) exceeds the trigger number, as shown in the table below. bit 10: rstrg2 bit 9: rstrg1 bit 8: rstrg0 rts2 output active trigger 0 15 (initial value) 0 1 1 0 4 0 1 1 6 0 8 0 1 10 1 1 0 12 1 14
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 747 of 1076 sep 24, 2013 bits 7 and 6?receive fifo data number trigger (rtrg1, rtrg0): these bits are used to set the number of receive data bytes that sets the receive data full (rdf) flag in the serial status register (scfsr2). the rdf flag is set when the number of receive data bytes in scfrdr2 is equal to or greater than the trigger set number shown in the following table. bit 7: rtrg1 bit 6: rtrg 0 receive trigger number 0 0 1 (initial value) 1 4 1 0 8 1 14 bits 5 and 4?transmit fifo data number trigger (ttrg1, ttrg0): these bits are used to set the number of remaining transmit data bytes that sets the transmit fifo data register empty (tdfe) flag in the serial status register (scf sr2). the tdfe flag is set when the number of transmit data bytes in scftdr2 is equal to or less than the trigger set number shown in the following table. ? SH7750 bit 5: ttrg1 bit 4: ttrg0 transmit trigger number 0 0 7 (9) (initial value) 1 3 (13) 1 0 1 (15) 1 0 (16) note: figures in parentheses are the number of empty bytes in scftdr2 when the flag is set. ? SH7750s/SH7750r bit 5: ttrg1 bit 4: ttrg0 transmit trigger number 0 0 8 (8) (initial value) 1 4 (12) 1 0 2 (14) 1 1 (15) note: figures in parentheses are the number of empty bytes in scftdr2 when the flag is set.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 748 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 3?modem control enable (mce): enables the cts2 and rts2 modem control signals. bit 3: mce description 0 modem signals disabled * (initial value) 1 modem signals enabled note: * cts2 is fixed at active-0 regardless of the input value, and rts2 output is also fixed at 0. bit 2?transmit fifo data register reset (tfrst): invalidates the transmit data in the transmit fifo data register and resets it to the empty state. bit 2: tfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. bit 1?receive fifo data register reset (rfrst): invalidates the receive data in the receive fifo data register and rese ts it to the empty state. bit 1: rfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. bit 0?loopback test (loop): internally connects th e transmit output pin (txd2) and receive input pin (rxd2), and the rts2 pin and cts2 pin, enabling loopback testing. bit 0: loop description 0 loopback test disabled (initial value) 1 loopback test enabled
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 749 of 1076 sep 24, 2013 16.2.10 fifo data count register (scfdr2) scfdr2 is a 16-bit register that indicates the number of data bytes stored in scftdr2 and scfrdr2. the upper 8 bits show the number of transmit data bytes in scftdr2, and the lower 8 bits show the number of receive da ta bytes in scfrdr2. scfdr2 can be read by the cpu at all times. bit: 15 14 13 12 11 10 9 8 ? ? ? t4 t3 t2 t1 t0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r these bits show the number of untransmitted data bytes in scftdr2. a value of h'00 indicates that there is no transmit data, and a value of h'10 indicates that scftdr2 is full of transmit data. bit: 7 6 5 4 3 2 1 0 ? ? ? r4 r3 r2 r1 r0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r these bits show the numb er of receive data bytes in scfrdr 2. a value of h'00 indicates that there is no receive data, and a value of h'10 indicates that sc frdr2 is full of receive data.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 750 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 16.2.11 serial port register (scsptr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 rtsio rtsdt ctsio ctsdt ? ? spb2io spb2dt initial value: 0 ? 0 ? 0 ? 0 ? r/w: r/w r/w r/w r/w r r r/w r/w scsptr2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (scif) pins. input data can be read from the rxd2 pin, output data written to the txd2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. data can be read from, and output data written to, the cts2 pin by means of bits 5 and 4. data can be read from, and output data written to, the rts2 pin by means of bits 6 and 7. scsptr2 can be read or written to by the cpu at all times. all scsptr2 bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or ma nual reset; the value of bits 6, 4, and 0 is undefined. scsptr2 is not initialized in standby mode or in the module standby state. bits 15 to 8?reserved: these bits are always read as 0, and should only be written with 0. bit 7?serial port rts port i/o (rtsio): specifies the serial port rts2 pin input/output condition. when the rts2 pin is actually set as a port output pin and outputs the value set by the rtsdt bit, the mce bit in scfcr2 should be cleared to 0. bit 7: rtsio description 0 rtsdt bit value is not output to rts2 pin (initial value) 1 rtsdt bit value is output to rts2 pin
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 751 of 1076 sep 24, 2013 bit 6?serial port rts port data (rtsdt): specifies the serial port rts2 pin input/output data. input or output is specified by the rtsio bit (see the description of bit 7, rtsio, for details). in output mode, the rtsdt bit value is output to the rts2 pin. the rts2 pin value is read from the rtsdt bit regardless of the value of the rtsio bit. the initial value of this bit after a power-on reset or manual reset is undefined. bit 6: rtsdt description 0 input/output data is low-level 1 input/output data is high-level bit 5?serial port cts port i/o (ctsio): specifies the serial port cts2 pin input/output condition. when the cts2 pin is actually set as a port output pin and outputs the value set by the ctsdt bit, the mce bit in scfcr2 should be cleared to 0. bit 5: ctsio description 0 ctsdt bit value is not output to cts2 pin (initial value) 1 ctsdt bit value is output to cts2 pin bit 4?serial port cts port data (ctsdt): specifies the serial port cts2 pin input/output data. input or output is specified by the ctsio bit (see the description of bit 5, ctsio, for details). in output mode, the ctsdt bit value is output to the cts2 pin. the cts2 pin value is read from the ctsdt bit regardless of the value of the ctsio bit. the initial value of this bit after a power-on reset or manual reset is undefined. bit 4: ctsdt description 0 input/output data is low-level 1 input/output data is high-level bit 3?reserved: this bit is always read as 0, and should only be written with 0. bit 2?reserved: the value of this bit is undefined when read. the write value should always be 0.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 752 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 1?serial port break i/o (spb2io): specifies the serial port txd2 pin output condition. when the txd2 pin is actually set as a port output pin and outputs the value set by the spb2dt bit, the te bit in scscr2 should be cleared to 0. bit 1: spb2io description 0 spb2dt bit value is not output to the txd2 pin (initial value) 1 spb2dt bit value is output to the txd2 pin bit 0?serial port break data (spb2dt): specifies the serial port rxd2 pin input data and txd2 pin output data. the txd2 pin output condition is specified by the spb2io bit (see the description of bit 1, spb2io, for details). when the txd2 pin is designated as an output, the value of the spb2dt bit is output to the txd2 pin. the rxd2 pin value is read from the spb2dt bit regardless of the value of the spb2io bit. the in itial value of this bit after a power-on reset or manual reset is undefined. bit 0: spb2dt description 0 input/output data is low-level 1 input/output data is high-level
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 753 of 1076 sep 24, 2013 scif i/o port block diagrams are shown in figures 16.2 to 16.5. reset internal data bus sptrw d7 d6 scif r q d rtsio c reset mode settin g re g ister sptrr sptrw r q d rtsdt c md8/ r t s2 le g end: sptrw: write to sptr sptrr: read sptr note: * the r t s2 pin function is desi g nated as modem control by the mce bit in scfcr2. modem control enable si g nal * r t s2 si g nal figure 16.2 md8/ rts2 pin
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 754 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 reset internal data bus sptrw d5 d4 scif r q d ctsio c reset sptrr sptrw r q d ctsdt c c t s2 le g end: sptrw: write to sptr sptrr: read sptr note: * the c t s2 pin function is desi g nated as modem control by the mce bit in scfcr2. modem control enable si g nal * c t s2 si g nal figure 16.3 cts2 pin
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 755 of 1076 sep 24, 2013 reset internal data bus sptrw mode settin g re g ister scif r q d d1 d0 spb2io c reset sptrw r q d spb2dt c md1/txd2 le g end: sptrw: write to sptr transmit enable si g nal serial transmit data figure 16.4 md1/txd2 pin internal data bus mode settin g re g ister scif md2/rxd2 sptrr d0 serial receive data le g end: sptrr: read sptr figure 16.5 md2/rxd2 pin
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 756 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 16.2.12 line status register (sclsr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? orer initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r (r/w) * note: * only 0 can be written, to clear the flag. bits 15 to 1?reserved: these bits are always read as 0, and should only be written with 0. bit 0?overrun error (orer): indicates that an overrun er ror occurred during reception, causing abnormal termination. bit 0: orer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] ? power-on reset or manual reset ? when 0 is written to orer after reading orer = 1 1 an overrun error occurred during reception * 2 [setting condition] when the next serial reception is completed while the receive fifo is full notes: 1. the orer flag is not affected and re tains its previous state when the re bit in scscr2 is cleared to 0. 2. the receive data prior to the overr un error is retained in scfrdr2, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 757 of 1076 sep 24, 2013 16.3 operation 16.3.1 overview the scif can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. see section 15.3.2 , operation in asynchronous mode, for details. sixteen-stage fifo buffers are provided for both transmission an d reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. rts2 and cts2 signals are also provided as modem control signals. the transmission format is selected using the se rial mode register (scsmr2), as shown in table 16.3. the scif clock source is determined by the cke1 bit in the serial control register (scscr2), as shown in table 16.4. ? data length: choice of 7 or 8 bits ? choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer fo rmat and character length) ? detection of framing errors, parity errors, receiv e-fifo-data-full state, overrun errors, receive- data-ready state, and br eaks, during reception ? indication of the number of data bytes stored in the transmit and receive fifo registers ? choice of internal or external clock as scif clock source when internal clock is selected: the scif operat es on the baud rate generator clock, and can output a clock with a frequency of 16 times the bit rate. when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used).
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 758 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 16.3 scsmr2 settings for serial transfer format selection scsmr2 settings scif transfer format bit 6: chr bit 5: pe bit 3: stop mode data length multiprocessor bit parity bit stop bit length 0 0 0 asynchronous mode 8-bit data no no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits table 16.4 scscr2 settings fo r scif clock source selection scscr2 setting scif transmit/receive clock bit 1: cke1 mode clock source sck2 pin function 0 asynchronous mode internal scif does not use sck2 pin 1 external inputs clock with frequency of 16 times the bit rate 16.3.2 serial operation transmit/receive format table 16.5 shows the transmit/receive formats that can be used. any of 8 transfer formats can be selected according to the scsmr2 settings.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 759 of 1076 sep 24, 2013 table 16.5 serial transmit/receive formats scsmr2 settings serial transmit/receive format and frame length chr pe stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 s 8-bit data stop 0 0 1 s 8-bit data stop stop 0 1 0 s 8-bit data p stop 0 1 1 s 8-bit data p stop stop 1 0 0 s 7-bit data stop 1 0 1 s 7-bit data stop stop 1 1 0 s 7-bit data p stop 1 1 1 s 7-bit data p stop stop legend: s: start bit stop: stop bit p: parity bit clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck2 pin can be selected as th e scif's serial clock, according to the setting of the cke1 bit in scscr2. for details of scif clock source selection, see table 16.4. when an external clock is input at the sck2 pin, the clock frequency should be 16 times the bit rate used.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 760 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 data transfer operations scif initialization: before transmitting and receiving data, it is necessary to clear the te and re bits in scscr2 to 0, then initialize the scif as described below. when the transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, sctsr2 is initialized. note that clearing the te and re bits to 0 does not change the contents of scfsr2, scftdr2, or scfrdr2. the te bit should be cleared to 0 after all transmit data has been sent and the tend flag in scfsr2 has been set. tend can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state afte r the clearance. before setting te again to start transmission, the tfrst bit in scfcr2 should first be set to 1 to reset scftdr2. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 761 of 1076 sep 24, 2013 figure 16.6 shows a sample scif initialization flowchart. initialization clear te and re bits in scscr2 to 0 set tfrst and rfrst bits in scfcr2 to 1 set cke1 bit in scscr2 (leaving te and re bits cleared to 0) set transmit/receive format in scsmr2 set value in scbrr2 1-bit interval elapsed? set rtrg1?0, ttrg1?0, and mce bits in scfcr2 clear tfrst and rfrst bits to 0 set te and re bits in scscr2 to 1, and set rie, tie, and reie bits end wait no yes 1. set the clock selection in scscr2. be sure to clear bits rie and tie, and bits te and re, to 0. 2. set the transmit/receive format in scsmr2. 3. write a value corresponding to the bit rate into scbrr2. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr2 to 1. also set the rie, reie, and tie bits. setting the te and re bits enables the txd2 and rxd2 pins to be used. when transmitting, the scif will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. figure 16.6 sample scif initialization flowchart
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 762 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 serial data transmission: figure 16.7 shows a sample flow chart for serial transmission. use the following procedure for serial data transmission after enabling the scif for transmission. start of transmission read tdfe fla g in scfsr2 tdfe = 1 ? write transmit data (16 - transmit tri gg er set number) to scftdr2, read 1 from tdfe fla g and tend fla g in scfsr2, then clear to 0 all data transmitted ? read tend fla g in scfsr2 tend = 1 ? break output ? clear spb2dt to 0 and set spb2io to 1 clear te bit in scscr2 to 0 end of transmission no yes no yes no yes no yes 1. scif status check and transmit data write: read scfsr2 and check that the tdfe fla g is set to 1, then write transmit data to scftdr2, read 1 from the tdfe and tend fla g s, then clear these fla g s to 0. the number of transmit data bytes that can be written is 16 - (transmit tri gg er set number). 2. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe fla g to confirm that writin g is possible, then write data to scftdr2, and then clear the tdfe fla g to 0. 3. break output at the end of serial transmission: to output a break in serial transmission, clear the spb2dt bit to 0 and set the spb2io bit to 1 in scsptr2, then clear the te bit in scscr2 to 0. in steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr2 indicated by the upper 8 bits of scfdr2. figure 16.7 sample serial transmission flowchart
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 763 of 1076 sep 24, 2013 in serial transmission, the scif operates as described below. 1. when data is written into scftdr2, the sc if transfers the data fr om scftdr2 to sctsr2 and starts transmitting. confirm that the tdfe flag in the serial status re gister (scfsr2) is set to 1 before writing transmit data to scftdr2. th e number of data bytes that can be written is at least 16 - transmit trigger setting. 2. when data is transferred from scftdr2 to sctsr2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr2. when the number of transmit data bytes in scftdr2 falls to or below the transmit trigger number set in the fifo control register (scfcr2), the tdfe flag is set. if the tie bit in scscr2 is set to 1 at this time, a transmit-fi fo-data-empty interrupt (txi) request is generated. the serial transmit data is sent from the txd2 pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output. (a format in which a parity bit is not output can also be selected.) d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the scif checks the scftdr2 transmit data at the timing for sending the stop bit. if data is present, the data is transferred from scftdr2 to sctsr2, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scfsr2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 764 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 16.8 shows an example of the operation for transmission in asynchronous mode. 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 tdfe tend serial data start bit data parity bit stop bit start bit idle state (mark state) data parity bit stop bit txi interrupt request data written to scftdr2 and tdfe fla g read as 1 then cleared to 0 by txi interrupt handler one frame txi interrupt request figure 16.8 example of transmit operation (example with 8-bit data, parity, one stop bit) 4. when modem control is enabled, transmission can be stopped and rest arted in accordance with the cts2 input value. when cts2 is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. when cts2 is set to 0, the next transmit data is output starting from the start bit. figure 16.9 shows an example of the operation when modem control is used. serial data txd2 0 d0 d1 d7 0/1 0 1 d0 d1 d7 0/1 c t s2 drive hi g h before stop bit start bit parity bit stop bit start bit figure 16.9 example of op eration using modem control ( cts2 )
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 765 of 1076 sep 24, 2013 serial data reception: figure 16.10 shows a sample fl owchart for serial reception. use the following procedure for serial data r eception after enabling th e scif for reception. start of reception read er, dr, brk fla g s in scfsr2 and orer fla g in sclsr2 er or dr or brk or orer = 1 ? read rdf fla g in scfsr2 rdf = 1 ? read receive data in scfrdr2, and clear rdf fla g in scfsr2 to 0 all data received ? clear re bit in scscr2 to 0 end of reception yes no yes yes no no error handlin g 1. receive error handlin g and break detection: read the dr, er, and brk fla g s in scfsr2, and the orer fla g in sclsr2, to identify any error, perform the appropriate error handlin g , then clear the dr, er, brk, and orer fla g s to 0. in the case of a framin g error, a break can also be detected by readin g the value of the rxd2 pin. 2. scif status check and receive data read : read scfsr2 and check that rdf = 1, then read the receive data in scfrdr2, read 1 from the rdf fla g , and then clear the rdf fla g to 0. the transition of the rdf fla g from 0 to 1 can also be identified by an rxi interrupt. 3. serial reception continuation procedure: to continue serial reception, read at least the receive tri gg er set number of receive data bytes from scfrdr2, read 1 from the rdf fla g , then clear the rdf fla g to 0. the number of receive data bytes in scfrdr2 can be ascertained by readin g the lower bits of scfdr2. figure 16.10 sample serial reception flowchart (1)
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 766 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 error handlin g receive error handlin g er = 1 ? brk = 1 ? break handlin g dr = 1 ? read receive data in scfrdr2 clear dr, er, brk fla g s in scfsr2, and orer fla g in sclsr2, to 0 end yes yes yes no overrun error handlin g orer = 1 ? yes no no no 1. whether a framin g error or parity error has occurred that is to be read from scfrdr2 can be ascertained from the fer and per bits in scfsr2. 2. when a break si g nal is received, receive data is not transferred to scfrdr2 while the brk fla g is set. however, note that the last data in scfrdr2 is h'00 (the break data in which a framin g error occurred is stored). figure 16.10 sample serial reception flowchart (2)
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 767 of 1076 sep 24, 2013 in serial reception, the scif operates as described below. 1. the scif monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr2 in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. a. stop bit check: the scif checks whether the st op bit is 1. if there are two stop bits, only the first is checked. b. the scif checks whether receive data can be transferred from the receive shift register (scrsr2) to scfrdr2. c. overrun error check: the scif checks that th e orer flag is 0, indi cating that no overrun error has occurred. d. break check: the scif checks that the brk fl ag is 0, indicating that the break state is not set. if b, c, and d checks are passed, the r eceive data is stored in scfrdr2. note: reception continues when par ity error, framing error occurs. 4. if the rie bit in scscr2 is set to 1 when the rdf or dr fl ag changes to 1, a receive-fifo- data-full interrupt (rxi) request is generated. if the rie bit or reie bit in scs cr2 is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the rie bit or reie bit in scscr2 is set to 1 when the brk or orer flag changes to 1, a break reception interrupt (br i) request is generated.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 768 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 figure 16.11 shows an example of the operation for reception in asynchronous mode. 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0/1 0 rdf fer serial data start bit data parity bit stop bit start bit data parity bit stop bit rxi interrupt request one frame data read and rdf fla g read as 1 then cleared to 0 by rxi interrupt handler eri interrupt request g enerated by receive error figure 16.11 example of scif receive operation (example with 8-bit data, parity, one stop bit) 5. when modem control is enabled, the rts2 signal is output when scfrdr2 is empty. when rts2 is 0, reception is possible. SH7750: when rts2 is 1, this indicates that scfrdr2 contains 15 or more bytes of data. SH7750s, SH7750r: when rts2 is 1, this indicates that scfrdr2 contains a number of data bytes equal to or greater than the rts2 output active trigger set number. the rts2 output active trigger value is specified by bits 10 to 8 in the fifo control register (scfcr2), described in section 16.2.9, fifo control register (scfcr2). rts2 also becomes 1 when bit 4 (re) in scscr2 is 0.
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 769 of 1076 sep 24, 2013 figure 16.12 shows an example of the operation when modem control is used. d0 d1 d2 d7 0/1 1 0 0 r t s2 serial data rxd2 start bit parity bit stop bit start bit figure 16.12 example of op eration using modem control ( rts2 ) 16.4 scif interrupt sources and the dmac the scif has four interrupt sour ces: transmit-fifo-data-empty in terrupt (txi) request, receive- error interrupt (eri) requ est, receive-fifo-data-full interrupt (rxi) request, and break interrupt (bri) request. table 16.6 shows the interrupt sources and their order of priority. the interrupt sources are enabled or disabled by means of the tie, rie, and reie bits in scscr2. a separate interrupt request is sent to the interrupt contro ller for each of these interrupt sources. when transmission/reception is carried out using the dmac, output of interrupt requests to the interrupt controller can be inhibited by clearing the rie bit in scscr2 to 0. by setting the reie bit to 1 while the rie bit is cleared to 0, it is possible to output eri and bri interrupt requests, but not rxi interrupt requests. when the tdfe flag in the serial status register (scfsr2) is set to 1, a transmit-fifo-data-empty request is generated separately from the interrupt request. a transmit-fifo-data-empty request can activate the dmac to perform data transfer. when the rdf flag or dr flag in scfsr2 is set to 1, a receive-fifo -data-full request is generated separately from the interrupt request. a receive-fifo-data-full request can activate the dmac to perform data transfer. when using the dmac for transmission/reception, set and enable the dmac before making the scif settings. see section 14, direct memory access controller (dmac) , for details of the dmac setting procedure.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 770 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 when the brk flag in scfsr2 or the orer flag in the line status register (sclsr2) is set to 1, a bri interrupt request is generated. the txi interrupt indicates that transmit data can be written, and the rxi interrupt indicates that there is receive data in scfrdr2. table 16.6 scif interrupt sources interrupt source description dmac activation priority on reset release eri interrupt initiated by receive error flag (er) not possible high rxi interrupt initiated by receive fifo data full flag (rdf) or receive data ready flag (dr) possible bri interrupt initiated by break flag (brk) or overrun error flag (orer) not possible txi interrupt initiated by transmit fifo data empty flag (tdfe) possible low see section 5, exceptions, for priorities and the relationship with non-scif interrupts. 16.5 usage notes note the following when using the scif. scftdr2 writing and the tdfe flag: the tdfe flag in the serial status register (scfsr2) is set when the number of transmit data bytes writte n in the transmit fifo data register (scftdr2) has fallen to or below the transmit trigger number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr2). after tdfe is set, transmit data up to the number of empty bytes in scftdr2 can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr2 is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 agai n after being read as 1 and cleared to 0. tdfe clearing should therefore be carri ed out when scftdr2 contains mo re than the transmit trigger number of transmit data bytes. the number of transmit data bytes in scftdr2 can be found from the upper 8 bits of the fifo data count register (scfdr2). scfrdr2 reading and the rdf flag: the rdf flag in the serial status register (scfsr2) is set when the number of receive data bytes in the receive fifo data register (scfrdr2) has become equal to or greater than the receive tri gger number set by bits rtrg1 and rtrg0 in the
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 771 of 1076 sep 24, 2013 fifo control register (scfcr2). after rdf is set, receive data equivalent to the trigger number can be read from scfrdr2, allowi ng efficient cont inuous reception. however, if the number of data bytes in scfrdr2 is equal to or greater than the trigger number, the rdf flag will be set to 1 again if it is cleared to 0. rdf should therefore be cleared to 0 after being read as 1 after all the receive data has been read. the number of receive data bytes in scfrdr2 ca n be found from the lower 8 bits of the fifo data count register (scfdr2). break detection and processing: break signals can be detected by reading the rxd2 pin directly when a framing error (fer) is detected. in the brea k state the input from the rxd2 pin consists of all 0s, so the fer flag is set and the pa rity error flag (per) may also be set. although the scif stops tr ansferring receive data to scfrdr2 after receiving a break, the receive operation continues. sending a break signal: the input/output condition and level of the txd2 pin are determined by bits spb2io and spb2dt in the serial port register (scsptr2). this feature can be used to send a break signal. after the serial transmitter is initialized, the txd2 pin function is not selected and the value of the spb2dt bit substitutes for the mark state until the te bit is set to 1 (i.e. transmission is enabled). the spb2io and spb2dt bits should therefore be set to 1 (designating output and high level) beforehand. to send a break signal during serial transmissi on, clear the spb2dt bit to 0 (designating low level), then clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized, regardless of its curren t state, and 0 is output from the txd2 pin. receive data sampling timi ng and receive margin: the scif operates on a base clock with a frequency of 16 times the transfer rate. in reception, the scif synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 16.13.
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 772 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 d0 d1 16 clocks 8 clocks base clock receive data (rxd2) start bit ?7.5 clocks +7.5 clocks synchronization samplin g timin g data samplin g timin g figure 16.13 receive data sampling timing in asynchronous mode the receive margin in asynchron ous mode can therefore be expres sed as shown in equation (1). m = (0.5 ? ) ? (l ? 0.5) f ? (1 + f) 100 % 1 2n | d ? 0.5 | n ...................... (1) m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875 % , as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 1 / (2 16)) 100 % = 46.875 % ................................................ (2) this is a theoretical value. a reasonable margin to allow in system designs is 20 % to 30 % .
SH7750, SH7750s, SH7750r group section 16 serial communication interface with fifo (scif) r01uh0456ej0702 rev. 7.02 page 773 of 1076 sep 24, 2013 sck2/ mreset : as the manual reset pin is multiplexed with the sck2 pin, a manual reset must not be executed while the scif is operating in external clock mode. when using the dmac: when using the dmac for transmission/reception, inhibit output of rxi and txi interrupt requests to the interrupt cont roller. if interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the dmac without regard to the interrupt handler. serial ports: note that, when the scif pin value is read using a serial port, the value read will be the value two peripheral clock cycles earlier. overrun error flag (SH7750): scif overrun error flag is not set in the case that overrun error and flaming error occurred simulta neously in receiving data, that means 17th byte data which overrun was accompanying with fl aming error. in such case, only scfsr2. er flag which shows occurrence of flaming error is set. receive fifo stores data received before the overrun and does not store (i. e. lose) overrun data. scif has no bit which corresponds to scfsr2. fer for the lost data. in addition to the overrun error handling software routine, exception handler should check co- occurrence of overrun error when a flaming error is occurred and when a co-occurrence is found, it should handle also overrun error (when (i) a overrun error sole ly occurred without accompanying with other r eceive error and (ii) when a parity error is accompanied with overrun error, usual overrun error handling can be used. overrun error handling should rather be done primarily).
section 16 serial communication interface with fifo (scif) SH7750, SH7750s, SH7750r group page 774 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 read receive fifo last data ? no no yes yes normal error handlin g error handlin g no yes overrun error handlin g + framin g error handlin g framin g error occurrence flow c hart: when flamin g error (scfsr.er=1) is occurred, bit7 to bit0 should be read out from scfdr2. if bit7 to bit0 equals h'10, contents of the receive fifo should be read. when the data received last is not accompanied with flamin g error (scfsr2.fer=0) both overrun error handlin g and flamin g error handlin g shoud be conducted. bits 7 to 0 in scfdr2 = h'10 ? per or fer bit in scfsr2 set to 1 ? figure 16.14 overrun error flag
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 775 of 1076 sep 24, 2013 section 17 smart card interface 17.1 overview the serial communication interface (sci) supports a subset of the iso/iec 7816-3 (identification cards) standard as an extended function. switching between the normal serial communication interface an d the smart card interface is carried out by means of a register setting. 17.1.1 features features of the smart card interface are listed below. ? asynchronous mode ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (p arity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported ? on-chip baud rate generator allows any bit rate to be selected ? three interrupt sources there are three interrupt source s?transmit-data-empty, receive-da ta-full, and transmit/receive error?that can issue requests independently. the transmit-data-empty inte rrupt and receive-dat a-full interrupt can activate the dma controller (dmac) to execute data transfer.
section 17 smart card interface SH7750, SH7750s, SH7750r group page 776 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 17.1.2 block diagram figure 17.1 shows a block diagram of the smart card interface. module data bus scrdr1 scrsr1 rxd txd sck sctdr1 sctsr1 scscmr1 scssr1 scscr1 scbrr1 parity generation parity check transmission/ reception control baud rate generator clock external clock pck pck/4 pck/16 pck/64 txi rxi eri sci bus interface internal data bus scsmr1 legend: scscmr1: smart card mode register scrsr1: receive shift register scrdr1: receive data register sctsr1: transmit shift register sctdr1: transmit data register scsmr1: serial mode register scscr1: serial control register scssr1: serial status register scbrr1: bit rate register scsptr1: serial port register scsptr1 figure 17.1 block diagram of smart card interface
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 777 of 1076 sep 24, 2013 17.1.3 pin configuration table 17.1 shows the smart card interface pin configuration. table 17.1 smart card interface pins pin name abbreviation i/o function serial clock pin md0/ sck i/o clock input/output receive data pin rxd i nput receive data input transmit data pin md7/txd ou tput transmit data output note: the serial clock pin and transmit data pin function as mode input pins md0 and md7 after a power-on reset. 17.1.4 register configuration the smart card interface has the internal regist ers shown in table 17.2. details of the scbrr1, sctdr1, scrdr1, and scsptr1 registers are the sa me as for the normal sci function: see the register descriptions in section 15, serial communication interface (sci). with the exception of the serial port register, the smart card inte rface registers are initialized in standby mode and in the module standby state as well as by a power-on reset or manual reset. when recovering from standby mode or the module standby state, the registers must be set again. table 17.2 smart card interface registers name abbreviation r/w initial value p4 address area 7 address access size serial mode register scsmr1 r/w h'00 h'ffe00000 h'1fe00000 8 bit rate register scbrr1 r/w h'ff h'ffe00004 h'1fe00004 8 serial control register scs cr1 r/w h'00 h'ffe00008 h'1fe00008 8 transmit data register sctdr1 r/w h'ff h'ffe0000c h'1fe0000c 8 serial status register scssr1 r/(w) * 1 h'84 h'ffe00010 h'1fe00010 8 receive data register scrdr 1 r h'00 h'ffe00014 h'1fe00014 8 smart card mode register scscmr1 r/w h'00 h'ffe00018 h'1fe00018 8 serial port register scsptr1 r/w h'00 * 2 h'ffe0001c h'1fe0001c 8 notes: 1. only 0 can be written, to clear flags. 2. the value of bits 2 and 0 is undefined.
section 17 smart card interface SH7750, SH7750s, SH7750r group page 778 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 17.2 register descriptions only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 smart card mode register (scscmr1) scscmr1 is an 8-bit readable/writable register that selects the smart card interface function. scscmr1 is initialized to h'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. bit: 7 6 5 4 3 2 1 0 ? ? ? ? sdir sinv ? smif initial value: ? ? ? ? 0 0 ? 0 r/w: ? ? ? ? r/w r/w ? r/w bits 7 to 4 and 1?reserved: these bits are always read as 0, and should only be written with 0. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3: sdir description 0 sctdr1 contents are transmitted lsb-first (initial value) receive data is stored in scrdr1 lsb-first 1 sctdr1 contents are transmitted msb-first receive data is stored in scrdr1 msb-first bit 2?smart card data invert (sinv): specifies inversion of the data logic level. this function is used together with the bit 3 function for communication with an inverse convention card. the sinv bit does not affect the logic level of the parity bit. for parity-related setting procedures, see section 17 .3.4, register settings. bit 2: sinv description 0 sctdr1 contents are transmitted as they are (initial value) receive data is stored in scrdr1 as it is 1 sctdr1 contents are inve rted before being transmitted receive data is stored in scrdr1 in inverted form
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 779 of 1076 sep 24, 2013 bit 0?smart card interface mode select (smif): enables or disables the smart card interface function. bit 0: smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled 17.2.2 serial mode register (scsmr1) bit 7 of scsmr1 has a different fu nction in smart card interface mode. bit: 7 6 5 4 3 2 1 0 gm(c/ a ) chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?gsm mode (gm): sets the smart card interface function to gsm mode. with the normal smart card interface, this bit is cleared to 0. setting this bit to 1 selects gsm mode, an additional mode for controlling the timing for setting the tend flag that indicates completion of transmission, and the type of clock output used. the details of the additional clock output control mode are specified by the cke1 and cke0 bits in the serial control register (scscr1). in gsm mode, the pulse width is guar anteed when sck start/stop specifications are made by cke1 and cke0. bit 7: gm description 0 normal smart card interface mode operation (initial value) ? the tend flag is set 12.5 etu afte r the beginning of the start bit ? clock output on/off control only 1 gsm mode smart card interface mode operation ? the tend flag is set 11.0 etu afte r the beginning of the start bit ? clock output on/off and fixed-high/fixed-low control (set in scscr1) note: etu: elementary time unit (time for transfer of 1 bit) bits 6 to 0: operate in the same way as for the normal sci. see section 15, serial communication interface (sci), for details. with the smart card interf ace, the following settings should be used: chr = 0, pe = 1, stop = 1, mp = 0.
section 17 smart card interface SH7750, SH7750s, SH7750r group page 780 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 17.2.3 serial control register (scscr1) bits 1 and 0 of scscr1 have a differ ent function in smart card interface mode. bit: 7 6 5 4 3 2 1 0 tie rie te re ? ? cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 7 to 4: operate in the same way as for the normal sci. see section 15, serial communication interface (sci), for details. bits 3 and 2?reserved: not used with the smart card interface. bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits specify the function of the sck pin. in smart card interface mode, an internal cloc k is always used as the clock source. in smart card interface mode, it is po ssible to specify a fixed high leve l or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. gm cke1 cke0 sck pin function 0 0 0 port i/o pin 1 clock output as sck output pin 1 0 invalid setting: must not be used 1 invalid setting: must not be used 1 0 0 output pin with output fixed low 1 clock output as output pin 1 0 output pin with output fixed high 1 clock output as output pin
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 781 of 1076 sep 24, 2013 17.2.4 serial status re gister (scssr1) bit 4 of scssr1 has a different function in sm art card interface mode. coupled with this, the setting conditions for bit 2 (tend) are also different. bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer/ ers per tend ? ? initial value: 1 0 0 0 0 1 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only 0 can be written, to clear the flag. bits 7 to 5: operate in the same way as for the normal sci. see section 15, serial communication interface (sci), for details. bit 4?error signal status (ers): in smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving side during transmission . framing errors are not detected in smart card interface mode. bit 4: ers description 0 normal reception, no error signal (initial value) [clearing conditions] ? power-on reset, manual reset, standby mode, or module standby ? when 0 is written to ers after reading ers = 1 1 an error signal has been sent from the receiving side indicating detection of a parity error [setting condition] when the low level of the error signal is detected note: clearing the te bit in scscr1 to 0 does not affect the ers flag, which retains its previous state. bit 3?parity error (per): operates in the same way as fo r the normal sci. see section 15, serial communication interface (sci), for details.
section 17 smart card interface SH7750, SH7750s, SH7750r group page 782 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 2?transmit end (tend): the setting conditions for the tend flag are as follows. bit 2: tend description 0 transmission in progress [clearing condition] when 0 is written to tdre after reading tdre = 1 1 transmission has been ended (initial value) [setting conditions] ? power-on reset, manual reset, standby mode, or module standby ? when the te bit in scscr1 is 0 and the fer/ers bit is also 0 ? when the gm bit in scsmr1 is 0, and tdre = 1 and fer/ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character ? when the gm bit in scsmr1 is 1, and tdre = 1 and fer/ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character note: etu: elementary time unit (time for transfer for 1 bit) bits 1 and 0?reserved: not used with the sm art card interface. 17.3 operation 17.3.1 overview the main functions of the smart card interface are as follows. ? one frame consists of 8-bit data plus a parity bit. ? in transmission, a guard time of at least 2 etu (e lementary time unit: the time for transfer of one bit) is left between the end of the par ity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for a 1-etu period 10.5 etu after the start bit. ? if an error signal is detected during transmissi on, the same data is transmitted automatically after the elapse of 2 etu or longer. ? only asynchronous communication is supported; there is no synchronous communication function.
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 783 of 1076 sep 24, 2013 17.3.2 pin connections figure 17.2 shows a schematic diagram of smart card interface related pin connections. in communication with an ic card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected outside the chip. the data transmission line should be pulled up on the v cc power supply side with a resistor. when the clock generated on the smart card interface is used by an ic card , the sck pin output is input to the clk pin of the ic card. no connection is needed if the ic card us es an internal clock. chip port output is used as the reset signal. other pins must normally be connected to the power supply or ground. note: if an ic card is not connected, and both te and re are set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. SH7750 SH7750s SH7750r connected equipment txd rxd sck px (port) data line clock line reset line io clk rst ic card v cc figure 17.2 schematic diagram of smart card interface pin connections
section 17 smart card interface SH7750, SH7750s, SH7750r group page 784 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 17.3.3 data format figure 17.3 shows the smart card in terface data format. in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmi ssion of the data. if an error signal is detected during transmission, the same data is retransmitted. ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds d0 d1 d2 d3 d4 d5 d6 d7 dp de ds: start bit d0?d7: data bits dp: parity bit de: error si g nal when there is no parity error when a parity error occurs transmittin g station output transmittin g station output receivin g station output figure 17.3 smart card interface data format the operation sequence is as follows. 1. when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. 2. the transmitting station starts transmission of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). 3. with the smart card interface, the data line then returns to th e high-impedance state. the data line is pulled high with a pull-up resistor. 4. the receiving station car ries out a parity check. if there is no parity error and the data is r eceived normally, the receiving station waits for reception of the next data.
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 785 of 1076 sep 24, 2013 if a parity error occurs, however, the receiving station outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving station places the signa l line in the high-imped ance state again. the signal line is pulled high again by a pull-up resistor. 5. if the transmitting station does not receive an erro r signal, it proceeds to transmit the next data frame. if it receives an error signal, however, it return s to step 2 and retransmits the erroneous data. 17.3.4 register settings table 17.3 shows a bit map of the registers used by the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described below. table 17.3 smart card interface register settings bit register bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 scsmr1 gm 0 1 o/ e 1 0 cks1 cks0 scbrr1 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scscr1 tie rie te re 0 0 cke1 cke0 sctdr1 tdr7 tdr6 tdr5 t dr4 tdr3 tdr2 tdr1 tdr0 scssr1 tdre rdrf orer fer/ers per tend 0 0 scrdr1 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scscmr1 ? ? ? ? sdir sinv ? smif scsptr1 eio ? ? ? spb1io spb1dt spb0io spb0dt note: a dash indicates an unused bit. serial mode register (scsmr1) settings: the gm bit is used to select the timing of tend flag setting, and, together with the cke1 and cke0 bits in the serial control register (scscr1), to select the clock output state. the o/ e bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the on-chip baud rate generator. see section 17.3.5, clock.
section 17 smart card interface SH7750, SH7750s, SH7750r group page 786 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 i/o data txi (tend interrupt) note: etu: elementary time unit (time for transfer for 1 bit) guard time ds da db dc dd de df d g dh dp de 12.5 etu 11.0 etu gm = 0 gm = 1 figure 17.4 tend generation timing bit rate register (scbrr1) setting: scbrr1 is used to set the bit rate. see section 17.3.5, clock, for the method of calculating the value to be set. serial control regist er (scscr1) settings: the function of the tie, rie, te, and re bits is the same as for the normal sci. see section 15, serial communication inte rface (sci), for details. the cke1 and cke0 bits specify the clock output state. see section 17.3.5, clock, for details. smart card mode register (scscmr1) settings: the sdir bit and sinv bit are both cleared to 0 if the ic card is of the direct convention t ype, and both set to 1 if of the inverse convention type. the smif bit is set to 1 when the smart card interface is used. figure 17.5 shows examples of register settings an d the waveform of the start character for the two types of ic card (direct convention and inverse convention). with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first orde r. the start character data in this case is h'3b. the parity bit is 1 since even parity is stipulated for the smart card. with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first orde r. the start character data in this case is h'3f. the parity bit is 0, corresponding to state z, sin ce even parity is stipul ated for the smart card.
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 787 of 1076 sep 24, 2013 inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in scsmr1 is set to odd parity mode. (this applies to both transmission and reception). (z) (a) direct convention (sdir = sinv = o/ e = 0) (b) inverse convention (sdir = sinv = o/ e = 1) a z z a z z z a a z (z) state ds d0 d1 d2 d3 d4 d5 d6 d7 dp (z) a z z a a a a a a z (z) state ds d7 d6 d5 d4 d3 d2 d1 d0 dp figure 17.5 sample start character waveforms 17.3.5 clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for th e smart card interface. the bit rate is set with the bit rate register (scbrr1) and the cks1 and cks0 bits in the serial mode register (scsmr1). the equation for calculating the bit rate is shown below. table 17.5 shows some sample bit rates. if clock output is selected with cke0 set to 1, a clock with a frequency of 372 times the bit rate is output from the sck pin. b = 10 6 1488 2 2n ? 1 (n + 1) pck where: n = value set in scbrr1 (0 n 255) b = bit rate (bits/s) pck = peripheral module operating frequency (mhz) n = 0 to 3 (see table 17.4)
section 17 smart card interface SH7750, SH7750s, SH7750r group page 788 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 17.4 values of n and corres ponding cks1 and cks0 settings n cks1 cks0 0 0 0 1 0 1 2 1 0 3 1 1 table 17.5 examples of bit rate b (bits/s) for various scbrr1 settings (when n = 0) pck (mhz) n 7.1424 10.00 10.7136 14.2848 25.0 33.0 50.0 0 9600.0 13440.9 14400.0 192 00.0 33602.2 44354.8 67204.3 1 4800.0 6720.4 7200.0 960 0.0 16801.1 22177.4 33602.2 2 3200.0 4480.3 4800.0 640 0.0 11200.7 14784.9 22401.4 note: bit rates are rounded to one decimal place. the method of calculating the value to be set in the bit rate register (scbrr1) from the peripheral module operating frequency and bit rate is shown below. here, n is an integer in the range 0 n 255, and the smaller error is specified. n = 10 6 ? 1 1488 2 2n ? 1 b pck table 17.6 examples of scbrr1 settings for bit rate b (bits/s) (when n = 0) pck (mhz) 7.1424 10.00 10.7136 14.2848 25.00 33.00 50.00 bits/s n error n error n error n error n error n error n error 9600 0 0.00 1 30.00 1 25.00 1 8.99 3 14.27 4 8.22 6 0.01
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 789 of 1076 sep 24, 2013 table 17.7 maximum bit rate at various frequencies (smart card interface mode) pck (mhz) maximum bit rate (bits/s) n n 7.1424 19200 0 0 10.00 26882 0 0 10.7136 28800 0 0 16.00 43010 0 0 20.00 53763 0 0 25.0 67204 0 0 30.0 80645 0 0 33.0 88710 0 0 50.0 67204 0 0 the bit rate error is given by the following equation: error ( % ) = 1488 2 2n ? 1 b (n + 1) 10 6 ? 1 100 pck table 17.8 shows the relationship between the smar t card interface transmit/receive clock register settings and the output state. table 17.8 register setti ngs and sck pin state register values sck pin setting smif gm cke1 cke0 output state 1 * 1 1 0 0 0 port determined by setting of spb1io and spb1dt bits in scsptr1 1 0 0 1 sck (serial clock) output state 2 * 2 1 1 0 0 low output low-level output state 1 1 0 1 sck (serial clock) output state 3 * 2 1 1 1 0 high output high-level output state 1 1 1 1 sck (serial clock) output state notes: 1. the sck output state changes as soon as the cke0 bit setting is changed. clear the cke1 bit to 0. 2. stopping and starting the clock by changi ng the cke0 bit setting does not affect the clock duty cycle.
section 17 smart card interface SH7750, SH7750s, SH7750r group page 790 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 port value width is undefined cke1 value specified width sck sck (a) when gm = 0 (b) when gm = 1 width is undefined specified width port value cke1 value figure 17.6 difference in clock ou tput according to gm bit setting 17.3.6 data transmit/receive operations initialization: before transmitting and receiving data, th e smart card interface must be initialized as described below. initialization is also necessary when switching from tr ansmit mode to receive mode, or vice versa. figure 17.7 shows a sample initialization processing flowchart. 1. clear the te and re bits in the se rial control register (scscr1) to 0. 2. clear error flags fer/ers, per, and orer in the serial status regi ster (scssr1) to 0. 3. set the gm bit, parity bit (o/ e ), and baud rate generator select bits (cks1 and cks0) in the serial mode register (scsmr1). clear the chr and mp bits to 0, and set the stop and pe bits to 1. 4. set the smif, sdir, and sinv bits in the smart card mode register (scscmr1). when the smif bit is set to 1, the txd pin and rxd pin both go to the high-impedance state. 5. set the value corresponding to the bit rate in the bit rate register (scbrr1). 6. set the clock source select bits (cke1 and cke0) in scscr1. clear the tie, rie, te, re, mpie, and teie bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. 7. wait at least one bit interval, then set the tie, rie, te, and re bits in scscr1. do not set the te bit and re bit at the same tim e, except for self-diagnosis.
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 791 of 1076 sep 24, 2013 initialization clear te and re bits in scscr1 to 0 clear fer/ers, per, and orer fla g s in scscr1 to 0 in scsmr1, set parity in o/ e bit, clock in cks1 and cks0 bits, and set gm set smif, sdir, and sinv bits in scscmr1 set value in scbrr1 in scscr1, set clock in cke1 and cke0 bits, and clear tie, rie, te, re, mpie, and teie bits to 0. 1-bit interval elapsed? set tie, rie, te, and re bits in scscr1 end wait no yes 1 2 3 4 5 6 7 figure 17.7 sample initialization flowchart
section 17 smart card interface SH7750, SH7750s, SH7750r group page 792 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 serial data transmission: as data transmission in smart car d mode involves error signal sampling and retransmission pro cessing, the processing procedure is different from that for the normal sci. figure 17.8 shows a sample transmission processing flowchart. 1. perform smart card interface mode initialization as described in in itialization above. 2. check that the fer/ers error fl ag in scssr1 is cleared to 0. 3. repeat steps 2 and 3 until it can be confirmed that the tend flag in scssr1 is set to 1. 4. write the transmit data to sctdr1, clear th e tdre flag to 0, an d perform the transmit operation. the tend flag is cleared to 0. 5. to continue transmitting data, go back to step 2. 6. to end transmission, clear the te bit to 0. with the above processing, interrupt handling is possible. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrup t (txi) request will be generated. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transmit/receive-error in terrupt (eri) request will be generated. see interrupt operation in section 17.3.6 below for details.
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 793 of 1076 sep 24, 2013 start initialization start of transmission write transmit data to sctdr1, and clear tdre fla g in scssr1 to 0 fer/ers = 0? tend = 1? all data transmitted? fer/ers = 0? tend = 1? clear te bit in scscr1 to 0 end of transmission error handlin g error handlin g no yes yes yes yes no yes no no no 1 2 3 4 5 6 figure 17.8 sample transmission processing flowchart
section 17 smart card interface SH7750, SH7750s, SH7750r group page 794 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 serial data reception: data reception in smart card mode uses the same processi ng procedure as for the normal sci. figure 17.9 shows a sample reception processing flowchart. 1. perform smart card interface mode initialization as described in in itialization above. 2. check that the orer flag and per flag in scssr 1 are cleared to 0. if either is set, perform the appropriate receive error ha ndling, then clear both the or er and the per flag to 0. 3. repeat steps 2 and 3 until it can be confirmed that the rdrf flag is set to 1. 4. read the receive data from scrdr1. 5. to continue receiving data, clear the rdrf flag to 0 and go back to step 2. 6. to end reception, clear the re bit to 0. with the above processing, interrupt handling is possible. if reception ends and the rdrf flag is set to 1 wh ile the rie bit is set to 1 and interrupt requests are enabled, a receive-data-full in terrupt (rxi) request wi ll be generated. if an error occurs in reception and either the orer flag or the per flag is set to 1, a transmit/receive-error interrupt (eri) request will be generated. see interrupt operation in section 17.3.6 below for details. if a parity error occurs during reception and the per flag is set to 1, the received data is still transferred to scrdr1, and ther efore this data can be read.
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 795 of 1076 sep 24, 2013 start initialization start of reception read receive data from scrdr1 and clear rdrf fla g in scssr1 to 0 orer = 0 and per = 0? rdrf = 1? all data received? clear re bit in scscr1 to 0 end of reception error handlin g no yes yes yes no no 1 2 3 4 5 6 figure 17.9 sample recep tion processing flowchart mode switching operation: when switching fr om receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initi alization, clearing re to 0 and setting te to 1. the rdrf flag or the per and or er flags can be used to check that the receive operation has been completed. when switching from transmit mode to receive mo de, first confirm that th e transmit operation has been completed, then start from initialization, clearing te to 0 and setting re to 1. the tend flag can be used to check that the transmit operation has been completed.
section 17 smart card interface SH7750, SH7750s, SH7750r group page 796 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 interrupt operation: there are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (t xi) requests, transmit/receive-error interrupt (eri) requests, and receive-data-full interrupt (rxi) requests. the tran smit-end interrupt (tei) request cannot be used in this mode. when the tend flag in scssr1 is set to 1, a txi interrupt request is generated. when the rdrf flag in scssr1 is set to 1, an rxi interrupt request is generated. when any of flags orer, per, and fer/ers in scssr1 is set to 1, an eri interrupt request is generated. the relationship between the operating states and interrupt sources is shown in table 17.9. table 17.9 smart card mode operati ng states and interrupt sources operating state flag mask bit interrupt source transmit mode normal operation tend tie txi error fer/ers rie eri receive mode normal operation rdrf rie rxi error per, orer rie eri data transfer operation by dmac: in smart card mode, as with th e normal sci, transfer can be carried out using the dmac. in a transmit operation, when the tend flag in scssr1 is set to 1, a txi interrupt is requested. if the txi request is designated beforehand as a dmac activation source, the dmac will be activated by the txi reques t, and transfer of the transmit data will be carried out. the tend flag is auto matically cleared to 0 when data transfer is performed by the dmac. in the event of an error, the sci retransmits the same data automatically. the tend flag remains cleared to 0 during this time, and the dm ac is not activated. thus , the number of bytes specified by the sci and dmac are transmitted au tomatically, including retransmission following an error. however, the ers flag is not cleared automatically when an error occurs, and therefore the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. in a receive operation, an rxi interrupt request is generated when the rdrf flag in scssr1 is set to 1. if the rxi request is designated be forehand as a dmac activ ation source, the dmac will be activated by the rxi request, and transfer of the receive data will be carried out. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dmac. if an error occurs, an error flag is set but the rdrf flag is not. the dmac is not activated, but instead, an eri interrupt request is sent to the cpu. the error flag must therefore be cleared.
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 797 of 1076 sep 24, 2013 when performing data transfer using the dmac, it is essential to set and enable the dmac before carrying out sci settings. for details of the dmac setting procedures, see section 14, direct memory acce ss controller (dmac). 17.4 usage notes the following points should be noted when using the sci as a smart card interface. (1) receive data sampling timing and receive margin in asynchronous mode, the sci operates on a base clock with a frequency of 372 times the transfer rate. in reception, the sci synchronizes internally wi th the fall of the start bit, which it samples on the base clock. receive data is latched at the risi ng edge of the 186th base clock pulse. the timing is shown in figure 17.10. 0 185 371 0 185 371 0 base clock 372 clocks 186 clocks start bit d0 d1 receive data (rxd) synchronization samplin g timin g data samplin g timin g figure 17.10 receive data sampling timing in smart card mode
section 17 smart card interface SH7750, SH7750s, SH7750r group page 798 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 the receive margin in smart card mode can ther efore be expressed as shown in the following equation. m = (0.5 ? ) ? (l ? 0.5) f ? (1 + f) 100 % 1 2n | d ? 0.5 | n m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 372) d: clock duty cycle (d = 0 to 1.0) l: frame length (l =10) f: absolute deviation of clock frequency from the above equation, if f = 0 and d = 0.5, the receive margin is 49.866 % , as given by the following equation. when d = 0.5 and f = 0: m = (0.5 ? 1/2 372) 100 % = 49.866 % (2) retransfer operations retransfer operations are performed by the sci in receive mode and transm it mode as described below. retransfer operation when sci is in receive mode: figure 17.11 illustrates the retransfer operation when the sci is in receive mode. 1. if an error is found when the received parity bit is chec ked, the per bit in scssr1 is automatically set to 1. if the rie bit in scscr1 is enabled at this time, an eri interrupt request is generated. the per bit in scssr1 should be cleared to 0 before the next parity bit is sampled. 2. the rdrf bit in scssr1 is not set for a frame in which an error has occurred. 3. if an error is found when the received parity bit is checked, th e per bit in scssr1 is not set to 1. 4. if no error is found when the received parity b it is checked, the receive operation is judged to have been completed normally, and the rdrf bit in scssr1 is automatically set to 1. if the rie bit in scscr1 is enabled at this time, an rxi interrupt request is generated. 5. when a normal frame is received, the pin reta ins the high-impedance state at the timing for error signal transmission.
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 799 of 1076 sep 24, 2013 ds nth transfer frame retransferred frame transfer frame n+1 d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds ds d0 d0 d1 d1 d2 d2 de d3 d3 d4 d4 d5 d6 d7 dp rdrf per 1 2 3 4 5 figure 17.11 retransfer opera tion in sci receive mode retransfer operation when sci is in transmit mode: figure 17.12 illustrates the retransfer operation when the sci is in transmit mode. 1. if an error signal is sent back from the r eceiving side after transmi ssion of one frame is completed, the fer/ers bit in scssr1 is set to 1. if the rie bit in scscr1 is enabled at this time, an eri interrupt request is generated. the fer/ers bit in scssr1 should be cleared to 0 before the next parity bit is sampled. 2. the tend bit in scssr1 is not set for a frame for which an error signal indicating an error is received. 3. if an error signal is not sent back from the receiving side, the fer/ers bit in scssr1 is not set. 4. if an error signal is not sent back from the receiving side, transmission of one frame, including a retransfer, is judged to have been completed, and the tend bit in scssr1 is set to 1. if the tie bit in scscr1 is enabled at this tim e, a txi interrupt request is generated. tdre ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds ds d0 d0 d1 d1 d2 d2 de d3 d3 d4 d4 d5 d6 d7 dp tend fer/ers 2 4 1 transfer from sctdr1 to sctsr1 nth transfer frame retransferred frame transfer frame n+1 transfer from sctdr1 to sctsr1 transfer from sctdr1 to sctsr1 3 figure 17.12 retransfer operation in sci transmit mode
section 17 smart card interface SH7750, SH7750s, SH7750r group page 800 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (3) standby mode and clock when switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. switching from smart card int erface mode to standby mode: 1. set the sbp1io and sbp1dt bits in scsptr1 to the values for the fixed output state in standby mode. 2. write 0 to the te and re bits in the serial co ntrol register (scscr1) to stop transmit/receive operations. at the same time, set the cke1 bit to the value for the fixed output state in standby mode. 3. write 0 to the cke0 bit in scscr1 to stop the clock. 4. wait for one serial clock cycle. during this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. write h'00 to the serial mode register (scsmr1) and smart card mode register (scsmr1). 6. make the transition to the standby state. returning from standby mode to smart card interface mode: 7. clear the standby state. 8. set the cke1 bit in scscr1 to the value for the fixed output state at the start of standby (the current sck pin state). 9. set smart card interface mode and output the cl ock. clock signal generation is started with the normal duty cycle. normal operation normal operation standby mode 1 2 3 4 5 6 7 8 9 figure 17.13 procedure for stop ping and restarting the clock
SH7750, SH7750s, SH7750r group section 17 smart card interface r01uh0456ej0702 rev. 7.02 page 801 of 1076 sep 24, 2013 (4) power-on and clock the following procedure should be used to s ecure the clock duty cycle after powering on. 1. the initial state is port input and high impedance. use pull-up or pull-down resistors to fix the potential. 2. fix at the output specified by the cke1 bit in the serial control register (scscr1). 3. set the serial mode register (scsmr1) and smart card mode register (scscmr1), and switch to smart card mode operation. 4. set the cke0 bit in scscr1 to 1 to start clock output.
section 17 smart card interface SH7750, SH7750s, SH7750r group page 802 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 803 of 1076 sep 24, 2013 section 18 i/o ports 18.1 overview this lsi has a 20-bit general-purpose i/o port, sci i/o port, and scif i/o port. 18.1.1 features the features of the general-pu rpose i/o port are as follows: ? 20-bit i/o port with input/output direction independently specifiable for each bit ? pull-up can be specified in dependently for each bit. ? interrupt input is possible for 16 of the 20 i/o port bits. ? use or non-use of the i/o port can be selected with the porten bit in bus control register 2 (bcr2). the features of the sci i/o port are as follows: ? data can be output when the i/o port is designated for output and sci enabling has not been set. this allows break function transmission. ? the rxd pin value can be read at all times, allowing break state detection. ? sck pin control is possible when the i/o port is designated for output and sci enabling has not been set. ? the sck pin value can be read at all times. the features of the scif i/o port are as follows: ? data can be output when the i/o port is designated for output and scif enabling has not been set. this allows break function transmission. ? the rxd2 pin value can be read at all times, allowing break state detection. ? cts2 and rts2 pin control is possible when the i/o port is designated for output and scif enabling has not been set. ? the cts2 and rts2 pin values can be read at all times.
section 18 i/o ports SH7750, SH7750s, SH7750r group page 804 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 18.1.2 block diagrams figure 18.1 shows a block diagram of the 16-bit general-purpose i/o port. pbnpup porten dndir pbnio 0 1 pdtrw bck data input strobe d q c 0 1 0 1 mpx mpx mpx ptirenn bck c q d pull-up resistor port 15 (input / output)/d47 to port 0 (input/ output)/d32 dn output data internal bus dn input data interrupt controller porten 0: port not available 1: port available pbnpup 0: pull-up 1: pull-up off dndir 0: input 1: output pbnio 0: input 1: output ptirenn 0: interrupt input disabled 1: interrupt input enabled figure 18.1 16-bit port
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 805 of 1076 sep 24, 2013 figure 18.2 shows a block diagram of the 4-bit general-purpose i/o port. pbnpup porten dndir pbnio 0 1 pdtrw bck d q c 0 1 0 1 bck c q d mpx mpx mpx data input strobe pull-up resistor port 19 (input / output)/d51 to port 16 (input / output)/d48 dn output data internal bus porten 0: port not available 1: port available pbnpup 0: pull-up 1: pull-up off dndir 0: input 1: output pbnio 0: input 1: output dn input data figure 18.2 4-bit port
section 18 i/o ports SH7750, SH7750s, SH7750r group page 806 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 sci i/o port block diagrams are shown in figures 18.3 to 18.5. reset reset internal data bus sptrw sptrw sci r q d spb1io c r q d spb1dt c sptrr clock output enable si g nal serial clock output si g nal serial clock input si g nal clock input enable si g nal * md0/sck mode settin g re g ister le g end: sptrw: write to sptr sptrr: read sptr note: * si g nals that set the sck pin function as internal clock output or external clock input accordin g to the cke0 and cke1 bits in scscr1 and the c/ a bit in scsmr1. figure 18.3 md0/sck pin
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 807 of 1076 sep 24, 2013 reset internal data bus sptrw sci r q d spb0io c reset sptrw r q d spb0dt c md7/txd mode settin g re g ister transmit enable si g nal serial transmit data le g end: sptrw: write to sptr figure 18.4 md7/txd pin internal data bus sci rxd sptrr serial receive data le g end: read sptr figure 18.5 rxd pin
section 18 i/o ports SH7750, SH7750s, SH7750r group page 808 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 scif i/o port block diagrams are shown in figures 18.6 to 18.9. reset internal data bus sptrw mode settin g re g ister scif r q d spb2io c reset sptrw r q d spb2dt c md1/txd2 le g end: sptrw: write to sptr transmit enable si g nal serial transmit data figure 18.6 md1/txd2 pin internal data bus mode settin g re g ister scif md2/rxd2 sptrr serial receive data le g end: sptrr: read sptr figure 18.7 md2/rxd2 pin
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 809 of 1076 sep 24, 2013 reset internal data bus sptrw scif r q d ctsio c reset sptrr sptrw r q d ctsdt c cts2 le g end: sptrw: write to sptr sptrr: read sptr note: * mce bit in scfcr2: si g nal that desi g nates modem control as the cts2 pin function. modem control enable si g nal * cts2 si g nal figure 18.8 cts2 pin
section 18 i/o ports SH7750, SH7750s, SH7750r group page 810 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 reset internal data bus sptrw scif r q d rtsio c reset mode settin g re g ister sptrr sptrw r q d rtsdt c md8/ rts2 le g end: sptrw: write to sptr sptrr: read sptr note: * mce bit in scfcr2: si g nal that desi g nates modem control as the rts2 pin function. modem control enable si g nal * rts2 si g nal figure 18.9 md8/ rts2 pin
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 811 of 1076 sep 24, 2013 18.1.3 pin configuration table 18.1 shows the 20-bit general-purpose i/o port pin configuration. table 18.1 20-bit genera l-purpose i/o port pins pin name signal i/o function port 19 pin port19/d51 i/o i/o port port 18 pin port18/d50 i/o i/o port port 17 pin port17/d49 i/o i/o port port 16 pin port16/d48 i/o i/o port port 15 pin port15/d47 i/o * i/o port / gpio interrupt port 14 pin port14/d46 i/o * i/o port / gpio interrupt port 13 pin port13/d45 i/o * i/o port / gpio interrupt port 12 pin port12/d44 i/o * i/o port / gpio interrupt port 11 pin port11/d43 i/o * i/o port / gpio interrupt port 10 pin port10/d42 i/o * i/o port / gpio interrupt port 9 pin port9/d41 i/o * i/o port / gpio interrupt port 8 pin port8/d40 i/o * i/o port / gpio interrupt port 7 pin port7/d39 i/o * i/o port / gpio interrupt port 6 pin port6/d38 i/o * i/o port / gpio interrupt port 5 pin port5/d37 i/o * i/o port / gpio interrupt port 4 pin port4/d36 i/o * i/o port / gpio interrupt port 3 pin port3/d35 i/o * i/o port / gpio interrupt port 2 pin port2/d34 i/o * i/o port / gpio interrupt port 1 pin port1/d33 i/o * i/o port / gpio interrupt port 0 pin port0/d32 i/o * i/o port / gpio interrupt note: * when port pins are used as gpio interrupts, they must be set to input mode. the input setting can be made in the pctra register.
section 18 i/o ports SH7750, SH7750s, SH7750r group page 812 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 18.2 shows the sci i/o port pin configuration. table 18.2 sci i/o port pins pin name abbreviation i/o function serial clock pin md0/ sck i/o clock input/output receive data pin rxd i nput receive data input transmit data pin md7/txd ou tput transmit data output note: pins md0/sck and md7/txd function as mo de input pins md0 and md7 after a power-on reset. they are made to function as serial pins by performing sci operation settings with the te, re, ckei, and cke0 bits in scscr1 and the c/ a bit in scsmr1. break state transmission and detection can be performed by means of a setting in the sci's scsptr1 register. table 18.3 shows the scif i/o port pin configuration. table 18.3 scif i/o port pins pin name abbreviation i/o function serial clock pin mreset /sck2 input clock input receive data pin md2/rxd2 input receive data input transmit data pin md1/txd2 output transmit data output modem control pin cts2 i/o transmission enabled modem control pin md8/ rts2 i/o transmission request note: the mreset/sck2 pin functions as the mreset manual reset pin when a manual reset is executed. the md1/txd2, md2/rxd2, and md8/ rts2 pins function as the md1, md2, and md8 mode input pins after a power-on reset. these pins are made to function as serial pins by performing scif operation settings with the te and re bits in scscr2 and the mce bit in scfcr2. break state transmission and detec tion can be set in the scif's scsptr2 register.
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 813 of 1076 sep 24, 2013 18.1.4 register configuration the 20-bit general-purpose i/o port, sci i/o port , and scif i/o port have seven registers, as shown in table 18.4. table 18.4 i/o port registers name abbreviation r/w initial value * p4 address area 7 address access size port control register a pctra r/w h'00000000 h'ff80002c h'1f80002c 32 port data register a pdtra r/ w undefined h'ff 800030 h'1f800030 16 port control register b pctrb r/w h'00000000 h'ff800040 h'1f800040 32 port data register b pdtrb r/ w undefined h'ff 800044 h'1f800044 16 gpio interrupt control register gpioic r/w h'00000000 h'ff800048 h' 1f800048 16 serial port register scsptr1 r/ w undefined h'ffe0001c h'1fe0001c 8 serial port register scsptr2 r/w undefined h'ffe80020 h'1fe80020 16 note: * initialized by a power-on reset.
section 18 i/o ports SH7750, SH7750s, SH7750r group page 814 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 18.2 register descriptions 18.2.1 port control register a (pctra) port control register a (pctra) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port (port 15 pin to port 0 pin). as the initial value of port data register a (pdtra) is undefined, all the bits in the 16-bit port should be set to output with pctra after writing a value to the pdtra register. pctra is initialized to h'00000000 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. bit: 31 30 29 28 27 26 25 24 pb15pup pb15io pb14pup pb14io pb13pup pb13io pb12pup pb12io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 pb11pup pb11io pb10pup pb10io pb9pup pb9io pb8pup pb8io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 pb7pup pb7io pb6pup pb6io pb5pup pb5io pb4pup pb4io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pb3pup pb3io pb2pup pb2io pb1pup pb1io pb0pup pb0io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 815 of 1076 sep 24, 2013 bit 2n + 1 (n = 0?15)?port pull-up control (pbnpup): specifies whether each bit in the 16- bit port is to be pulled up with a built-in resistor. pull-up is automatically turned off for a port pin set to output by bit pbnio. bit 2n + 1: pbnpup description 0 bit m (m = 0?15) of 16-bit port is pulled up (initial value) 1 bit m (m = 0?15) of 16-bit port is not pulled up bit 2n (n = 0?15)?port i/o control (pbnio): specifies whether each bit in the 16-bit port is an input or an output. bit 2n: pbnio description 0 bit m (m = 0?15) of 16-bit port is an input (initial value) 1 bit m (m = 0?15) of 16-bit port is an output 18.2.2 port data register a (pdtra) port data register a (pdtra) is a 16-bit readable/w ritable register used as a data latch for each bit in the 16-bit port. when a bit is set as an output, the value written to the pdtra register is output from the external pin. when a value is read from the pdtra register while a bit is set as an input, the external pin value sampled on the external bus cl ock is read. when a bit is set as an output, the value written to the pdtra register is read. pdtra is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. bit: 15 14 13 12 11 10 9 8 pb15dt pb14dt pb13dt pb12dt pb11dt pb10dt pb9dt pb8dt initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 18 i/o ports SH7750, SH7750s, SH7750r group page 816 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 18.2.3 port control register b (pctrb) port control register b (pctrb) is a 32-bit readable /writable register that controls the input/output direction and pull-up for each bit in the 4-bit port (port 19 pin to port 16 pin). as the initial value of port data register b (pdtrb) is undefined, each bit in the 4-bit port should be set to output with pctrb after writing a value to the pdtrb register. pctrb is initialized to h'00000000 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 pb19pup pb19io pb18pup pb18io pb17pup pb17io pb16pup pb16io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 817 of 1076 sep 24, 2013 bit 2n + 1 (n = 0?3)?port pull-up control (pbnpup): specifies whether each bit in the 4-bit port is to be pulled up with a built-in resistor. pu ll-up is automatically turned off for a port pin set to output by bit pbnio. bit 2n + 1: pbnpup description 0 bit m (m = 16?19) of 4-bit port is pulled up (initial value) 1 bit m (m = 16?19) of 4-bit port is not pulled up bit 2n (n = 0?3)?port i/o control (pbnio): specifies whether each bit in the 4-bit port is an input or an output. bit 2n: pbnio description 0 bit m (m = 16?19) of 4-bit port is an input (initial value) 1 bit m (m = 16?19) of 4-bit port is an output 18.2.4 port data register b (pdtrb) port data register b (pdtrb) is a 16-bit readable/w ritable register used as a data latch for each bit in the 4-bit port. when a bit is set as an output, the value written to the pdtrb register is output from the external pin. when a value is read from the pdtrb register while a bit is set as an input, the external pin value sampled on the external bus cl ock is read. when a bit is set as an output, the value written to the pdtrb register is read. pdtrb is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? pb19dt pb18dt pb17dt pb16dt initial value: 0 0 0 0 ? ? ? ? r/w: r r r r r/w r/w r/w r/w
section 18 i/o ports SH7750, SH7750s, SH7750r group page 818 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 18.2.5 gpio interrupt control register (gpioic) the gpio interrupt control register (gpioic) is a 16-bit readable/writable register that performs 16-bit interrupt input control. gpioic is initialized to h'00000000 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. gpio interrupts are active-low level interrupts. bi t-by-bit masking is possible, and the or of all the bits set as gpio interrupts is used for interrupt detection. which bits interrupts are input to can be identified by reading the pdtra register. bit: 15 14 13 12 11 10 9 8 ptiren15 ptiren14 ptiren13 ptiren12 ptiren11 ptiren10 ptiren9 ptiren8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ptiren7 ptiren6 ptiren5 ptiren4 ptiren3 ptiren2 ptiren1 ptiren0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit n (n = 0?15)?port interrupt enable (ptirenn): specifies whether interrupt input is performed for each bit. bit n: ptirenn description 0 port m (m = 0?15) of 16-bit port is used as a normal i/o port (initial value) 1 port m (m = 0?15) of 16-bit port is used as a gpio interrupt * note: * when using an interrupt, set the corresponding port to input in the pctra register before making the ptirenn setting.
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 819 of 1076 sep 24, 2013 18.2.6 serial port register (scsptr1) bit: 7 6 5 4 3 2 1 0 eio ? ? ? spb1io spb1dt spb0io spb0dt initial value: 0 0 0 0 0 ? 0 ? r/w: r/w ? ? ? r/w r/w r/w r/w the serial port register (scsptr1) is an 8-bit r eadable/writable register that controls input/output and data for the port pins multiplexed with th e serial communication in terface (sci) pins. input data can be read from the rxd pin, output data written to the txd pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. sck pin data reading and output data writing can be performed by means of bits 3 and 2. bit 7 controls enabling and disabling of the rxi interrupt. scsptr1 can be read or written to by the cpu at all times. all scsptr1 bits except bits 2 and 0 are initialized to h'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. scsptr1 is not initialized in the module standby state or standby mode. bit 7?error interrupt only (eio): see section 15.2.8, serial port register (scsptr1). bits 6 to 4?reserved: these bits are always read as 0, and should only be written with 0. bit 3?serial port clock port i/o (spb1io): specifies serial port sck pin input/output. when the sck pin is actually set as a port output pin and outputs the value set by the spb1dt bit, the c/ a bit in scsmr1 and the cke1 and cke0 bits in scscr1 should be cleared to 0. bit 3: spb1io description 0 spb1dt bit value is not output to the sck pin (initial value) 1 spb1dt bit value is output to the sck pin
section 18 i/o ports SH7750, SH7750s, SH7750r group page 820 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 2?serial port cloc k port data (spb1dt): specifies the serial port sck pin input/output data. input or output is specified by the spb1io bit (see the description of bit 3, spb1io, for details). when output is specified, the value of the spb1dt bit is output to the sck pin. the sck pin value is read from the spb1dt bit regardless of the value of the spb1io bit. the initial value of this bit after a power-on reset or manual reset is undefined. bit 2: spb1dt description 0 input/output data is low-level 1 input/output data is high-level bit 1?serial port break i/o (spb0io): specifies the serial port txd pin output condition. when the txd pin is actually set as a port output pin and outputs the value set by the spb0dt bit, the te bit in scscr1 should be cleared to 0. bit 1: spb0io description 0 spb0dt bit value is not output to the txd pin (initial value) 1 spb0dt bit value is output to the txd pin bit 0?serial port break data (spb0dt): specifies the serial port rxd pin input data and txd pin output data. the txd pin output condition is specified by the spb0io bit (see the description of bit 1, spb0io, for details). when the txd pin is designated as an output, the value of the spb0dt bit is output to the txd pin. the rxd pin value is read from the spb0dt bit regardless of the value of the spb0io bit. the initial value of this bit after a power-on reset or manual reset is undefined. bit 0: spb0dt description 0 input/output data is low-level 1 input/output data is high-level
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 821 of 1076 sep 24, 2013 18.2.7 serial port register (scsptr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 rtsio rtsdt ctsio ctsdt ? ? spb2io spb2dt initial value: 0 ? 0 ? 0 0 0 ? r/w: r/w r/w r/w r/w r r r/w r/w the serial port register (scsptr2) is a 16-bit read able/writable register that controls input/output and data for the port pins multip lexed with the serial communicat ion interface (scif) pins. input data can be read from the rxd2 pin, output data written to the txd2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. cts2 pin data reading and output data writing can be performed by means of bits 5 and 4, and rts2 pin data reading and output data writing by means of bits 7 and 6. scsptr2 can be read or written to by the cpu at all times. all scsptr2 bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or ma nual reset; the value of bits 6, 4, and 0 is undefined. scsptr2 is not initialized in standby mode or in the module standby state. bits 15 to 8?reserved: these bits are always read as 0, and should only be written with 0. bit 7?serial port rts port i/o (rtsio): specifies serial port rts2 pin input/output. when the rts2 pin is actually set as a port output pin and outputs the value set by the rtsdt bit, the mce bit in scfcr2 should be cleared to 0. bit 7: rtsio description 0 rtsdt bit value is not output to the rts2 pin (initial value) 1 rtsdt bit value is output to the rts2 pin
section 18 i/o ports SH7750, SH7750s, SH7750r group page 822 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 6?serial port rts port data (rtsdt): specifies the serial port rts2 pin input/output data. input or output is specified by the rtsio pin (see the description of bit 7, rtsio, for details). when the rts2 pin is designated as an output, the value of the rtsdt bit is output to the rts2 pin. the rts2 pin value is read from the rtsdt bit regardless of the value of the rtsio bit. the initial value of this bit after a po wer-on reset or manual reset is undefined. bit 6: rtsdt description 0 input/output data is low-level 1 input/output data is high-level bit 5?serial port cts port i/o (ctsio): specifies serial port cts2 pin input/output. when the cts2 pin is actually set as a port output pin and outputs the value set by the ctsdt bit, the mce bit in scfcr2 should be cleared to 0. bit 5: ctsio description 0 ctsdt bit value is not output to the cts2 pin (initial value) 1 ctsdt bit value is output to the cts2 pin bit 4?serial port cts port data (ctsdt): specifies the serial port cts2 pin input/output data. input or output is specified by the ctsio pin (see the description of bit 5, ctsio, for details). when the cts2 pin is designated as an output, the value of the ctsdt bit is output to the cts2 pin. the cts2 pin value is read from the ctsdt bit regardless of the value of the ctsio bit. the initial value of this bit after a po wer-on reset or manual reset is undefined. bit 4: ctsdt description 0 input/output data is low-level 1 input/output data is high-level bits 3 and 2?reserved: these bits are always read as 0, and should only be written with 0. bit 1?serial port break i/o (spb2io): specifies the serial port txd2 pin output condition. when the txd2 pin is actually set as a port output pin and outputs the value set by the spb2dt bit, the te bit in scscr2 should be cleared to 0. bit 1: spb2io description 0 spb2dt bit value is not output to the txd2 pin (initial value) 1 spb2dt bit value is output to the txd2 pin
SH7750, SH7750s, SH7750r group section 18 i/o ports r01uh0456ej0702 rev. 7.02 page 823 of 1076 sep 24, 2013 bit 0?serial port break data (spb2dt): specifies the serial port rxd2 pin input data and txd2 pin output data. the txd2 pin output condition is specified by the spb2io bit (see the description of bit 1, spb2io, for details). when the txd2 pin is designated as an output, the value of the spb2dt bit is output to the txd2 pin. the rxd2 pin value is read from the spb2dt bit regardless of the value of the spb2io bit. the ini tial value of this bit after a power-on reset or manual reset is undefined. bit 0: spb2dt description 0 input/output data is low-level 1 input/output data is high-level
section 18 i/o ports SH7750, SH7750s, SH7750r group page 824 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 825 of 1076 sep 24, 2013 section 19 interrupt controller (intc) 19.1 overview the interrupt controller (intc) ascertains the prior ity of interrupt sources and controls interrupt requests to the cpu. the intc registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority. 19.1.1 features the intc has the following features. ? fifteen interrupt priority levels can be set by setting the three interrupt priority registers, the priorities of on-chip peripheral module interrupts can be selected from 15 levels for different request sources. ? nmi noise canceler function the nmi input level bit indicates the nmi pin st ate. the pin state can be checked by reading this bit in the interrupt exception service routin e, enabling it to be used as a noise canceler. ? nmi request masking when sr.bl bit is set to 1 it is possible to select whether or not nmi requests are to be masked when the sr.bl bit is set to 1. 19.1.2 block diagram figure 19.1 shows a block diagram of the intc.
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 826 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 legend: tmu: timer unit rtc: realtime clock unit sci: serial communication interface scif: serial communication interface with fifo wdt: watchdog timer ref: memory refresh controller section of the bus state controller dmac: direct memory access controller h-udi: high-performance user debug interface gpio: i/o port icr: interrupt control register ipra?iprd: interrupt priority registers a?d * 1 intpri00: interrupt priority level setting register 00 * 2 sr: status register notes: 1. iprd is provided only in the SH7750s and SH7750r. 2. intpri00 is provided only in the SH7750r. nmi input control irl3 ? irl0 tmu rtc sci scif wdt ref dmac h-udi gpio priority identifier 4 4 (interrupt request) com- parator bus interface internal bus icr ipra?iprd * 1 intpri00 * 2 (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) intc interrupt request imask sr cpu ipr figure 19.1 block diagram of intc
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 827 of 1076 sep 24, 2013 19.1.3 pin configuration table 19.1 shows the intc pin configuration. table 19.1 intc pins pin name abbreviation i/o function nonmaskable interrupt input pin nmi input input of nonmaskable interrupt request signal interrupt input pins irl3 ? irl0 input input of interrupt request signals (maskable by imask in sr) 19.1.4 register configuration the intc has the registers shown in table 19.2. table 19.2 intc registers name abbreviation r/w initial value * 1 p4 address area 7 address access size interrupt control register icr r/w * 2 h'ffd00000 h'1fd00000 16 interrupt priority register a ipra r/w h'0000 h 'ffd00004 h'1fd00004 16 interrupt priority register b iprb r/w h'0000 h 'ffd00008 h'1fd00008 16 interrupt priority register c iprc r/w h'0000 h'ffd 0000c h'1fd0000c 16 interrupt priority register d * 3 iprd r/w h'da74 h'ffd00010 h'1fd00010 16 interrupt priority level setting register 00 * 4 intpri00 r/w h'00000000 h'fe080000 h'1e080000 32 interrupt source register 00 * 4 intreq00 r h'00000000 h'fe080020 h'1e080020 32 interrupt mask register 00 * 4 intmsk00 r/w h'00000300 h'fe080040 h'1e080040 32 interrupt mask clear register 00 * 4 intmskclr 00 r ? h'fe080060 h'1e080060 32 notes: 1. initialized by a power-on reset or manual reset. 2. h'8000 when the nmi pin is hi gh, h'0000 when the nmi pin is low.
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 828 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 3. SH7750s and SH7750r only 4. SH7750r only 19.2 interrupt sources there are three types of interrupt sources: nmi, rl, and on-chip peripheral modules. each interrupt has a priority level (16?0), with level 16 as the highest and level 1 as the lowest. when level 0 is set, the interrupt is masked and interrupt requests are ignored. 19.2.1 nmi interrupt the nmi interrupt has the highest pr iority level of 16. it is alwa ys accepted unless the bl bit in the status register in the cpu is set to 1. in sleep or standby mode, the interrupt is accepted even if the bl bit is set to 1. a setting can also be made to have the nmi inte rrupt accepted even if the bl bit is set to 1. input from the nmi pin is edge-detected. the nmi ed ge select bit (nmie) in the interrupt control register (icr) is used to select either rising or falling edge. when the nmie bit in the icr register is modified, the nmi interrupt is not detected for a maximum of 6 bus clock cycles after the modification. nmi interrupt exception handling does not affect the interrupt mask level bits (imask) in the status register (sr).
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 829 of 1076 sep 24, 2013 19.2.2 irl interrupts irl interrupts are input by level at pins irl3 ? irl0 . the priority level is the level indicated by pins irl3 ? irl0 . an irl3 ? irl0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). a value of 15 (1111) indicates no interrupt request (interrupt priority level 0). interrupt requests priority encoder i r l 3 to i r l 0 4 SH7750 SH7750s SH7750r i r l 3 to i r l 0 figure 19.2 example of irl interrupt connection
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 830 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 19.3 irl3 ? irl0 pins and interrupt levels irl3 irl2 irl1 irl0 interrupt priority level interrupt request 0 0 0 0 15 level 15 interrupt request 1 14 level 14 interrupt request 1 0 13 level 13 interrupt request 1 12 level 12 interrupt request 1 0 0 11 level 11 interrupt request 1 10 level 10 interrupt request 1 0 9 level 9 interrupt request 1 8 level 8 interrupt request 1 0 0 0 7 level 7 interrupt request 1 6 level 6 interrupt request 1 0 5 level 5 interrupt request 1 4 level 4 interrupt request 1 0 0 3 level 3 interrupt request 1 2 level 2 interrupt request 1 0 1 level 1 interrupt request 1 0 no interrupt request a noise-cancellation feature is built in, and the irl interrupt is not detected unless the levels sampled at every bus clock cycle remain unchan ged for three consecutive cycles, so that no transient level on the irl pin change is detected. in stand by mode, as the bus clock is stopped, noise cancellation is performed using the 32.768 khz clock for the rtc instead. when the rtc is not used, therefore, interruption by means of irl interrupts cannot be performed in standby mode. the priority level of the irl interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts. however, the priority level can be changed to a higher one. the interrupt mask bits (imask) in the status re gister (sr) are not affe cted by irl interrupt handling. pins irl0 ? irl3 can be used for four independent interrupt requests by setting the irlm bit to 1 in the icr register. when independent interrupt requests are used in the SH7750, the interrupt priority levels are fixed (table 19.4). when independent interrupt requests are used in the SH7750s or SH7750r, the interrupt priority levels can be set in interrupt priority register d (iprd).
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 831 of 1076 sep 24, 2013 table 19.4 SH7750 irl3 ? irl0 pins and interrupt levels (when irlm = 1) irl3 irl2 irl1 irl0 interrupt priority level interrupt request 1/0 1/0 1/0 0 13 irl0 1/0 1/0 0 1 10 irl1 1/0 0 1 1 7 irl2 0 1 1 1 4 irl3 19.2.3 on-chip peripheral module interrupts on-chip peripheral module interrupts are generated by the following nine modules: ? high-performance user de bug interface (h-udi) ? direct memory access controller (dmac) ? timer unit (tmu) ? realtime clock (rtc) ? serial communicati on interface (sci) ? serial communication inte rface with fifo (scif) ? bus state controller (bsc) ? watchdog timer (wdt) ? i/o port (gpio) not every interrupt source is assigned a different in terrupt vector, bus sources are reflected in the interrupt event register (intevt), so it is easy to identify sources by using the intevt register value as a branch offset in th e exception handling routine. a priority level from 15 to 0 can be set for each module by means of interrupt priority registers a to d (ipra?iprd), 00 (intpri00). the interrupt mask bits (imask) in the status regi ster (sr) are not affected by on-chip peripheral module interrupt handling. on-chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the bl bit in th e status register (sr) is set to 1. to prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the bl bit to 0. in the case of interrupts on channel 3 or 4 of the tmu, also read from the interrupt source register 00 (intreq00). this will secure the necessary timing in ternally. when updating a number of flags, there is no problem if only the register containing the last flag updated is read.
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 832 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 if flag updating is performed while the bl bit is cleared to 0, the program may jump to the interrupt handling routine when the intevt register value is 0. in this case, interrupt handling is initiated due to the timing relationship between th e flag update and interrupt request recognition within the chip. processing can be continue d without any problem by executing an rte instruction. 19.2.4 interrupt exception handling and priority table 19.5 lists the codes for the interrupt even t register (intevt), and the order of interrupt priority. each interrupt source is assigned a unique intevt code. th e start address of the interrupt handler is common to each interrupt source. this is why, for instance, the value of intevt is used as an offset at the start of the interrupt handler and branched to in order to identify the interrupt source. the order of priority of the on-chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority register s a to d (ipra?iprd). the order of priority of the on-chip peripheral modules is set to 0 by a reset. when the priorities for multiple interrupt sources ar e set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 19.5. updating of interrupt priority registers a to d, 00 should only be carried out when the bl bit in the status register (sr) is set to 1. to prevent erroneous interrupt acceptance , first read one of the interrupt priority registers, then clear the bl b it to 0. this will secure the necessary timing internally.
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 833 of 1076 sep 24, 2013 table 19.5 interrupt exception ha ndling sources and priority order interrupt source intevt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 16 ? ? high irl irl3 ? irl0 = 0 h'200 15 ? ? irl3 ? irl0 = 1 h'220 14 ? ? irl3 ? irl0 = 2 h'240 13 ? ? irl3 ? irl0 = 3 h'260 12 ? ? irl3 ? irl0 = 4 h'280 11 ? ? irl3 ? irl0 = 5 h'2a0 10 ? ? irl3 ? irl0 = 6 h'2c0 9 ? ? irl3 ? irl0 = 7 h'2e0 8 ? ? irl3 ? irl0 = 8 h'300 7 ? ? irl3 ? irl0 = 9 h'320 6 ? ? irl3 ? irl0 = a h'340 5 ? ? irl3 ? irl0 = b h'360 4 ? ? irl3 ? irl0 = c h'380 3 ? ? irl3 ? irl0 = d h'3a0 2 ? ? irl3 ? irl0 = e h'3c0 1 ? ? irl0 h'240 15?0 (13) * 1 iprd (15? 12) * 1 ? irl1 h'2a0 15?0 (10) * 1 iprd (11?8) * 1 ? irl2 h'300 15?0 (7) * 1 iprd (7?4) * 1 ? irl3 h'360 15?0 (4) * 1 iprd (3?0) * 1 ? h-udi h-udi h'600 15?0 (0) iprc (3?0) ? gpio gpioi h'620 15?0 (0) iprc (15?12) ? dmac dmte0 h'640 15?0 (0) iprc (11?8) high dmte1 h'660 dmte2 h'680 dmte3 h'6a0 dmte4 * 2 h'780 dmte5 * 2 h'7a0 dmte6 * 2 h'7c0 dmte7 * 2 h'7e0 ? ? ? ? ? ? ? ? ? ? ? ? dmae h'6c0 low ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? low
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 834 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 interrupt source intevt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority tmu3 tuni3 * 2 h'b00 15?0 (0) intpri00 (11?8) ? tmu4 tuni4 * 2 h'b80 15?0 (0) intpri00 (15?12) ? tmu0 tuni0 h'400 15?0 (0) ipra (15?12) ? tmu1 tuni1 h'420 15?0 (0) ipra (11?8) ? tmu2 tuni2 h'440 15?0 (0) ipra (7?4) high ticpi2 h'460 low rtc ati h'480 15?0 (0) ipra (3?0) pri h'4a0 cui h'4c0 high ? low sci eri h'4e0 15?0 (0) iprb (7?4) high rxi h'500 txi h'520 ? ? tei h'540 low scif eri h'700 15?0 (0) iprc (7?4) high rxi h'720 bri h'740 ? ? txi h'760 low wdt iti h'560 15?0 (0) iprb (15?12) ? ref rcmi h'580 15?0 (0) iprb (11?8) high high ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rovi h'5a0 low low legend: tuni0?tuni4: underflow interrupts ticpi2: input capture interrupt ati: alarm interrupt pri: periodic interrupt cui: carry-up interrupt eri: receive-error interrupt rxi: receive-data-full interrupt txi: transmit-data-empty interrupt tei: transmit-end interrupt bri: break interrupt request iti: interval timer interrupt
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 835 of 1076 sep 24, 2013 rcmi: compare-match interrupt rovi: refresh counter overflow interrupt h-udi: high-performance use debug interface gpioi: i/o port interrupt dmte0?dmte7: dmac transfer end interrupts dmae: dmac address error interrupt notes: 1. interrupt priority levels can only be changed in the SH7750s or SH7750r. in the SH7750, the initial values cannot be changed. 2. SH7750r only 19.3 register descriptions 19.3.1 interrupt priority regist ers a to d (ipra?iprd) interrupt priority registers a to d (ipra?iprd) are 16-bit readable/writable registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. ipra to iprc are initialized to h'0000 and iprd is to h'da74 by a rese t. they are not initialized in standby mode. ipra to iprc bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 836 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 iprd (SH7750s and SH7750r only) bit: 15 14 13 12 11 10 9 8 initial value: 1 1 0 1 1 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 1 1 1 0 1 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 19.6 shows the relationship between the interrupt request sources and the ipra?iprd register bits. table 19.6 interrupt request so urces and ipra?iprd registers bits register 15?12 11?8 7?4 3?0 interrupt priority register a tmu0 tmu1 tmu2 rtc interrupt priority register b wdt ref * 1 sci reserved * 2 interrupt priority register c gpio dmac scif h-udi interrupt priority register d * 3 irl0 irl1 irl2 irl3 notes: 1. ref is the memory refresh unit in t he bus state controller (bsc). see section 13, bus state controller (bsc), for details. 2. reserved bits: these bits are always re ad as 0 and should always be written with 0. 3. SH7750s and SH7750r only as shown in table 19.6, four on-chip peripheral modules are assigned to each register. interrupt priority levels are established by setting a value fr om h'f (1111) to h'0 (00 00) in each of the four- bit groups: 15?12, 11?8, 7?4, and 3?0. setting h'f designates priority level 15 (the highest level), and setting h'0 designates priority level 0 (requests are masked).
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 837 of 1076 sep 24, 2013 19.3.2 interrupt control register (icr) the interrupt control register (icr) is a 16-bit register that sets the input signal detection mode for external interrupt input pin nmi an d indicates the input signal level at the nmi pin. this register is initialized by a power-on reset or manual reset. it is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 bit name: nmil mai ? ? ? ? nmib nmie initial value: 0/1 * 0 0 0 0 0 0 0 r/w: r r/w ? ? ? ? r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: irlm ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w ? ? ? ? ? ? ? note: * 1 when nmi pin input is high, 0 when low. bit 15?nmi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. it cannot be modified. bit 15: nmil description 0 nmi pin input level is low 1 nmi pin input level is high bit 14?nmi interrupt mask (mai): specifies whether or not all interrupts are to be masked while the nmi pin input level is low, irrespective of the cpu's sr.bl bit. bit 14: mai description 0 interrupts enabled even while nmi pin is low (initial value) 1 interrupts disabled while nmi pin is low * note: * nmi interrupts are accepted in normal operation and in sleep mode. in standby mode, all interrupts are masked, and standby is not cleared, while the nmi pin is low.
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 838 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 9?nmi block mode (nmib): specifies whether an nmi request is to be held pending or detected immediately while the sr.bl bit is set to 1. bit 9: nmib description 0 nmi interrupt requests held pending while sr.bl bit is set to 1 (initial value) 1 nmi interrupt requests detected while sr.bl bit is set to 1 notes: 1. if interrupt requests are enabled while sr.bl = 1, the previous exception information will be lost, and so must be saved beforehand. 2. this bit is cleared automatically by nmi acceptance. bit 8?nmi edge select (nmie): specifies whether the falling or rising edge of the interrupt request signal to the nmi pin is detected. bit 8: nmie description 0 interrupt request detected on falling edge of nmi input (initial value) 1 interrupt request detected on rising edge of nmi input bit 7?irl pin mode (irlm): specifies whether pins irl3 ? irl0 are to be used as level- encoded interrupt requests or as four independent interrupt requests. bit 7: irlm description 0 irl pins used as level-encoded interrupt requests (initial value) 1 irl pins used as four independent in terrupt requests (level-sense irq mode) bits 13 to 10 and 6 to 0?reserved: these bits are always read as 0, and should only be written with 0.
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 839 of 1076 sep 24, 2013 19.3.3 interrupt-priority-level setting regi ster 00 (intpri00) (SH7750r only) the interrupt-priority-level sett ing register 00 (intpri00) sets the priority levels (levels 15 ? 0) for the on-chip peripheral module interrupts. intpri00 is a 32-bit readable/writable register. it is initialized to h'00000000 by a reset, but is not initialized when the device enters standby mode. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r table 19.7 shows the correspondence between interrupt request sources and the bits in intpri00. table 19.7 interrupt request sources a nd the bits of the intpri00 register bit register 31 to 28 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4 3 to 0 interrupt- priority-level setting register 00 reserved reserved reserved reserved tmu ch4 tmu ch3 reserved reserved note: as shown in the table above, levels for all eight on-chip peripheral modules are assigned in a single register. the interrupt priority level fo r the interrupt source that corresponds to each set of four bits is set as a value from h 'f (1111) to h'0 (0000). the setting h'f selects interrupt priority level 15, which is the hig hest, and h'0 selects level 0, which means that interrupt requests from that source are masked. reserved bits are always read as 0. when writ ing, only 0s should be written to these bits.
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 840 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 19.3.4 interrupt source register 00 (intreq00) (SH7750r only) the interrupt source register 00 (intreq00) indicat es the origin of the interrupt request that has been sent to the intc. the states of the bits in this register is not aff ected by masking of the corresponding interrupts by the settings in the intpri00 or intmsk00 register. intreq00 is a 32-bit read-only register. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bit 31 to 0?interrupt request: each of the non-reserved bits in this register indicates that there is an interrupt request relevant to that bit. fo r the correspondence between the bits and interrupt sources, see section 19.3.7, bit assignments of intreq00, intmsk00, and intmskclr00 (SH7750r only). bits 31 to 0 description 0 there is no interrupt request that corresponds to this bit 1 there is an interrupt request that corresponds to this bit.
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 841 of 1076 sep 24, 2013 19.3.5 interrupt mask register 00 (intmsk00) (SH7750r only) the interrupt mask register 00 (intmsk00) sets the masking of individual interrupt requests. intmsk00 is a 32-bit register. it is initialized to h'000003ff by a reset, and retains this value in standby mode. to cancel masking of an interrupt, write a 1 to the corresponding bit in the intmskclr00 register. note that writing a 0 to a bit in intmsk00 does not change its value. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 r/w: r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 31 to 0?interrupt mask: sets the masking of the interrupt request that corresponds to the given bit. for the correspondence between bits and interrupt sources, see section 19.3.7, bit assignments of intreq00, intmsk00, and intmskclr00 (SH7750r only). bits 31 to 0 description 0 interrupt requests from the source that corresponds to this bit are accepted 1 interrupt requests from the source that corresponds to this bit are masked (initial value)
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 842 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 19.3.6 interrupt mask clear register 00 (intmskclr00) (SH7750r only) the interrupt mask clear register 00 (intmskclr00) clears the masking of individual interrupt requests. intmskclr00 is a 32-bit write-only register. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: w w w w w w w w w w w w w w w w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: w w w w w w w w w w w w w w w w bit 31 to 0 ? interrupt mask clear: each bit selects whether or no t to clear the masking of the interrupt source that corresponds to that bit. for the correspondence between the bits and interrupt sources, see section 19.3.7, bit assignments of intreq00, intmsk00, and intmskclr00 (SH7750r only). bits 31 to 0 description 0 masking of interrupt requests from the source that corresponds to the bit is not changed 1 masking of interrupt requests from the source that corresponds to the bit is cleared 19.3.7 bit assignments of intreq00, intmsk00, and intmskclr00 (SH7750r only) the relationship between the bits in these registers and interrupt sources is as shown below. table 19.8 bit assignments bit number module interrupt 31 to 10, 7 to 0 reserved reserved 9 tmu tuni4 8 tmu tuni3
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 843 of 1076 sep 24, 2013 19.4 intc operation 19.4.1 interrupt operation sequence the sequence of operations when an interrupt is generated is described below. figure 19.3 shows a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest-prio rity interrupt from the interrupt requests sent, according to the priority levels set in interrupt priority regi sters a to c (ipra?iprc). lower- priority interrupts are held pending. if two of thes e interrupts have the same priority level, or if multiple interrupts occur within a single module, the interrupt with the highest priority according to table 19.5, interrupt exception handling sources and priority order, is selected. 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (imask) in the status register (sr) of the cpu. if the request priority level is higher that the level in bits imask, the in terrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. 4. the cpu accepts an interrupt at a break between instructions. 5. the interrupt source code is set in the interrupt event register (intevt). 6. the status register (sr) and program counter (pc) are saved to ssr and spc, respectively. the r15 contents at this time are saved in sgr. 7. the block bit (bl), mode bit (md), and register bank bit (rb) in sr are set to 1. 8. the cpu jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (vbr) and h'00000600). the interrupt handler may branch with the intevt register value as its offset in order to identify the interrupt source. this enables it to branch to the handling routine for the particular interrupt source. notes: 1. the interrupt mask bits (imask) in the status register (sr) are not changed by acceptance of an interr upt in this lsi. 2. the interrupt source flag should be cleared in the interrupt handler. to ensure that an interrupt request that should have been clear ed is not inadvertently accepted again, read the interrupt source flag after it has been cl eared, then wait for the interval shown in table 19.9 (time for priority decision and sr mask bit comparison) before clearing the bl bit or executing an rte instruction. 3. for some interrupt sources, their interr upt masks (intmsk00) must e cleared using the intmskclr00 register.
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 844 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 program execution state no no yes no yes no yes yes no no yes yes no yes no no yes no yes save sr to ssr; save pc to spc set interrupt source in intevt set bl, md, rb bits in sr to 1 branch to exception handler interrupt generated? (bl bit in sr = 0) or (sleep or standby mode)? nmi? level 14 interrupt? level 1 interrupt? imask = level 13 or lower? imask = level 0? yes level 15 interrupt? imask * = level 14 or lower? note: * imask: interrupt mask bits in status register (sr) nmib in icr = 1 and nmi? figure 19.3 interrupt operation flowchart
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 845 of 1076 sep 24, 2013 19.4.2 multiple interrupts when handling multiple interrupts, interrupt handling should include the following procedures: 1. branch to a specific interrupt handler corresponding to a code set in the intevt register. the code in intevt can be used as a branch-offset for branching to the specific handler. 2. clear the interrupt source in the corresponding interrupt handler. 3. save spc and ssr to the stack. 4. clear the bl bit in sr, and set the accepted inte rrupt level in the interrupt mask bits in sr. 5. handle the interrupt. 6. set the bl bit in sr to 1. 7. restore ssr and spc from memory. 8. execute the rte instruction. when these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing bl in step 4. this enables th e interrupt response time to be shortened for urgent processing. 19.4.3 interrupt masking with mai bit by setting the mai bit to 1 in the icr register, it is possible to mask interrupts while the nmi pin is low, irrespective of the bl and imask bits in the sr register. ? in normal operation and sleep mode all interrupts are masked while the nmi pin is low. however, an nmi interrupt only is generated by a transition at the nmi pin. ? in standby mode all interrupts are masked while the nmi pin is low, and an nmi interrupt is not generated by a transition at the nmi pin. therefore, standby cannot be cleared by an nmi interrupt while the mai bit is set to 1.
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 846 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 19.5 interrupt response time the time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception service routine is started (the interrupt response time) is shown in table 19.9. table 19.9 interrupt response time number of states item nmi rl peripheral modules notes time for priority decision and sr mask bit comparison * 1icyc + 4bcyc 1icyc + 7bcyc 1icyc + 2bcyc wait time until end of sequence being executed by cpu s ? 1 ( 0) icyc s ? 1 ( 0) icyc s ? 1 ( 0) icyc time from interrupt exception handling (save of sr and pc) until fetch of first instruction of exception handler is started 4 icyc 4 icyc 4 icyc response time total 5icyc + 4bcyc + (s ? 1)icyc 5icyc + 7bcyc + (s ? 1)icyc 5icyc + 2bcyc + (s ? 1)icyc minimum case 13icyc 19icyc 9icyc when icyc: bcyc = 2:1 maximum case 36 + s icyc 60 + s icyc 20 + s icyc when icyc: bcyc = 8:1 legend: icyc: one cycle of internal cl ock supplied to cpu, etc. bcyc: one ckio cycle s: latency of instruction note: * in the SH7750 and SH7750s including the case where the mask bit (imask) in sr is changed, and a new interrupt is generated.
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 847 of 1076 sep 24, 2013 19.6 usage notes 19.6.1 nmi interrupts (SH7750 and SH7750s only) when multiple nmi interrupts are input to the nmi pin within a set period of time (which is dependent on the internal state of the cpu and the external bus st ate), subsequent interrupts may not be accepted. note that this problem does not occur when sufficient time* 1 is provided between nmi interrupt inputs or with non-nmi interrupts such as irl interrupts. workarounds: methods 1, 2, or 3 below may be used to avoid the above problem. 1. allow sufficient time between nmi interrupt inputs, as described in note 1, below. note that it may not be possible to assure the above interval between nmi interrupt inputs if hazard is input to nmi, and that this may cause the device to malfunction. design the external circuits so that no hazard is input via nmi.* 2 2. do not use nmi interrupts. use irl interrupts instead. 3. workaround using software the above problem can be avoided by inserting the following lines of code* 3 * 4 into the nmi exception handling routine. notes: 1. if sr.bl is cleared to 0 so that one or more instructions may be executed between the handling of two nmi interrupts. 2. when changing the level of the nmi input, ensure that the high and low durations are at least 5 ckio cycles. also ensure that no noise pulses occur before or after level changes. 3. if the nmi exception handling routine contains code that changes the value of the sr.bl bit, the code listed below should be inserted before the point at which the change is made. 4. registers r0 to r3 in the code sample can be changed to any general register. also, the necessary register save and restore instructions should be inserted before and after the code listed below, as appropriate.
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 848 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; r0 : tmp ;; r1 : original sr ;; r2 : original icr ;; r3 : icr address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; nmih: ; (1) set sr.imask = h'f stc sr, r1 ; store sr mov r1,r0 or #h'f0,r0 ldc r0, sr ; (2) reverse icr.nmie mov.l #icr, r3 mov.w @r3, r2 ; store icr mov.w #h'0100, r0 xor r2, r0 mov.w r0, @r3 ; write icr.nmie inverted (dummy) bra nmih1 nop .pool .align 4 nmih2: ; mov.w @r3, r0 ; dummy read mov.w r2, @r3 ; write icr.nmie stc sr, r0 ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r0, sr ldc r1, sr ; restore sr bra nmih3
SH7750, SH7750s, SH7750r group section 19 interrupt controller (intc) r01uh0456ej0702 rev. 7.02 page 849 of 1076 sep 24, 2013 nop nmih1: bra nmih2 nop nmih3: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
section 19 interrupt controller (intc) SH7750, SH7750s, SH7750r group page 850 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 851 of 1076 sep 24, 2013 section 20 user break controller (ubc) 20.1 overview the user break controller (ubc) provides functions that simplify program debugging. when break conditions are set in the ubc, a user break interrupt is generated according to the contents of the bus cycle generated by the cpu. this function makes it easy to design an effective self- monitoring debugger, enabling programs to be debugged with the chip alone, without using an in- circuit emulator. 20.1.1 features the ubc has the following features. ? two break channels (a and b) user break interrupts can be generated on independent conditions for channels a and b, or on sequential conditions (sequential break setting: channel a channel b). ? the following can be set as break compare conditions: ? address (selection of 32-bit virtual address and asid for comparison): address: all bits compared/lower 10 bits ma sked/lower 12 bits masked/lower 16 bits masked/lower 20 bits masked/all bits masked asid: all bits compared/all bits masked ? data (channel b only, 32-bit mask capability) ? bus cycle: instruction access/operand access ? read/write ? operand size: byte/word/longword/quadword ? an instruction access cycle break ca n be effected before or afte r the instruction is executed.
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 852 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 20.1.2 block diagram figure 20.1 shows a block diagram of the ubc. access control address bus data bus channel a access comparator address comparator channel b access comparator address comparator data comparator bbra bara basra bamra bbrb barb basrb bamrb bdrb bdmrb brcr control user break trap request le g end: bbra: break bus cycle re g ister a bara: break address re g ister a basra: break asid re g ister a bamra: break address mask re g ister a bbrb: break bus cycle re g ister b barb: break address re g ister b basrb: break asid re g ister b bamrb: break address mask re g ister b bdrb: break data re g ister b bdmrb: break data mask re g ister b brcr: break control re g ister figure 20.1 block diagra m of user break controller
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 853 of 1076 sep 24, 2013 table 20.1 shows the ubc registers. table 20.1 ubc registers name abbreviation r/w initial value p4 address area 7 address access size break address register a bara r/w undefined h'ff200000 h' 1f200000 32 break address mask register a bamra r/w undefined h'ff200004 h'1f200004 8 break bus cycle register a bbra r/w h'0000 h'ff200008 h'1f200008 16 break asid register a basra r/w undefined h'ff000014 h'1f000014 8 break address register b barb r/w undefined h'ff20000c h'1f20000c 32 break address mask register b bamrb r/w undefined h'ff200010 h'1f200010 8 break bus cycle register b bbrb r/w h'0000 h'ff200014 h'1f200014 16 break asid register b basrb r/w undefined h'ff000018 h'1f000018 8 break data register b bdrb r/w undefined h'ff200018 h' 1f200018 32 break data mask register b bdmrb r/w undefined h'ff20001c h'1f20001c 32 break control register brcr r/w h'0000 * h'ff200020 h'1f200020 16 note: * some bits are not initialized. see section 20.2.12, break control register (brcr), for details.
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 854 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 20.2 register descriptions 20.2.1 access to ubc control registers the access size must be the same as the control regi ster size. if the sizes are different, a write will not be effected in a ubc register write operation, and a read operation will return an undefined value. ubc control register contents cannot be transferred to a floating-point register using a floating-point memory load instruction. when a ubc control register is updated, use either of the following methods to make the updated value valid: 1. execute an rte instruction after the memory store instruction that upd ated the register. the updated value will be valid from the rte instruction jump destination onward. 2. execute instructions requiring 5 states for execution after the memory store instruction that updated the register. as the cpu executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. the updated value will be valid from the 6th state onward.
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 855 of 1076 sep 24, 2013 20.2.2 break address register a (bara) bit: 31 30 29 28 27 26 25 24 baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w legend: * : undefined break address register a (bara) is a 32-bit readable/writable regi ster that specifies the virtual address used in the channel a break conditions. bara is not initialized by a power-on reset or manual reset. bits 31 to 0?break address a31 to a0 (baa31?baa0): these bits hold the virtual address (bits 31?0) used in the channel a break conditions.
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 856 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 20.2.3 break asid register a (basra) bit: 7 6 5 4 3 2 1 0 basa7 basa6 basa5 basa4 basa3 basa2 basa1 basa0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w legend: * : undefined break asid register a (basra) is an 8-bit read able/writable register th at specifies the asid used in the channel a break conditions. basra is not initialized by a power-on reset or manual reset. bits 7 to 0?break asid a7 to a0 (basa7?basa0): these bits hold the as id (bits 7?0) used in the channel a break conditions. 20.2.4 break address mask register a (bamra) bit: 7 6 5 4 3 2 1 0 ? ? ? ? bama2 basma bama1 bama0 initial value: 0 0 0 0 * * * * r/w: r r r r r/w r/w r/w r/w legend: * : undefined break address mask register a (b amra) is an 8-bit readable/wri table register that specifies which bits are to be masked in the break asid set in basra and the break address set in bara. bamra is not initialized by a power-on reset or manual reset. bits 7 to 4?reserved: these bits are always read as 0, and should only be written with 0. bit 2?break asid mask a (basma): specifies whether all bits of the channel a break asid7 to asid0 (basa7?basa0) are to be masked. bit 2: basma description 0 all basra bits are incl uded in break conditions 1 no basra bits are include d in break conditions
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 857 of 1076 sep 24, 2013 bits 3, 1, and 0?break address mask a2 to a0 (bama2?bama0): these bits specify which bits of the channel a break address 31 to 0 (baa31?baa0) set in bara are to be masked. bit 3: bama2 bit 1: bama1 bit 0: bama0 description 0 0 0 all bara bits are included in break conditions 1 lower 10 bits of bara are masked, and not included in break conditions 1 0 lower 12 bits of bara are masked, and not included in break conditions 1 all bara bits are masked, and not included in break conditions 1 0 0 lower 16 bits of bara are masked, and not included in break conditions 1 lower 20 bits of bara are masked, and not included in break conditions 1 * reserved (cannot be set) legend: * : don't care 20.2.5 break bus cycle register a (bbra) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? sza2 ida1 ida0 rwa1 rwa0 sza1 sza0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w break bus cycle register a (bbra) is a 16-bit readable/writable register that sets three conditions?(1) instruction access/operand acce ss, (2) read/write, and (3) operand size?from among the channel a break conditions. bbra is initialized to h'0000 by a power-on reset. it retains its value in standby mode. bits 15 to 7?reserved: these bits are always read as 0, and should only be written with 0.
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 858 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 5 and 4?instruction access/opera nd access select a (ida1, ida0): these bits specify whether an instruction access cycle or an operan d access cycle is used as the bus cycle in the channel a break conditions. bit 5: ida1 bit 4: ida0 description 0 0 condition comparison is not performed (initial value) 1 instruction access cycle is used as break condition 1 0 operand access cycle is used as break condition 1 instruction access cycle or operand access cycle is used as break condition bits 3 and 2?read/write select a (rwa1, rwa0): these bits specify whether a read cycle or write cycle is used as the bus cycl e in the channel a break conditions. bit 3: rwa1 bit 2: rwa0 description 0 0 condition comparison is not performed (initial value) 1 read cycle is used as break condition 1 0 write cycle is used as break condition 1 read cycle or write cycle is used as break condition bits 6, 1, and 0?operand si ze select a (sza2?sza0): these bits select the operand size of the bus cycle used as a channel a break condition. bit 6: sza2 bit 1: sza1 bit 0: sza0 description 0 0 0 operand size is not included in break conditions (initial value) 1 byte access is used as break condition 1 0 word access is used as break condition 1 longword access is used as break condition 1 0 0 quadword access is used as break condition 1 reserved (cannot be set) 1 * reserved (cannot be set) legend: * : don't care
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 859 of 1076 sep 24, 2013 20.2.6 break address register b (barb) barb is the channel b break address register. th e bit configuration is the same as for bara. 20.2.7 break asid register b (basrb) basrb is the channel b break asid register. the bit configuration is the same as for basra. 20.2.8 break address mask register b (bamrb) bamrb is the channel b break address mask regist er. the bit configuration is the same as for bamra. 20.2.9 break data register b (bdrb) bit: 31 30 29 28 27 26 25 24 bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w legend: * : undefined
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 860 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 break data register b (bdrb) is a 32-bit readable/w ritable register that specifies the data (bits 31? 0) to be used in the channel b break conditions. bdrb is not initialized by a power-on reset or manual reset. bits 31 to 0?break data b31 to b0 (bdb31?bdb0): these bits hold the data (bits 31?0) to be used in the channel b break conditions. 20.2.10 break data mask register b (bdmrb) bit: 31 30 29 28 27 26 25 24 bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bdmb2 3 bdmb2 2 bdmb2 1 bdmb2 0 bdmb1 9 bdmb1 8 bdmb1 7 bdmb1 6 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bdmb1 5 bdmb1 4 bdmb1 3 bdmb1 2 bdmb1 1 bdmb1 0 bdmb9 bdmb8 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w legend: * : undefined break data mask register b (bdmrb) is a 32-bit readable/writable register that specifies which bits of the break data set in bdrb are to be masked. bdmrb is not initialized by a power-on reset or manual reset.
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 861 of 1076 sep 24, 2013 bits 31 to 0?break data mask b31 to b0 (bdmb31?bdmb0): these bits specify whether the corresponding bit of the channel b break data b31 to b0 (bdb31?bdb0) set in bdrb is to be masked. bit 31?0: bdmbn description 0 channel b break data bit bdbn is included in break conditions 1 channel b break data bit bdbn is masked, and not included in break conditions n = 31 to 0 note: when the data bus value is included in the break conditions, the operand size should be specified. when byte size is specified, se t the same data in bits 15?8 and 7?0 of bdrb and bdmrb. 20.2.11 break bus cycle register b (bbrb) bbrb is the channel b bus break register. the b it configuration is the same as for bbra. 20.2.12 break control register (brcr) bit: 15 14 13 12 11 10 9 8 cmfa cmfb ? ? ? pcba ? ? initial value: 0 0 0 0 0 * 0 0 r/w: r/w r/w r r r r/w r r bit: 7 6 5 4 3 2 1 0 dbeb pcbb ? ? seq ? ? ubde initial value: * * 0 0 * 0 0 0 r/w: r/w r/w r r r/w r r r/w legend: * : undefined the break control register (brcr) is a 16-bit read able/writable register that specifies (1) whether channels a and b are to be used as two independent channels or in a sequential condition, (2) whether the break is to be effected before or after instruction execution, (3) whether the bdrb register is to be included in the channel b break conditions, and (4) whether the user break debug function is to be used. brcr also contains condition match flags. the cmfa, cmfb, and ubde bits in brcr are initialized to 0 by a power-on reset, but retain their value in standby mode. the value of the pcba, dbeb, pcbb, and seq bits is undefined after a power-on reset or manual reset, so these bits should be in itialized by software as necessary.
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 862 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bit 15?condition match flag a (cmfa): set to 1 when a break condition set for channel a is satisfied. this flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) bit 15: cmfa description 0 channel a break condition is not matched (initial value) 1 channel a break condition match has occurred bit 14?condition match flag b (cmfb): set to 1 when a break condition set for channel b is satisfied. this flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) bit 14: cmfb description 0 channel b break condition is not matched (initial value) 1 channel b break condition match has occurred bits 13 to 11?reserved: these bits are always read as 0, and should only be written with 0. bit 10?instruction access break select a (pcba): specifies whether a channel a instruction access cycle break is to be effected before or af ter the instruction is executed. this bit is not initialized by a power-on reset or manual reset. bit 10: pcba description 0 channel a pc break is effect ed before instruction execution 1 channel a pc break is effected after instruction execution bits 9 and 8?reserved: these bits are always read as 0, and should only be written with 0. bit 7?data break enable b (dbeb): specifies whether the data bus condition is to be included in the channel b break conditions. this bit is not initialized by a power-on reset or manual reset. bit 7: dbeb description 0 data bus condition is not included in channel b conditions 1 data bus condition is included in channel b conditions note: when the data bus is included in the break conditions, bits idb1?0 in break bus cycle register b (bbrb) should be set to 10 or 11.
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 863 of 1076 sep 24, 2013 bit 6?pc break select b (pcbb): specifies whether a channel b instruction access cycle break is to be effected before or after the instruction is executed. this bit is not initialized by a power-on reset or manual reset. bit 6: pcbb description 0 channel b pc break is effect ed before instruction execution 1 channel b pc break is effected after instruction execution bits 5 and 4?reserved: these bits are always read as 0, and should only be written with 0. bit 3?sequence condition select (seq): specifies whether the conditions for channels a and b are to be independent or sequential. this bit is not initialized by a power-on reset or manual reset. bit 3: seq description 0 channel a and b comparisons are performed as independent conditions 1 channel a and b comparisons are performed as sequential conditions (channel a channel b) bits 2 and 1?reserved: these bits are always read as 0, and should only be written with 0. bit 0?user break debug enable (ubde): specifies whether the user break debug function (see section 20.4, user break debug support function) is to be used. bit 0: ubde description 0 user break debug function is not used (initial value) 1 user break debug function is used
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 864 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 20.3 operation 20.3.1 explanation of terms relating to accesses an instruction access is an access that obtains an instruction. an operand access is any memory access for the purpose of instru ction execution. for example, the access to address pc+disp 2+4 in the instruction mov.w @(disp ,pc), rn (an access very close to the program counter) is an operand access. the fetching of an instruction from the branch destination when a branch instruction is executed is also an instruction access. as the term ?d ata? is used to distinguish data from an address, the term ?operand access? is used in this section. in this lsi, all operand accesses are treated as either read accesses or write accesses. the following instructions require special attention: ? pref, ocbp, and ocbwb instructio ns: treated as read accesses. ? movca.l and ocbi instructions: treated as write accesses. ? tas.b instruction: treated as one read access and one write access. the operand accesses for the pref , ocbp, ocbwb, and ocbi inst ructions are accesses with no access data. this lsi handles all operand accesses as having a data size. the data size can be byte, word, longword, or quadword. the operand data si ze for the pref, ocbp, ocbwb, movca.l, and ocbi instructions is treated as longword. 20.3.2 explanation of terms relating to instruction intervals in this section, ?1 (2, 3, ...) instruction(s) af ter...?, as a measure of the distance between two instructions, is defined as follows. a branch is counted as an interval of two instructions. ? example of sequence of instructions with no branch: 100 instruction a (0 instructions after instruction a) 102 instruction b (1 instruction after instruction a) 104 instruction c (2 instructions after instruction a) 106 instruction d (3 instructions after instruction a)
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 865 of 1076 sep 24, 2013 ? example of sequence of instruc tions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 instruction a: bt/s l200 (0 instructions after instruction a) 102 instruction b (1 instruction after instruction a, 0 instructions after instruction b) l200 200 instruction c (3 instructions after instruction a, 2 instructions after instruction b) 202 instruction d (4 instructions after instruction a, 3 instructions after instruction b) 20.3.3 user break operation sequence the sequence of operations from setting of brea k conditions to user break exception handling is described below. 1. specify pre- or post-execu tion breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel a and b break conditions, in the break control register (brcr). set the break addresses in the break address registers for each channel (bara, barb), the asids corr esponding to the break space in the break asid registers (basra, basrb), and the address and asid masking methods in the break address mask registers (bamra, bamrb). if the data bus value is to be included in the break conditions, also set the break data in the break data regist er (bdrb) and the data mask in the break data mask register (bdmrb). 2. set the break bus conditions in the break bus cycle registers (bbra, bbrb). if even one of the bbra/bbrb instruction access/operand access select (id bit) and read/write select groups (rw bit) is set to 00, a user break interrupt w ill not be generated on the corresponding channel. make the bbra and bbrb settings after all other break-related register settings have been completed. if breaks are enabled with bbra/ bbrb while the break address, data, or mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently. 3. the operation when a break condition is satisfied depends on the bl bit (in the cpu's sr register). when the bl bit is 0, exception handling is started and the condition match flag (cmfa/cmfb) for the respective channel is set fo r the matched condition. when the bl bit is 1, the condition match flag (cmfa/cmfb) for th e respective channel is set for the matched condition but exception handling is not started. the condition match flags (cmfa, cmfb) are set by a branch condition match, but are not automatically cleared. therefore, a memory store instruction should be used on the brcr
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 866 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 register to clear the flags to 0. see section 20.3.6, condition match flag setting, for the exact setting conditions for the condition match flags. 4. when sequential condition mode has been selected, and the channel b condition is matched after the channel a condition has been matched, a break is effected at the instruction at which the channel b condition was matched. see section 20.3.8, contiguous a and b settings for sequential conditions, for the operation when the channel a condition match and channel b condition match occur close together. with sequential conditions, only the channel b condition match flag is set. when sequential condition mode has been selected, if it is wished to clear the channel a match when the channel a condition has been matched but the channel b condition has not yet been matched, this can be done by writing 0 to the seq bit in the brcr register. 20.3.4 instruction access cycle break 1. when an instruction access/ read/word setting is made in the break bus cycle register (bbra/bbrb), an instruction access cycle can be used as a break condition. in this case, breaking before or after execution of the re levant instruction can be selected with the pcba/pcbb bit in the br eak control register (brcr). when an instruction access cycle is used as a break condition, clear the lsb of the break address registers (bara, barb) to 0. a break will not be generated if this bit is set to 1. 2. when a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. therefore, an overrun-fetched instruction (an instruction that is fetched but not executed when a branch or exception occurs) cannot be used in a break. however, if a tlb miss or tlb protection violation exception occurs at the time of the fetch of an instruction subject to a break, the break exception handling is carried out first. the instruction tlb exception handling is performed when the instruction is re-executed (see section 5.4, exception types and priorities). also , since a delayed branch instruction and the delay slot instruction are executed as a single in struction, if a pre-execu tion break is specified for a delay slot instruction, the break will be e ffected before execution of the delayed branch instruction. however, a pre-execution break cannot be specified for the delay slot instruction for an rte instruction. 3. with a pre-execution break, th e instruction set as a break cond ition is executed, then a break interrupt is generated before the next instruction is executed. when a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruct ion at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made).
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 867 of 1076 sep 24, 2013 4. when an instruction access cycle is set for cha nnel b, break data register b (bdrb) is ignored in judging whether there is an instruction acce ss match. therefore, a br eak condition specified by the dbeb bit in brcr is not executed. 20.3.5 operand access cycle break 1. in the case of an operand access cycle break, the bits included in address bus comparison vary as shown below according to the data size sp ecification in the break bus cycle register (bbra/bbrb). data size address bits compared quadword (100) address bits a31?a3 longword (011) address bits a31?a2 word (010) address bits a31?a1 byte (001) address bits a31?a0 not included in condition (000) in quadword access, address bits a31?a3 in longword access, address bits a31?a2 in word access, address bits a31?a1 in byte access, address bits a31?a0 2. when data value is included in break conditions in channel b when a data value is included in the break conditions, set the dbeb bit in the break control register (brcr) to 1. in this case, break data register b (bdrb) and break data mask register b (bdmrb) settings are necessary in addition to the address condition. a user break interrupt is generated when all three conditions?address, asid, and data?are matched. when a quadword access occurs, the 64-bit access data is di vided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. a break is generated if either of the 32-bit data units satisfies the data match condition. set the idb1?0 bits in break bus cycle regist er b (bbrb) to 10 or 11. when byte data is specified, the same data should be set in the two bytes comprising bits 15?8 and bits 7?0 in break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31?16 of bdrb and bdmrb are ignored. 3. when the dbeb bit in the break control register (brcr) is set to 1, a break is not generated by an operand access with no access data (an operand access in a pref, ocbp, ocbwb, or ocbi instruction).
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 868 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 20.3.6 condition match flag setting 1. instruction access with post-e xecution condition, or operand access the flag is set when execution of the instructi on that causes the break is completed. as an exception to this, however, in the case of an in struction with more th an one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed. example 1: 100 bt l200 (branch performed) 102 instruction (operand access break on channel a) flag not set example 2: 110 fadd (fpu exception) 112 instruction (operand access break on channel a) flag not set 2. instruction access wi th pre-execution condition the flag is set when the break match condition is detected. example 1: 110 instruction (pre-execution break on channel a) flag set 112 instruction (pre-execution break on channel b) flag not set example 2: 110 instruction (pre-execution break on channel b, instruction access tlb miss) flag set 20.3.7 program counter (pc) value saved 1. when instruction access (pre-ex ecution) is set as a break condi tion, the program counter (pc) value saved to spc in user break interrupt handling is the address of the instruction at which the break condition match occurred. in this case, a user break interrupt is generated and the fetched instruction is not executed. 2. when instruction access (post-ex ecution) is set as a break cond ition, the program counter (pc) value saved to spc in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. in this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction. 3. when an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). in this case, the pc
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 869 of 1076 sep 24, 2013 value saved to spc is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made). 4. when operand access (address only) is set as a break condition, the addr ess of the instruction to be executed after the instruction at which the condition match occurred is saved to spc. the instruction at which the condition match occu rred is executed, and a user break interrupt occurs before the following instruction is executed. 5. when operand access (address + data) is set as a break condition, execut ion of the instruction at which the condition match occurre d is completed. a user break interrupt is generated before execution of instructions from one instruction later to four instructions later. it is not possible to specify at which instruction, from one later to four later, the interrupt will be generated. the start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to spc. if an instruction between one instruction later and four instructi ons later causes another exception, control is performed as follows. designating the exception caused by the break as exception 1, and the exception caused by an instruction between one instruction later and four instructions later as exception 2, the fact that memo ry updating and register updatin g that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1. the program counter value saved is the address of the first instruction for which execution is suppressed. whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register (expevt/intevt) is not guaranteed. however, if exception 2 is from a source not synchronized with an instruction (external interrupt or peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register (expevt/intevt). 20.3.8 contiguous a and b settings for sequential conditions when channel a match and channel b match timings are close together, a sequential break may not be guaranteed. rules relating to the guaranteed range are given below. 1. instruction access matches on both channel a and channel b instruction b is 0 instructions after instruction a equivalent to setting the same address. do not use this setting. instruction b is 1 instruction after instruction a sequential operation is not guaranteed. instruction b is 2 or more instructions after instruction a sequential operation is guaranteed.
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 870 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 2. instruction access match on channe l a, operand access match on channel b instruction b is 0 or 1 instruction after instruction a sequential operation is not guaranteed. instruction b is 2 or more instructions after instruction a sequential operation is guaranteed. 3. operand access match on channel a, instruction access match on channel b instruction b is 0 to 3 instructions after instruction a sequential operation is not guaranteed. instruction b is 4 or more instructions after instruction a sequential operation is guaranteed. 4. operand access matches on bo th channel a and channel b do not make a setting such that a single oper and access will match the break conditions of both channel a and channel b. there are no other restrictions. for example, sequential operation is guaranteed even if two accesses with in a single instruction match channel a and channel b conditions in turn. 20.3.9 usage notes 1. do not execute a post-exe cution instruction access break for the sleep instruction. 2. do not make an operand access break setting between 1 and 3 instructions before a sleep instruction. 3. the value of the bl bit referenced in a user break exception depends on the break setting, as follows. a. pre-execution in struction access break: the bl bit value before the executed instruction is referenced. b. post-execution instruction access break: the or of the bl bit values before and after the executed instruction is referenced. c. operand access break (address/data): the bl bit value after the exec uted instruction is referenced. d. in the case of an instruction that modifies the bl bit
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 871 of 1076 sep 24, 2013 sl.bl pre- execution instruction access post- execution instruction access pre- execution instruction access post- execution instruction access operand access (address/data) 0 0 a a a a a 1 0 m m m m a 0 1 a m a m m 1 1 m m m m m legend: a: accepted m: masked e. in the case of an rte delay slot the bl bit value before execution of a delay slot instruction is the same as the bl bit value before execution of an rte instruction. the bl bit value after execution of a delay slot instruction is the same as the first bl bit value for the first instruction executed on returning by means of an rte instruction (the same as the value of the bl bit in ssr before execution of the rte instruction). f. if an interrupt or exception is accepted with th e bl bit cleared to 0, the value of the bl bit before execution of the first instruction of the exception handling routine is 1. 4. if channels a and b both match independently at virtually the same time, and, as a result, the spc value is the same for both user break interrupt s, only one user break interrupt is generated, but both the cmfa bit and the cmfb bit are set. for example: 110 instruction (post-execution instruction break on channel a) spc = 112, cmfa = 1 112 instruction (pre-execution instruction break on channel b) spc = 112, cmfb = 1 5. the pcba or pcbb bit in brcr is invali d for an instruction access break setting. 6. when the seq bit in brcr is 1, the internal sequential break state is initialized by a channel b condition match. for example: a a b (user break generated) b (no break generated) 7. in the event of contention between a re-execution type exception and a post-execution break in a multistep instruction, the re-execution type excep tion is generated. in this case, the cmf bit may or may not be set to 1 when the break condition occurs. 8. a post-execution break is cla ssified as a completion type excep tion. consequently, in the event of contention between a completion type exce ption and a post-execut ion break, the post- execution break is suppressed in accordance with the priorities of the two events. for example,
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 872 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 in the case of contention between a trapa inst ruction and a post-execu tion break, the user break is suppressed. however, in this case, the cmf bit is set by the occurrence of the break condition. 20.4 user break debug support function the user break debug support function enables the processing used in the event of a user break exception to be changed. when a user break exception occurs, if the ubde bit is set to 1 in the brcr register, the dbr register value will be used as the branch destination address instead of [vbr + offset]. the value of r15 is saved in the sgr register regardless of the value of the ubde bit in the brcr register or the kind of exception event. a flowch art of the user break debug support function is shown in figure 20.2.
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 873 of 1076 sep 24, 2013 spc pc ssr sr sr.bl b'1 sr.md b'1 sr.rb b'1 exception/interrupt g eneration exception exception/ interrupt/trap? trap interrupt pc h'a0000000 pc vbr + vector offset exception service routine execute rte instruction pc spc sr ssr sgr r15 expevt h'160 tra trapa (imm) pc dbr debu g pro g ram r15 sgr (stc instruction) reset exception? (brcr.ubde == 1) && (user break exception)? end of exception operations intevt interrupt code expevt exception code yes no no yes hardware operation figure 20.2 user break debug support function flowchart
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 874 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 20.5 examples of use instruction access cycle br eak condition settings ? register settings: basra = h'80 / bara = h'00000404 / bamra = h'00 / bbra = h'0014 / basrb = h'70 / barb = h'00008010 / bamrb = h'01 / bbrb = h'0014 / bdrb = h'00000000 / bdmrb = h'00000000 / brcr = h'0400 conditions set: independent channel a/channel b mode ? channel a: asid: h'80 / address: h'00000404 / address mask: h'00 bus cycle: instruction access (pos t-instruction-execution), read (operand size not included in conditions) ? channel b: asid: h'70 / address: h'00008010 / address mask: h'01 data: h'00000000 / data mask: h'00000000 bus cycle: instruction access (pre -instruction-execution), read (operand size not included in conditions) a user break is generated after execution of the instruction at address h'00000404 with asid = h'80, or before execution of an instruction at addresses h'00008000?h'000083fe with asid = h'70. ? register settings: basra = h'80 / bara = h'00037226 / bamra = h'00 / bbra = h'0016 / basrb = h'70 / barb = h'0003722e / bamrb = h'00 / bbrb = h'0016 / bdrb = h'00000000 / bdmrb = h'00000000 / brcr = h'0008 conditions set: channel a channel b sequential mode ? channel a: asid: h'80 / address: h'00037226 / address mask: h'00 bus cycle: instruction access (pre-instruction-exe cution), read, word ? channel b: asid: h'70 / address: h'0003722e / address mask: h'00 data: h'00000000 / data mask: h'00000000 bus cycle: instruction access (pre-instruction-exe cution), read, word the instruction at address h'00037266 with asid = h'80 is executed, then a user break is generated before execution of the instruction at address h'0003722e with asid = h'70. ? register settings: basra = h'80 / bara = h'00027128 / bamra = h'00 / bbra = h'001a / basrb = h'70 / barb = h'00031415 / bamrb = h'00 / bbrb = h'0014 / bdrb = h'00000000 / bdmrb = h'00000000 / brcr = h'0000
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 875 of 1076 sep 24, 2013 conditions set: independent channel a/channel b mode ? channel a: asid: h'80 / address: h'00027128 / address mask: h'00 bus cycle: cpu, instruction access (pre -instruction-execution), write, word ? channel b: asid: h'70 / address: h'00031415 / address mask: h'00 data: h'00000000 / data mask: h'00000000 bus cycle: cpu, instruction access (pre-instr uction-execution), read (operand size not included in conditions) a user break interrupt is not generated on cha nnel a since the instruction access is not a write cycle. a user break interrupt is not generated on ch annel b since instructio n access is performed on an even address. operand access cycle break condition settings ? register settings: basra = h'80 / bara = h'00123456 / bamra = h'00 / bbra = h'0024 / basrb = h'70/ barb = h'000abcde / bamrb = h'02 / bbrb = h'002a / bdrb = h'0000a512 / bdmrb = h'00000000 / brcr = h'0080 conditions set: independent channel a/channel b mode ? channel a: asid: h'80 / address: h'00123456 / address mask: h'00 bus cycle: operand access, read (operand size not included in conditions) ? channel b: asid: h'70 / address: h'000abcde / address mask: h'02 data: h'0000a512 / data mask: h'00000000 bus cycle: operand access, write, word data break enabled on channel a, a user break interrupt is generated in the event of a longword read at address h'00123454, a word read at address h'00123456, or a byte read at address h'00123456, with asid = h'80. on channel b, a user break interrupt is genera ted when h'a512 is written by word access to any address from h'000ab000 to h'000abffe with asid = h'70.
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 876 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 20.6 user break controller stop function in the SH7750s, this function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. note that, if you use this function, you cannot use the user break controller. this function is not provided in the SH7750. 20.6.1 transition to user break controller stopped state setting the mstp5 bit of the stbcr2 (inside the cpg) to 1 stops the clock supply and causes the user break controller to enter the stopped state. follow steps (1) to (5) below to set the mstp5 bit to 1 and enter the stopped state. (1) initialize bbra and bbrb to 0; (2) initialize brcr to 0; (3) make a dummy read of brcr; (4) read stbcr2, then set the mstp5 bit in the read data to 1 and write back. (5) make two dummy reads of stbcr2. make sure that, if an exception or interrupt occu rs while performing steps (1) to (5), you do not change the values of these registers in the exception handling routine. do not read or write the following registers while the user break controller clock is stopped: bara, bamra, bbra, barb, bamrb, bbrb, bdrb, bdmrb, and brcr. if these registers are read or written, the value cannot be guaranteed. 20.6.2 cancelling the user break controller stopped state the clock supply can be restarted by setting the ms tp5 bit of stbcr2 (inside the cpg) to 0. the user break controller can then be operated again. follow steps (6) and (7) below to clear the mstp5 bit to 0 to cancel the stopped state. (6) read stbcr2, then clear the mstp5 bit in the read data to 0 and write the modified data back; (7) make two dummy reads of stbcr2. as with the transition to the stopped state, if an exception or interrupt occurs while processing steps (6) and (7), make sure that the values in these registers are not changed in the exception handling routine.
SH7750, SH7750s, SH7750r group section 20 user break controller (ubc) r01uh0456ej0702 rev. 7.02 page 877 of 1076 sep 24, 2013 20.6.3 examples of stopping and rest arting the user break controller the following are example programs: ; transition to user break controller stopped state ; (1) initialize bbra and bbrb to 0. mov #0, r0 mov.l #bbra, r1 mov.w r0, @r1 mov.l #bbrb, r1 mov.w r0, @r1 ; (2) initialize brcr to 0. mov.l #brcr, r1 mov.w r0, @r1 ; (3) dummy read brcr. mov.w @r1, r0 ; (4) read stbcr2, then set mstp5 bit in the read data to 1 and write it back mov.l #stbcr2, r1 mov.b @r1, r0 or #h'1, r0 mov.b r0, @r1 ; (5) twice dummy read stbcr2. mov.b @r1, r0 mov.b @r1, r0 ; canceling user break controller stopped state ; (6) read stbcr2, then clear mstp5 bit in the read data to 0 and write it back mov.l #stbcr2, r1 mov.b @r1, r0 and #h'fe, r0 mov.b r0, @r1 ; (7) twice dummy read stbcr2. mov.b @r1, r0 mov.b @r1, r0
section 20 user break controller (ubc) SH7750, SH7750s, SH7750r group page 878 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group section 21 high- performance user debug interface (h-udi) r01uh0456ej0702 rev. 7.02 page 879 of 1076 sep 24, 2013 section 21 high-performan ce user debug interface (h-udi) 21.1 overview 21.1.1 features the high-performance user debug in terface (h-udi) is a serial inpu t/output interface supporting a subset of the jtag, ieee 1149.1, ieee sta ndard test access port and boundary-scan architecture. the SH7750r's h-udi supports bound ary-scan, but is used for emulator connection as well. the functions of this in terface should not be used when using an emulator. refer to the emulator manual for the method of connecting the emulator. the h-udi uses six pins (tck, tms, tdi, tdo, trst , and asebrk /brkack). the pin functions and serial transfer protocol conform to the jtag specifications. 21.1.2 block diagram figure 21.1 shows a block diagram of the h- udi. the tap (test access port) controller and control registers are reset independently of the chip reset pin by driving the trst pin low or setting tms to 1 and applying tck for at least five clock cycles. the other circuits are reset and initialized in an ordinary reset. the h-udi circ uit has four internal registers: sdbpr, sdir, sddrh, and sddrl (these last two together de signated sddr). the sd bpr register supports the jtag bypass mode, sdir is the command regist er, and sddr is the data register. sdir can be accessed directly from the tdi and tdo pins.
section 21 high-performance user debug interface (h-udi) SH7750, SH7750s, SH7750r group page 880 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 sdir sddrh sddrl sdbpr sdbsr mux tck asebrk /brkack tms trst tdi tdo sdint interrupt/reset etc. tap controller break control decoder shift re g ister peripheral module bus * * note: * provided only in the SH7750r. figure 21.1 block di agram of h-udi circuit
SH7750, SH7750s, SH7750r group section 21 high- performance user debug interface (h-udi) r01uh0456ej0702 rev. 7.02 page 881 of 1076 sep 24, 2013 21.1.3 pin configuration table 21.1 shows the h-udi pin configuration. table 21.1 h-udi pins pin name abbreviation i/o function when not used clock pin tck input same as the jtag serial clock input pin. data is transferred from data input pin tdi to the h- udi circuit, and data is read from data output pin tdo, in synchronization with this signal. open * 1 mode pin tms input the mode select input pin. changing this signal in synchronization with tck determines the meaning of the data input from tdi. the protocol conforms to the jtag (ieee std 1149.1) specification. open * 1 reset pin trst input the input pin that resets the h-udi. this signal is received asynchronously with respect to tck, and effects a reset of the jtag interface circuit when low. trst must be driven low for a certain period when powering on, regardless of whether or not jtag is used. this differs from the ieee specification. * 2 * 3 data input pin tdi input the data input pin. data is sent to the h-udi circuit by changing this signal in synchronization with tck. open * 1 data output pin tdo output the data output pin. data is sent to the h-udi circuit by reading this signal in synchronization with tck. open emulator pin asebrk / brkack input/ output dedicated emulator pin open * 1 notes: 1. pulled up inside the chip. when designi ng a board that allows use of an emulator, or when using interrupts and resets via the h- udi, there is no problem in connecting a pullup resistance externally. 2. when designing a board that enables the use of an emulator, or when using interrupts and resets via the h-udi, drive trst low for a period overlapping reset at power-on, and also provide for control by trst alone. 3. fixed to the ground or connected to the same signal line as reset , or to a signal line that behaves in the same way. however, there is a problem when this pin is fixed to the ground. trst is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. the size of this current is determined by the rating of the pull-up resistor. although th is current has no effect on the chip's operation, unnecessary current will be dissipated.
section 21 high-performance user debug interface (h-udi) SH7750, SH7750s, SH7750r group page 882 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 the maximum frequency of tck (tms, tdi, tdo) is 20 mhz. make the tck or cpg setting of this lsi such that the tck frequency is lower than that of this lsi?s on-chip peripheral module clock. 21.1.4 register configuration table 21.2 shows the h-udi regi sters. except for sd bpr, these registers are mapped in the control register space and can be referenced by the cpu. table 21.2 h-udi registers cpu side h-udi side name abbre- viation r/w p4 address area 7 address access size initial value * 1 r/w access size initial value * 1 instruction register sdir r h'fff00000 h'1ff00000 16 h'ffff r/w 32 h'fffffffd (fixed value * 2 ) data register h sddr/ sddrh r/w h'fff00008 h'1ff00008 32/16 unde- fined ? ? ? data register l sddrl r/w h'fff0000a h'1ff0000a 16 unde- fined ? ? ? bypass register sdbpr ? ? ? ? unde- fined r/w 1 ? interrupt source register * 4 sdint r/w h'fff00014 h'1ff00014 16 h'0000 w * 3 32 h'00000000 boundary scan register * 4 sdbsr ? ? ? ? unde- fined r/w ? undefined notes: 1. initialized when the trst pin goes low or when the tap is in the test-logic-reset state. 2. the value read from h-udi is fixed (h'fffffffd). 3. using the h-udi interrupt command, a 1 can be written to the least significant bit. 4. SH7750r only
SH7750, SH7750s, SH7750r group section 21 high- performance user debug interface (h-udi) r01uh0456ej0702 rev. 7.02 page 883 of 1076 sep 24, 2013 21.2 register descriptions 21.2.1 instruction register (sdir) the instruction register (sdir) is a 16-bit register that can only be read by the cpu. in the initial state, bypass mode is set. the value (command) is set from the serial input pin (tdi). sdir is initialized by the trst pin or in the tap test-logic-reset state. when this register is written to from the h-udi, writing is possible regardless of the cpu mode. however, if a read is performed by the cpu while writing is in progress, it may not be possible to read the correct value. in this case, sdir should be read twice, and then read ag ain if the read values do not match. operation is undefined if a reserved command is set in this register. SH7750, SH7750s: bit: 15 14 13 12 11 10 9 8 ti3 ti2 ti1 ti0 ? ? ? ? initial value: 1 1 1 1 1 1 1 1 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 1 1 1 1 1 1 1 1 r/w: r r r r r r r r bits 15 to 12?test instruction bits (ti3 ? ti0) bit 15: ti3 bit 14: ti2 bit 13: ti1 bit 12: ti0 description 0 0 ? ? reserved 1 0 ? reserved 1 0 h-udi reset negate 1 h-udi reset assert 1 0 0 ? reserved 1 ? h-udi interrupt 1 0 ? reserved 1 0 reserved 1 bypass mode (initial value)
section 21 high-performance user debug interface (h-udi) SH7750, SH7750s, SH7750r group page 884 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bits 11 to 0?reserved: these bits are always read as 1, and should only be written with 1. SH7750r: bit: 15 14 13 12 11 10 9 8 ti7 ti6 ti5 ti4 ti3 ti2 ti1 ti0 initial value: 1 1 1 1 1 1 1 1 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 1 1 1 1 1 1 1 1 r/w: r r r r r r r r bits 15 to 8?test instruction bits (ti7?ti0) bit 15: ti7 bit 14: ti6 bit 13: ti5 bit 12: ti4 bit 11: ti3 bit 10: ti2 bit 9: ti1 bit 8: ti0 description 0 0 0 0 0 0 0 0 extest 0 0 0 0 0 1 0 0 sample/preload 0 1 1 0 ? ? ? ? h-udi reset negate 0 1 1 1 ? ? ? ? h-udi reset assert 1 0 1 ? ? ? ? ? h-udi interrupt 1 1 1 1 1 1 1 1 bypass mode (initial value) other than above reserved bits 7 to 0?reserved: these bits are always read as 1, and should only be written with 1.
SH7750, SH7750s, SH7750r group section 21 high- performance user debug interface (h-udi) r01uh0456ej0702 rev. 7.02 page 885 of 1076 sep 24, 2013 21.2.2 data register (sddr) the data register (sddr) is a 32-bit register , comprising the two 16-bit registers sddrh and sddrl, that can be read and written to by the cpu. the value in this register is not initialized by a trst or cpu reset. bit: 31 30 29 28 27 26 25 24 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w legend: * : undefined bits 31 to 0?dr data: these bits store the sddr value.
section 21 high-performance user debug interface (h-udi) SH7750, SH7750s, SH7750r group page 886 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 21.2.3 bypass register (sdbpr) the bypass register (sdbpr) is a one-bit register that cannot be accessed by the cpu. when bypass mode is set in sdir, sdbpr is connected between the tdi pin and tdo pin of the h-udi. 21.2.4 interrupt source register (sdint) (SH7750r only) the interrupt source register (sdint) is a 16-bit re gister that can be read from and written to by the cpu. from the h-udi pins, the intreq bit is set to 1 when a h-udi interrupt command is set in the sdir register (update-ir). while sdir is holding a h-udi interrupt command, the sdint register is connected between the tdi and tdo pins of the h-udi, allowing it to be read as a 32- bit register. in this case, the upper 16 bits will a ll be 0, and the lower 16 bits will represent sdint. from the cpu, only writing a 0 to the intreq bit is possible. while this bit holds a 1, the interrupt requests continue to be issued, so this bit should always be cleared in the interrupt handler. this register is initialized in the test-logic-reset state of trst or tap. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? intreq initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bits 15 to 1?reserved: these bits are always read as 0. wh en writing, only 0s should be written here. bit 0 ? interrupt request (intreq): indicates whether or not an interrupt request has been issued by an h-udi interrupt command. from the cpu, the interrupt request can be cleared by writing a 0 to this bit. if a 1 is written to this bit, it retains the value it had before the write operation.
SH7750, SH7750s, SH7750r group section 21 high- performance user debug interface (h-udi) r01uh0456ej0702 rev. 7.02 page 887 of 1076 sep 24, 2013 21.2.5 boundary scan register (sdbsr) (SH7750r only) the boundary scan register (sdbsr) is a shift regi ster that is placed on the pads to control the chip's i/o pins. this register can perform a boundary scan test equivalent to the jtag (ieee std 1149.1) standard using extest, sample, an d preload commands. table 21.3 shows the relationship between the SH7750r's pins and the boundary scan register.
section 21 high-performance user debug interface (h-udi) SH7750, SH7750s, SH7750r group page 888 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 21.3 configuration of the boundary scan register no. pin name type no. pin na me type no. pin name type to tdo 309 a19 out 272 d48 out 345 ckio2enb in 308 a18 ctl 271 d62 in 344 md6/ iois16 in 307 a18 out 270 d62 ctl 343 status1 ctl 306 sck2/ mreset in 269 d62 out 342 status1 out 305 sck2/ mreset ctl 268 d49 in 341 status0 ctl 304 sck2/ mreset out 267 d49 ctl 340 status0 out 303 md7/txd in 266 d49 out 339 a1 ctl 302 md7/txd ctl 265 d61 in 338 a1 out 301 md7/txd out 264 d61 ctl 337 a0 ctl 300 md8/rts2 in 263 d61 out 336 a0 out 299 md8/rts2 ctl 262 d50 in 335 dack1 ctl 298 md8/rts2 out 261 d50 ctl 334 dack1 out 297 tclk in 260 d50 out 333 dack0 ctl 296 tclk ctl 259 d60 in 332 dack0 out 295 tclk out 258 d60 ctl 331 md5/ ras2 in 294 cts2 in 257 d60 out 330 md5/ ras2 ctl 293 cts2 ctl 256 d51 in 329 md5/ ras2 out 292 cts2 out 255 d51 ctl 328 md4/ ce2b in 291 nmi in 254 d51 out 327 md4/ ce2b ctl 290 irl3 in 253 d59 in 326 md4/ ce2b out 289 irl2 in 252 d59 ctl 325 md3/ ce2a in 288 irl1 in 251 d59 out 324 md3/ ce2a ctl 287 irl0 in 250 d52 in 323 md3/ ce2a out 286 md2/rxd2 in 249 d52 ctl 322 a25 ctl 285 md1/txd2 in 248 d52 out 321 a25 out 284 md1/txd2 ctl 247 d58 in 320 a24 ctl 283 md1/txd2 out 246 d58 ctl 319 a24 out 282 md0/sck in 245 d58 out 318 a23 ctl 281 md0/sck ctl 244 d53 in 317 a23 out 280 md0/sck out 243 d53 ctl 316 a22 ctl 279 rd/ wr2 ctl 242 d53 out 315 a22 out 278 rd/ wr2 out 241 d57 in 314 a21 ctl 277 d63 in 240 d57 ctl 313 a21 out 276 d63 ctl 239 d57 out 312 a20 ctl 275 d63 out 238 d54 in 311 a20 out 274 d48 in 237 d54 ctl 310 a19 ctl 273 d48 ctl 236 d54 out
SH7750, SH7750s, SH7750r group section 21 high- performance user debug interface (h-udi) r01uh0456ej0702 rev. 7.02 page 889 of 1076 sep 24, 2013 no. pin name type no. pin na me type no. pin name type 235 d56 in 196 d21 in 157 drak1 out 234 d56 ctl 195 d21 ctl 156 a2 ctl 233 d56 out 194 d21 out 155 a2 out 232 d55 in 193 d25 in 154 a3 ctl 231 d55 ctl 192 d25 ctl 153 a3 out 230 d55 out 191 d25 out 152 a4 ctl 229 d31 in 190 dreq1 in 151 a4 out 228 d31 ctl 189 dreq0 in 150 a5 ctl 227 d31 out 188 rxd in 149 a5 out 226 d16 in 187 d22 in 148 a6 ctl 225 d16 ctl 186 d22 ctl 147 a6 out 224 d16 out 185 d22 out 146 a7 ctl 223 d30 in 184 d24 in 145 a7 out 222 d30 ctl 183 d24 ctl 144 a8 ctl 221 d30 out 182 d24 out 143 a8 out 220 d17 in 181 d23 in 142 a9 ctl 219 d17 ctl 180 d23 ctl 141 a9 out 218 d17 out 179 d23 out 140 a10 ctl 217 d29 in 178 we7 / cas7 /dqm7/ reg ctl 139 a10 out 216 d29 ctl 177 we7 / cas7 /dqm7/ reg out 138 a11 ctl 215 d29 out 176 we6 / cas6 /dqm6 ctl 137 a11 out 214 d18 in 175 we6 / cas6 /dqm6 out 136 a12 ctl 213 d18 ctl 174 we3 / cas3 /dqm3/ iciowr ctl 135 a12 out 212 d18 out 173 we3 / cas3 /dqm3/ iciowr out 134 a13 ctl 211 d28 in 172 we2 / cas2 /dqm2/ iciord ctl 133 a13 out 210 d28 ctl 171 we2 / cas2 /dqm2/ iciord out 132 a14 ctl 209 d28 out 170 rd/ wr ctl 131 a14 out 208 d19 in 169 rd/ wr out 130 a15 ctl 207 d19 ctl 168 rd / cass / frame ctl 129 a15 out 206 d19 out 167 rd / cass / frame out 128 a16 ctl 205 d27 in 166 ras ctl 127 a16 out 204 d27 ctl 165 ras out 126 a17 ctl 203 d27 out 164 cs2 ctl 125 a17 out 202 d20 in 163 cs2 out 124 we0 / cas0 /dqm0 ctl 201 d20 ctl 162 cs3 ctl 123 we0 / cas0 /dqm0 out 200 d20 out 161 cs3 out 122 we1 / cas1 /dqm1 ctl 199 d26 in 160 drak0 ctl 121 we1 / cas1 /dqm1 out 198 d26 ctl 159 drak0 out 120 we4 / cas4 /dqm4 ctl 197 d26 out 158 drak1 ctl 119 we4 / cas4 /dqm4 out
section 21 high-performance user debug interface (h-udi) SH7750, SH7750s, SH7750r group page 890 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 no. pin name type no. pin na me type no. pin name type 118 we5 / cas5 /dqm5 ctl 78 d13 in 38 d35 ctl 117 we5 / cas5 /dqm5 out 77 d13 ctl 37 d35 out 116 cke ctl 76 d13 out 36 d44 in 115 cke out 75 d1 in 35 d44 ctl 114 d7 in 74 d1 ctl 34 d44 out 113 d7 ctl 73 d1 out 33 d34 in 112 d7 out 72 d14 in 32 d34 ctl 111 d8 in 71 d14 ctl 31 d34 out 110 d8 ctl 70 d14 out 30 d45 in 109 d8 out 69 d0 in 29 d45 ctl 108 breq / bsack in 68 d0 ctl 28 d45 out 107 back / bsreq ctl 67 d0 out 27 d33 in 106 back / bsreq out 66 d15 in 26 d33 ctl 105 d6 in 65 d15 ctl 25 d33 out 104 d6 ctl 64 d15 out 24 d46 in 103 d6 out 63 d39 in 23 d46 ctl 102 d9 in 62 d39 ctl 22 d46 out 101 d9 ctl 61 d39 out 21 d32 in 100 d9 out 60 d40 in 20 d32 ctl 99 d5 in 59 d40 ctl 19 d32 out 98 d5 ctl 58 d40 out 18 d47 in 97 d5 out 57 d38 in 17 d47 ctl 96 d10 in 56 d38 ctl 16 d47 out 95 d10 ctl 55 d38 out 15 rd2 ctl 94 d10 out 54 d41 in 14 rd2 out 93 d4 in 53 d41 ctl 13 bs ctl 92 d4 ctl 52 d41 out 12 bs out 91 d4 out 51 d37 in 11 cs6 ctl 90 d11 in 50 d37 ctl 10 cs6 out 89 d11 ctl 49 d37 out 9 cs5 ctl 88 d11 out 48 d42 in 8 cs5 out 87 d3 in 47 d42 ctl 7 cs4 ctl 86 d3 ctl 46 d42 out 6 cs4 out 85 d3 out 45 d36 in 5 cs1 ctl 84 d12 in 44 d36 ctl 4 cs1 out 83 d12 ctl 43 d36 out 3 cs0 ctl 82 d12 out 42 d43 in 2 cs0 out 81 d2 in 41 d43 ctl 1 rdy in 80 d2 ctl 40 d43 out from tdi 79 d2 out 39 d35 in note: ctl is an active-low signal. the relevant pin is driven to the out state when ctl is set low.
SH7750, SH7750s, SH7750r group section 21 high- performance user debug interface (h-udi) r01uh0456ej0702 rev. 7.02 page 891 of 1076 sep 24, 2013 21.3 operation 21.3.1 tap control figure 21.2 shows the internal states of the tap control circuit. thes e conform to the state transitions specified by jtag. ? the transition condition is the tms value at the rising edge of tck. ? the tdi value is sampled at the rising edge of tck, and shifted at the falling edge. ? the tdo value changes at the falling edge of tck. when not in the shift-dr or shift-ir state, tdo is in the high-impedance state. ? in a transition to trst = 0, a transition is made to the test-logic-reset state asynchronously with respect to tck. 1 0 0 0 run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr test-lo g ic-reset 0 11 1 0 0 1 0 1 1 1 1 0 0 0 0 select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 0 0 1 0 1 1 1 1 0 0 figure 21.2 tap control state transition diagram
section 21 high-performance user debug interface (h-udi) SH7750, SH7750s, SH7750r group page 892 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 21.3.2 h-udi reset a power-on reset is effected by an sdir command . a reset is effected by sending an h-udi reset assert command, and then sending an h-udi reset negate command, from the h-udi pin (see figure 21.3). the interval required between the h-udi reset assert command and the h-udi reset negate command is the same as the length of time the reset pin is held low in order to effect a power-on reset. h-udi pin chip internal reset cpu state h-udi reset assert normal h-udi reset ne g ate reset processin g reset figure 21.3 h-udi reset 21.3.3 h-udi interrupt the h-udi interrupt function generates an interrupt by setting a command value in sdir from the h-udi. the h-udi interrupt is of general exception /interrupt operation type, with a branch to an address based on vbr and return effected by me ans of an rte instructio n. the exception code stored in control register intevt in this case is h'600. the priority of the h-udi interrupt can be controlled with bits 3 to 0 of control register iprc. in the SH7750 or SH7750s, the h-udi interrupt re quest signal is asserted for about eight cycles of the lsi's on-chip peripheral clock after the comm and is set. the number of cycles for assertion is determined by the ratio of tck to the frequency of the on-chip peripheral clock. since the period of assertion is limited , the cpu may miss a request. in the SH7750r, the h-udi interrupt request signal is asserted when the intreq bit in the sdint register is set to 1 afte r the command is set (update-ir). the interrupt request signal will not be negated unless a 0 is written to the intreq bit by software; therefore, the cpu will not miss a request. as long as the h-udi interrupt command is set in sdir, the sdint register is connected between the tdi and tdo pins. note that, in the SH7750 or SH7750s, the h- udi interrupt command au tomatically becomes a bypass command immediately after it has been set. in the SH7750r, the command is not changed
SH7750, SH7750s, SH7750r group section 21 high- performance user debug interface (h-udi) r01uh0456ej0702 rev. 7.02 page 893 of 1076 sep 24, 2013 except by the following operations: update in the update-ir state, initialization in the test-logic- reset state, and initialization by assertion of trst . 21.3.4 boundary scan (extest, sample/pr eload, bypass) (SH7750r only) in the SH7750r, setting a command from the h-udi in sdir ca n place the h-udi pins in the boundary scan mode. however, the following limitations apply. 1. boundary scan does not cover clock-related signals (extal, extal2, xtal, xtal2, and ckio). 2. boundary scan does not cover reset-related signals ( reset , ca) 3. boundary scan does not cover h-udi-related signals (tck, tdi, tdo, tms, trst ). 4. with extest, assert the mreset pin (low), the reset pin (low), and ca pin (high). with sample/preload, assert the ca pin (high). 5. to perform boundary scan, supply a clock to the extal pin, and wait for the power-on oscillation settling time to elapse before starting boundary scan. the frequency range of the input clock is from 1 to 33.3 mhz. note that after the power-on oscillation settling time has elapsed, a clock does not need to be supplied to the extal pin any longer. for details on the power-on oscillation settling time, see section 22, electrical characteristics. 21.4 usage notes 1. sdir command once an sdir command has been set, it remains unchanged until initialization by asserting trst or placing the tap in the test-logic-reset state, or until another command (other than an h-udi interrupt command) is written from the h-udi. 2. sdir commands in sleep mode sleep mode is cleared by an h- udi interrupt or h-udi reset, and these exception requests are accepted in this mode. in standby mode, neithe r an h-udi interrupt nor an h-udi reset is accepted. 3. in standby mode, the h-udi function cannot be used. furthermore, tck must be retained at a high level when entering the standby mode in order to retain the tap state before and after standby mode. 4. the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when an emulator is used. 5. the h-udi pins of the SH7750 and SH7750s must not be connected to a boundary-scan signal loop on the board.
section 21 high-performance user debug interface (h-udi) SH7750, SH7750s, SH7750r group page 894 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 6. in bypass mode on the SH7750 or SH7750s, the contents of the bypass register (sdbpr) are undefined in the capture-dr state. on the SH7750r, sdbpr has a value of 0.
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 895 of 1076 sep 24, 2013 section 22 electrical characteristics 22.1 absolute maximum ratings table 22.1 absolute maximum ratings item symbol value unit i/o, pll, rtc, cpg power supply voltage v ddq v dd-pll1/2 v dd-rtc v dd-cpg ?0.3 to 4.2, ?0.3 to 4.6 * 1 v internal power supply voltage v dd ?0.3 to 2.5, ?0.3 to 2.1 * 1 v input voltage v in ?0.3 to v ddq +0.3 v operating temperature t opr ?20 to 75, ?40 to 85 * 2 c storage temperature t stg ?55 to 125 c notes: permanent damage to the chip may re sult if the maximum ratings are exceeded. permanent damage to the chip may result if all v ss pins are not connected to gnd. for information on the power-on and power-off procedures, refer to appendix h, power-on and power-off procedures. 1. hd6417750r only 2. hd6417750rba240hv only
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 896 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 22.2 dc characteristics table 22.2 dc characteristics (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba240hv) t a = ?20 to +75 c* 3 item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.4 1.5 1.6 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 230 580 ick = 240 mhz sleep mode ? ? 120 ma ? ? 400 t a = 25 c * 1 current dissipation standby mode i dd ? ? 800 a t a > 50 c * 1 normal operation ? 170 215 sleep mode ? 35 40 ma ick = 240 mhz, bck = 120 mhz ? ? 440 t a = 25 c * 1 current dissipation standby mode i ddq ? ? 880 a t a > 50 c * 1 ? 15 25 rtc on * 2 rtc current dissipation standby mode i dd-rtc 3 5 a rtc off reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 input leakage current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 897 of 1076 sep 24, 2013 item symbol min typ max unit test conditions three-state leakage current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and connect v ss-cpg , v ss-pll1/2 , and v ss-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the total current value for the 3.3 v versions of v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg . 1. rcr2.rtcen must be set to 1 to reduce the leak current in the standby mode. (there is no need to input a clock from extal2.) 2. rtcon refers to the status in which rcr2 .rtcen is set to 1 and a clock is being input to extal2. 3. t a = ?40 to 85c for the hd6417750rba240hv.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 898 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.3 dc characteristics (hd6417750rf240 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.4 1.5 1.6 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 230 580 sleep mode ? ? 120 ma ick = 240 mhz ? ? 400 t a = 25 c * 1 current dissipation standby mode i dd ? ? 800 a t a > 50 c * 1 normal operation ? 140 180 sleep mode ? 35 40 ma ick = 240 mhz, bck = 80 mhz ? ? 440 t a = 25 c * 1 current dissipation standby mode i ddq ? ? 880 a t a > 50 c * 1 ? 15 25 rtc on * 2 rtc current dissipation standby mode i dd-rtc 3 5 a rtc off reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 input leakage current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leakage current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 899 of 1076 sep 24, 2013 item symbol min typ max unit test conditions v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the total current value for the 3.3 v versions of v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg . 1. rcr2.rtcen must be set to 1 to reduce the leak current in the standby mode. (there is no need to input a clock from extal2.) 2. rtcon refers to the status in which rcr2 .rtcen is set to 1 and a clock is being input to extal2.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 900 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.4 dc characteristics (hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba240hv* 3 ) t a = ?20 to +75 c* 4 item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.35 1.5 1.6 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 190 480 sleep mode ? ? 100 ma ick = 200 mhz ? ? 400 t a = 25 c * 1 current dissipation standby mode i dd ? ? 800 a t a > 50 c * 1 normal operation ? 140 180 sleep mode ? 30 35 ma ick = 200 mhz, bck = 100 mhz ? ? 440 t a = 25 c * 1 current dissipation standby mode i ddq ? ? 880 a t a > 50 c * 1 ? 15 25 rtc on * 2 rtc current dissipation standby mode i dd-rtc 3 5 a rtc off reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 input leakage current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leakage current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 901 of 1076 sep 24, 2013 item symbol min typ max unit test conditions v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and connect v ss-cpg , v ss-pll1/2 , and v ss-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-rtc , and v dd-cpg 3.3 v system currents. 1. rcr2.rtcen must be set to 1 to reduce the leak current in the standby mode. (there is no need to input a clock from extal2.) 2. rtcon refers to the status in which rcr2 .rtcen is set to 1 and a clock is being input to extal2. 3. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 4. t a = ?40 to 85c for the hd6417750rba240hv.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 902 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.5 dc characteristics (hd6417750rf200 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.35 1.5 1.6 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 190 480 sleep mode ? ? 100 ma ick = 200 mhz ? ? 400 t a = 25 c * 1 current dissipation standby mode i dd ? ? 800 a t a > 50 c * 1 normal operation ? 140 180 sleep mode ? 30 35 ma ick = 200 mhz, bck = 67 mhz ? ? 440 t a = 25 c * 1 current dissipation standby mode i ddq ? ? 880 a t a > 50 c * 1 ? 15 25 rtc on * 2 rtc current dissipation standby mode i dd-rtc 3 5 a rtc off reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 input leakage current all input pins |iin| ? ? 1 a v in = 0.5 to v ddq ?0.5 v three-state leakage current i/o, all output pins (off state) |isti| ? ? 1 a v in = 0.5 to v ddq ?0.5 v
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 903 of 1076 sep 24, 2013 item symbol min typ max unit test conditions v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. 1. rcr2.rtcen must be set to 1 to reduce the leak current in the standby mode. (there is no need to input a clock from extal2.) 2. rtcon refers to the status in which rcr2 .rtcen is set to 1 and a clock is being input to extal2.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 904 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.6 dc characteristics (hd6417750sbp200 (v), hd6417750sba200v) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.8 1.95 2.07 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 410 780 sleep mode ? 165 210 ma ick = 200 mhz ? ? 2000 t a = 25 c (rtc on * ) current dissipation standby mode i dd ? ? 5000 a t a > 50 c (rtc on * ) normal operation ? 140 180 sleep mode ? 40 50 ma ick = 200 mhz, bck = 100 mhz ? ? 2200 t a = 25 c (rtc on * ) current dissipation standby mode i ddq ? ? 5500 a t a > 50 c (rtc on * ) rtc current dissipation during rtc operation i dd-rtc ? 15 25 a rtc input clock: 32.768 khz power is supplied only to v dd-rtc reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 905 of 1076 sep 24, 2013 item symbol min typ max unit test conditions pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. * to reduce the leakage current in standby mo de, the rtc must be turned on (input the clock from extal2 and set rcr2.rtcen to 1).
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 906 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.7 dc characteristics (hd6417750sf200 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.8 1.95 2.07 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 410 780 sleep mode ? 165 210 ma ick = 200 mhz ? ? 2000 t a = 25 c (rtc on * ) current dissipation standby mode i dd ? ? 5000 a t a > 50 c (rtc on * ) normal operation ? 140 180 sleep mode ? 40 50 ma ick = 200 mhz, bck = 67 mhz ? ? 2200 t a = 25 c (rtc on * ) current dissipation standby mode i ddq ? ? 5500 a t a > 50 c (rtc on * ) rtc current dissipation during rtc operation i dd-rtc ? 15 25 a rtc input clock: 32.768 khz power is supplied only to v dd-rtc reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 907 of 1076 sep 24, 2013 item symbol min typ max unit test conditions pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. * to reduce the leakage current in standby mo de, the rtc must be turned on (input the clock from extal2 and set rcr2.rtcen to 1).
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 908 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.8 dc characteristics (hd6417750bp200m (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.8 1.95 2.07 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 1000 1200 sleep mode ? 165 ? ma ick = 200 mhz ? ? 2000 t a = 25 c (rtc on * ) current dissipation standby mode i dd ? ? 5000 a t a > 50 c (rtc on * ) normal operation ? 160 200 sleep mode ? 40 ? ma ick = 200 mhz, bck = 100 mhz ? ? 2200 t a = 25 c (rtc on * ) current dissipation standby mode i ddq ? ? 5500 a t a > 50 c (rtc on * ) reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 909 of 1076 sep 24, 2013 notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. * to reduce the leakage current in standby mo de, the rtc must be turned on (input the clock from extal2 and set rcr2.rtcen to 1).
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 910 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.9 dc characteristics (hd6417750sf167 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.6 1.8 2.0 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 320 650 sleep mode ? 120 150 ma ick = 167 mhz ? 50 400 t a = 25 c (rtc on * ) current dissipation standby mode i dd ? 100 800 a t a > 50 c (rtc on * ) normal operation ? 140 180 sleep mode ? 40 50 ma ick = 167 mhz, bck = 84 mhz ? 110 440 t a = 25 c (rtc on * ) current dissipation standby mode i ddq ? 220 880 a t a > 50 c (rtc on * ) rtc current dissipation during rtc operation i dd-rtc ? 15 45 a rtc input clock: 32.768 khz power is supplied only to v dd-rtc reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 911 of 1076 sep 24, 2013 item symbol min typ max unit test conditions pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. * to reduce the leakage current in standby mo de, the rtc must be turned on (input the clock from extal2 and set rcr2.rtcen to 1).
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 912 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.10 dc characteristics (hd6417750f167 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.6 1.8 2.0 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 630 700 sleep mode ? 120 ? ma ick = 167 mhz ? ? 400 t a = 25 c (rtc on * ) current dissipation standby mode i dd ? ? 800 a t a > 50 c (rtc on * ) normal operation ? 160 200 sleep mode ? 40 ? ma ick = 167 mhz, bck = 84 mhz ? ? 440 t a = 25 c (rtc on * ) current dissipation standby mode i ddq ? ? 880 a t a > 50 c (rtc on * ) reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 913 of 1076 sep 24, 2013 notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. * to reduce the leakage current in standby mo de, the rtc must be turned on (input the clock from extal2 and set rcr2.rtcen to 1).
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 914 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.11 dc characteristics (hd6417750svf133 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.4 1.5 1.7 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 210 520 sleep mode ? 50 60 ma ick = 133 mhz, bck = 67 mhz ? ? 100 t a = 25 c (rtc on * ) current dissipation standby mode i dd ? ? 200 a t a > 50 c (rtc on * ) normal operation ? 80 160 sleep mode ? 35 40 ma ick = 133 mhz, bck = 67 mhz ? ? 110 t a = 25 c (rtc on * ) current dissipation standby mode i ddq ? ? 220 a t a > 50 c (rtc on * ) rtc current dissipation during rtc operation i dd-rtc ? 15 25 a rtc input clock: 32.768 khz power is supplied only to v dd-rtc reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 915 of 1076 sep 24, 2013 item symbol min typ max unit test conditions pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. * to reduce the leakage current in standby mo de, the rtc must be turned on (input the clock from extal2 and set rcr2.rtcen to 1).
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 916 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.12 dc characteristics (hd6417750svbt133 (v)) t a = ?30 to +70 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.4 1.5 1.7 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? 210 520 sleep mode ? 50 60 ma ick = 133 mhz, bck = 66 mhz ? ? 100 t a = 25 c (rtc on * ) current dissipation standby mode i dd ? ? 200 a t a > 50 c (rtc on * ) normal operation ? 80 160 sleep mode ? 35 40 ma ick = 133 mhz, bck = 67 mhz ? ? 110 t a = 25 c (rtc on * ) current dissipation standby mode i ddq ? ? 220 a t a > 50 c (rtc on * ) rtc current dissipation during rtc operation i dd-rtc ? 15 45 a rtc input clock: 32.768 khz power is supplied only to v dd-rtc reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 917 of 1076 sep 24, 2013 item symbol min typ max unit test conditions pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. * to reduce the leakage current in standby mo de, the rtc must be turned on (input the clock from extal2 and set rcr2.rtcen to 1).
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 918 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.13 dc characteristics (hd6417750vf128 (v)) t a = ?20 to +75 c item symbol min typ max unit test conditions v ddq v dd-pll1/2 v dd-cpg v dd-rtc 3.0 3.3 3.6 v normal mode, sleep mode, deep sleep mode, standby mode power supply voltage v dd 1.4 1.5 1.7 normal mode, sleep mode, deep sleep mode, standby mode normal operation ? ? 520 sleep mode ? ? 60 ma ick = 128 mhz, bck = 64 mhz ? ? 100 t a = 25 c (rtc on * ) current dissipation standby mode i dd ? ? 200 a t a > 50 c (rtc on * ) normal operation ? ? 160 sleep mode ? ? 40 ma ick = 128 mhz, bck = 64 mhz ? ? 110 t a = 25 c (rtc on * ) current dissipation standby mode i ddq ? ? 220 a t a > 50 c (rtc on * ) reset , nmi, trst v ih v ddq 0.9 ? v ddq + 0.3 v other input pins 2.0 ? v ddq + 0.3 reset , nmi, trst v il ?0.3 ? v ddq 0.1 input voltage other input pins ?0.3 ? v ddq 0.2 v oh 2.4 ? ? v i oh = ?2 ma output voltage all output pins v ol ? ? 0.55 i ol = 2 ma pull-up resistance all pull-up resistance r pull 20 60 180 k pin capacitance all pins c l ? ? 10 pf
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 919 of 1076 sep 24, 2013 notes: connect v dd-pll1/2 , v dd-rtc , and v dd-cpg to v ddq , and v ss-cpg , v ss-pll1/2 , and v ssq-rtc to gnd, regardless of whether or not t he pll circuits and rtc are used. the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unloaded. i ddq is the sum of the v ddq , v dd-pll1/2 , v dd-rtc , and v dd-cpg 3.3 v system currents. * to reduce the leakage current in standby mo de, the rtc must be turned on (input the clock from extal2 and set rcr2.rtcen to 1). table 22.14 permissible output currents t a = ?20 to +75 c item symbol min typ max unit permissible output low current (per pin) i ol ? ? 2 ma permissible output low current (total) i ol ? ? 120 permissible output high current (per pin) ?i oh ? ? 2 permissible output high current (total) (?i oh ) ? ? 40 note: to protect chip reliability, do not exc eed the output current values in table 22.14.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 920 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 22.3 ac characteristics in principle, this lsi input should be synchronous. unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. table 22.15 clock timing (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba240hv) item symbol min typ max unit cpu, fpu, cache, tlb 1 ? 240 external bus 1 ? 120 operating frequency peripheral modules f 1 ? 60 mhz table 22.16 clock timing (hd6417750rf240 (v)) item symbol min typ max unit cpu, fpu, cache, tlb 1 ? 240 external bus 1 ? 84 operating frequency peripheral modules f 1 ? 60 mhz table 22.17 clock timing (hd6417750bp200m (v), hd6417750sbp200 (v), hd6417750sba200v*, hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba240hv*) item symbol min typ max unit cpu, fpu, cache, tlb 1 ? 200 external bus 1 ? 100 operating frequency peripheral modules f 1 ? 50 mhz note: * this is the case when the device in us e is an hd6417750rba240hv running at 200 mhz. table 22.18 clock timing (hd6417750rf200 (v)) item symbol min typ max unit cpu, fpu, cache, tlb 1 ? 200 external bus 1 ? 84 operating frequency peripheral modules f 1 ? 50 mhz
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 921 of 1076 sep 24, 2013 table 22.19 clock timing (hd6417750sf200 (v)) item symbol min typ max unit cpu, fpu, cache, tlb 1 ? 200 external bus 1 ? 67 operating frequency peripheral modules f 1 ? 50 mhz table 22.20 clock timing (hd6417750f167 (v), hd6417750sf167 (v)) item symbol min typ max unit cpu, fpu, cache, tlb f 1 ? 167 external bus 1 ? 84 operating frequency peripheral modules 1 ? 42 mhz table 22.21 clock timing (hd6417750svf133 (v), hd6417750svbt133 (v)) item symbol min typ max unit cpu, fpu, cache, tlb 1 ? 134 external bus 1 ? 67 operating frequency peripheral modules f 1 ? 34 mhz table 22.22 clock timing (hd6417750vf128 (v)) item symbol min typ max unit cpu, fpu, cache, tlb 1 ? 128 external bus 1 ? 64 operating frequency peripheral modules f 1 ? 32 mhz
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 922 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 22.3.1 clock and control signal timing table 22.23 clock and control signal timing (hd6417750rbp240 (v), hd6417750rbg240 (v), hd6417750rba240hv) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c* 2 , c l = 30 pf item symbol min max unit figure pll1 6-times/pll2 operation f ex 16 34 mhz extal clock input frequency pll1 12-times/pll2 operation f ex 14 20 pll1/pll2 not operating f ex 1 34 extal clock input cycle time t excyc 30 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll1/pll2 operating f op 25 120 mhz ckio clock output pll1/pll2 not operating f op 1 34 mhz ckio clock output cycle time t cyc 8.3 1000 ns 22.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2 (1) ckio clock output rise time t ckor ? 3 ns 22.2 (1) ckio clock output fall time t ckof ? 3 ns 22.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2 (2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12 reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 923 of 1076 sep 24, 2013 item symbol min max unit figure pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 3 ? ms 22.4, 22.6 standby return oscillation settling time 2 t osc3 3 ? ms 22.7 standby return oscillation settling time 3 t osc4 3 ? ms 22.8 standby return oscillation settling time 1 * 1 t osc2 2 ? ms standby return oscillation settling time 2 * 1 t osc3 2 ? ms standby return oscillation settling time 3 * 1 t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. 1. when the oscillation settling time of a cryst al resonator is lower than or equal to 1 ms. 2. t a = ?40 to 85c for the hd6417750rba240hv.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 924 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.24 clock and control signal timing (hd6417750rf240 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c, c l = 30 pf item symbol min max unit figure pll1 6-times/pll2 operation f ex 16 34 mhz pll1 12-times/pll2 operation f ex 14 20 extal clock input frequency pll1/pll2 not operating f ex 1 34 extal clock input cycle time t excyc 30 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll1/pll2 operating f op 25 84 mhz ckio clock output pll1/pll2 not operating f op 1 34 mhz ckio clock output cycle time t cyc 11.9 1000 ns 22.2(1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2(1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2(1) ckio clock output rise time t ckor ? 3 ns 22.2(1) ckio clock output fall time t ckof ? 3 ns 22.2(1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2(2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2(2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12 reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11 pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 3 ? ms 22.4, 22.6
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 925 of 1076 sep 24, 2013 item symbol min max unit figure standby return oscillation settling time 2 t osc3 3 ? ms 22.7 standby return oscillation settling time 3 t osc4 3 ? ms 22.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. * when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 926 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.25 clock and control signal timing (hd6417750rbp200 (v), hd6417750rbg200 (v), hd6417750rba240hv* 2 ) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c* 3 , c l = 30 pf item symbol min max unit figure pll1 6-times/pll2 operation f ex 16 34 mhz extal clock input frequency pll1 12-times/pll2 operation f ex 14 17 pll1/pll2 not operating f ex 1 34 extal clock input cycle time t excyc 30 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll1/pll2 operating f op 25 100 mhz ckio clock output pll1/pll2 not operating f op 1 100 mhz ckio clock output cycle time t cyc 10 1000 ns 22.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2 (1) ckio clock output rise time t ckor ? 3 ns 22.2 (1) ckio clock output fall time t ckof ? 3 ns 22.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2 (2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12 reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11 pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 5 ? ms 22.4, 22.6
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 927 of 1076 sep 24, 2013 item symbol min max unit figure standby return oscillation settling time 2 t osc3 5 ? ms 22.7 standby return oscillation settling time 3 t osc4 5 ? ms 22.8 standby return oscillation settling time 1 * 1 t osc2 2 ? ms standby return oscillation settling time 2 * 1 t osc3 2 ? ms standby return oscillation settling time 3 * 1 t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. 1. when the oscillation settling time of a cryst al resonator is lower than or equal to 1 ms. 2. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 3. t a = ?40 to 85c for the hd6417750rba240hv.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 928 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.26 clock and control signal timing (hd6417750rf200 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c, c l = 30 pf item symbol min max unit figure pll1 6-times/pll2 operation f ex 16 34 mhz extal clock input frequency pll1 12-times/pll2 operation f ex 14 17 pll1/pll2 not operating f ex 1 34 extal clock input cycle time t excyc 30 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll1/pll2 operating f op 25 84 mhz ckio clock output pll1/pll2 not operating f op 1 34 mhz ckio clock output cycle time t cyc 11.9 1000 ns 22.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2 (1) ckio clock output rise time t ckor ? 3 ns 22.2 (1) ckio clock output fall time t ckof ? 3 ns 22.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2 (2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12 reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11 pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 5 ? ms 22.4, 22.6
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 929 of 1076 sep 24, 2013 item symbol min max unit figure standby return oscillation settling time 2 t osc3 5 ? ms 22.7 standby return oscillation settling time 3 t osc4 5 ? ms 22.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. * when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 930 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.27 clock and control signal timing (hd6417750bp200m (v), hd6417750sbp200 (v), hd6417750sba200v) v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75 c, c l = 30 pf item symbol min max unit figure 1/2 divider operating f ex 16 67 mhz pll2 operating 1/2 divider not operating f ex 8 34 1/2 divider operating f ex 2 67 extal clock input frequency pll2 not operating 1/2 divider not operating f ex 1 34 extal clock input cycle time t excyc 15 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll2 operating f op 25 100 mhz ckio clock output pll2 not operating f op 1 100 mhz ckio clock output cycle time t cyc 10 1000 ns 22.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2 (1) ckio clock output rise time t ckor ? 3 ns 22.2 (1) ckio clock output fall time t ckof ? 3 ns 22.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2 (2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 931 of 1076 sep 24, 2013 item symbol min max unit figure reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11 pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 10 ? ms 22.4, 22.6 standby return oscillation settling time 2 t osc3 5 ? ms 22.7 standby return oscillation settling time 3 t osc4 5 ? ms 22.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. * when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 932 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.28 clock and control sign al timing (hd6417750sf200 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75 c, c l = 30 pf item symbol min max unit figure 1/2 divider operating f ex 16 67 mhz pll2 operating 1/2 divider not operating f ex 8 34 1/2 divider operating f ex 2 67 extal clock input frequency pll2 not operating 1/2 divider not operating f ex 1 34 extal clock input cycle time t excyc 15 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll2 operating f op 25 67 mhz ckio clock output pll2 not operating f op 1 67 mhz ckio clock output cycle time t cyc 10 1000 ns 22.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2 (1) ckio clock output rise time t ckor ? 3 ns 22.2 (1) ckio clock output fall time t ckof ? 3 ns 22.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2 (2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12 reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 933 of 1076 sep 24, 2013 item symbol min max unit figure pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 10 ? ms 22.4, 22.6 standby return oscillation settling time 2 t osc3 5 ? ms 22.7 standby return oscillation settling time 3 t osc4 5 ? ms 22.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. * when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 934 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.29 clock and control signal timing (hd6417750f167 (v), hd6417750sf167 (v)) hd6417750sf167 (v), hd6417750f167 (v): v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75 c, c l = 30 pf item symbol min max unit figure 1/2 divider operating f ex 16 56 mhz pll2 operating 1/2 divider not operating f ex 8 28 1/2 divider operating f ex 2 56 extal clock input frequency pll2 not operating 1/2 divider not operating f ex 1 28 extal clock input cycle time t excyc 18 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll2 operating f op 25 84 mhz ckio clock output pll2 not operating f op 1 84 mhz ckio clock output cycle time t cyc 12 1000 ns 22.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2 (1) ckio clock output rise time t ckor ? 3 ns 22.2 (1) ckio clock output fall time t ckof ? 3 ns 22.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2 (2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 935 of 1076 sep 24, 2013 item symbol min max unit figure reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11 pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 10 ? ms 22.4, 22.6 standby return oscillation settling time 2 t osc3 5 ? ms 22.7 standby return oscillation settling time 3 t osc4 5 ? ms 22.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. * when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 936 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.30 clock and control signal timing (hd6417750svf133 (v), hd6417750svbt133 (v)) hd6417750svbt133 (v): v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?30 to +70 c, c l = 30 pf hd6417750svf133 (v): v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c, c l = 30 pf item symbol min max unit figure 1/2 divider operating f ex 16 45 mhz pll2 operating 1/2 divider not operating f ex 8 23 1/2 divider operating f ex 2 45 extal clock input frequency pll2 not operating 1/2 divider not operating f ex 1 23 extal clock input cycle time t excyc 22 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll2 operating f op 25 67 mhz ckio clock output pll2 not operating f op 1 67 mhz ckio clock output cycle time t cyc 14 1000 ns 22.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2 (1) ckio clock output rise time t ckor ? 3 ns 22.2 (1) ckio clock output fall time t ckof ? 3 ns 22.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2 (2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 937 of 1076 sep 24, 2013 item symbol min max unit figure reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11 pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 10 ? ms 22.4, 22.6 standby return oscillation settling time 2 t osc3 5 ? ms 22.7 standby return oscillation settling time 3 t osc4 5 ? ms 22.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. * when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 938 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.31 clock and control signal timing (hd6417750vf128 (v)) v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75 c, c l = 30 pf item symbol min max unit figure 1/2 divider operating f ex 16 43 mhz pll2 operating 1/2 divider not operating f ex 8 22 1/2 divider operating f ex 2 43 extal clock input frequency pll2 not operating 1/2 divider not operating f ex 1 22 extal clock input cycle time t excyc 23 1000 ns 22.1 extal clock input low-level pulse width t exl 3.5 ? ns 22.1 extal clock input high-level pulse width t exh 3.5 ? ns 22.1 extal clock input rise time t exr ? 4 ns 22.1 extal clock input fall time t exf ? 4 ns 22.1 pll2 operating f op 25 64 mhz ckio clock output pll2 not operating f op 1 64 mhz ckio clock output cycle time t cyc 15 1000 ns 22.2 (1) ckio clock output low-level pulse width t ckol1 1 ? ns 22.2 (1) ckio clock output high-level pulse width t ckoh1 1 ? ns 22.2 (1) ckio clock output rise time t ckor ? 3 ns 22.2 (1) ckio clock output fall time t ckof ? 3 ns 22.2 (1) ckio clock output low-level pulse width t ckol2 3 ? ns 22.2 (2) ckio clock output high-level pulse width t ckoh2 3 ? ns 22.2 (2) power-on oscillation settling time t osc1 10 ? ms 22.3, 22.5 power-on oscillation settling time/mode settling t oscmd 10 ? ms 22.3, 22.5 sck2 reset setup time t sck2rs 20 ? ns 22.11 sck2 reset hold time t sck2rh 20 ? ns 22.3, 22.5, 22.11 md reset setup time t mdrs 3 ? t cyc 22.12 md reset hold time t mdrh 20 ? ns 22.3, 22.5, 22.12 reset assert time t resw 20 ? t cyc 22.3, 22.4, 22.5, 22.6, 22.11
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 939 of 1076 sep 24, 2013 item symbol min max unit figure pll synchronization settling time t pll 200 ? s 22.9, 22.10 standby return oscillation settling time 1 t osc2 10 ? ms 22.4, 22.6 standby return oscillation settling time 2 t osc3 5 ? ms 22.7 standby return oscillation settling time 3 t osc4 5 ? ms 22.8 standby return oscillation settling time 1 * t osc2 2 ? ms standby return oscillation settling time 2 * t osc3 2 ? ms standby return oscillation settling time 3 * t osc4 2 ? ms irl interrupt determination time (rtc used, standby mode) t irlstb ? 200 s 22.10 trst reset hold time t trstrh 0 ? ns 22.3, 22.5 notes: when a crystal resonator is connect ed to extal and xtal, the maximum frequency is 34 mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. the maximum load capacitance to be connected to ckio pin should be 50 pf in pll2 operation, because there is a feedback from ckio pin. * when the oscillation settling time of a crystal resonator is lower than or equal to 1 ms.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 940 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 t excyc t exh t exl t exr t exf 1/2v ddq v ih v ih v il v il v ih 1/2v ddq note: when the clock is input from the extal pin figure 22.1 extal clock input timing t cyc t ckoh1 t ckol1 t ckor t ckof 1/2v ddq v oh v oh v ol v ol v oh 1/2v ddq figure 22.2 (1) ckio clock output timing t ckoh2 t ckol2 1.5 v 1.5 v 1.5 v figure 22.2 (2) ckio clock output timing
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 941 of 1076 sep 24, 2013 ckio, internal clock vdd md8, md7, md2?md0 reset sck2 trst t osc1 v dd min t sck2rh t mdrh t oscmd t trstrh stable oscillation t resw notes: 1. oscillation settlin g time when on-chip oscillator is used 2. pll2 not operatin g figure 22.3 power-on oscillation settling time reset t resw t osc2 standby stable oscillation ckio, internal clock notes: 1. oscillation settlin g time when on-chip oscillator is used 2. pll2 not operatin g figure 22.4 standby return osc illation settling time (return by reset )
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 942 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 internal clock vdd md8, md7, md2?md0 reset sck2 trst t osc1 v dd min t sck2rh t mdrh t oscmd t trstrh stable oscillation t resw ckio notes: 1. oscillation settlin g time when on-chip oscillator is used 2. pll2 operatin g figure 22.5 power-on oscillation settling time reset t resw t osc2 ckio stable oscillation standby internal clock notes: 1. oscillation settlin g time when on-chip oscillator is used 2. pll2 operatin g figure 22.6 standby return osci llation settling time (return by reset )
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 943 of 1076 sep 24, 2013 ckio, internal clock nmi stable oscillation standby t osc3 note: oscillation settlin g time when on-chip oscillator is used figure 22.7 standby return oscilla tion settling time (return by nmi) irl3 to irl0 t osc4 standby stable oscillation ckio, internal clock note: oscillation settlin g time when on-chip oscillator is used figure 22.8 standby return osc illation settling time (return by irl3 to irl0 )
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 944 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 extal input pll output, ckio output internal clock status1, status0 note: when external clock from extal is input stable input clock normal standby normal t pll 2 stable input clock reset or nmi interrupt request pll synchronization pll synchronization figure 22.9 pll synchronization settling time in case of reset or nmi interrupt irl3 ? irl0 interrupt request t irlstb status1, status0 note: when external clock from extal is input normal standby normal t pll 2 extal input pll output, ckio output internal clock stable input clock stable input clock pll synchronization pll synchronization figure 22.10 pll synchronization settling time in case of irl interrupt
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 945 of 1076 sep 24, 2013 ckio sck2 reset t sck2rs t sck2rh t resw bus idle figure 22.11 manual reset input timing reset t mdrs t mdrh md6?md3 figure 22.12 mode input timing
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 946 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 22.3.2 control signal timing table 22.32 control signal timing hd6417750r bp240 (v) hd6417750r bg240 (v) hd6417750r ba240hv hd6417750r bp200 (v) hd6417750r bg200 (v) hd6417750r ba240hv * 5 hd6417750r f240 (v) hd6417750r f200 (v) * 1 * 1 * 1 * 1 item symbol min max min max min max min max unit figure breq setup time t breqs 2 ? 2.5 ? 3.5 ? 3.5 ? ns 22.13 breq hold time t breqh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 22.13 back delay time t backd ? 5.3 ? 6 ? 6 ? 6 ns 22.13 bus tri-state delay time t boff1 ? 12 ? 12 ? 12 ? 12 ns 22.13 bus tri-state delay time to standby mode t boff2 ? 2 ? 2 ? 2 ? 2 t cyc 22.14 (2) bus buffer on time t bon1 ? 12 ? 12 ? 12 ? 12 ns 22.13 bus buffer on time from standby t bon2 ? 2 ? 2 ? 2 ? 2 t cyc 22.14 (2) status0/1 delay time t std1 ? 6 ? 6 ? 6 ? 6 ns 22.14 (1) t std2 ? 2 ? 2 ? 2 ? 2 t cyc 22.14 (1), (2) t std3 ? 2 ? 2 ? 2 ? 2 t cyc 22.14 (2)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 947 of 1076 sep 24, 2013 table 22.33 control signal timing hd6417750v f128 (v) hd6417750 svf133 (v) hd6417750s vbt133 (v) hd6417750f 167 (v) hd6417750s f167 (v) hd6417750s f200 (v) hd6417750b p200m (v) hd6417750s bp200 (v) hd6417750s ba200v * 2 * 2 * 3 * 4 item symbol min max min max min max min max unit figure breq setup time t breqs 3.5 ? 3.5 ? 3.5 ? 3 ? ns 22.13 breq hold time t breqh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 22.13 back delay time t backd ? 10 ? 10 ? 8 ? 6 ns 22.13 bus tri-state delay time t boff1 ? 15 ? 15 ? 12 ? 10 ns 22.13 bus tri-state delay time to standby mode t boff2 ? 2 ? 2 ? 2 ? 2 t cyc 22.14 (2) bus buffer on time t bon1 ? 12 ? 12 ? 12 ? 12 ns 22.13 bus buffer on time from standby t bon2 ? 2 ? 2 ? 2 ? 2 t cyc 22.14 (2) status0/1 delay time t std1 ? 6 ? 6 ? 6 ? 6 ns 22.14 (1) t std2 ? 2 ? 2 ? 2 ? 2 t cyc 22.14 (1), (2) t std3 ? 2 ? 2 ? 2 ? 2 t cyc 22.14 (2) notes: 1. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c * 6 , c l = 30 pf, pll2 on 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 3. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 4. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 5. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 6. t a = ?40 to 85c for the hd6417750rba240hv.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 948 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 a[25-0], csn , bs , rd/ wr , ce2a , ce2b , rd/ wr2 , ras , ras2 , wen , rd rd2 t breqs t breqh ckio breq back t breqs t breqh t backd t boff1 t bon1 t backd figure 22.13 control signal timing t std1 ckio status1, status0 reset or sleep normal normal t std2 normal operation reset or sleep mode normal operation figure 22.14 (1) pin drive ti ming for reset or sleep mode
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 949 of 1076 sep 24, 2013 t std3 t bon2 ckio status1, status0 csn , rd , rd/ wr , wen , bs , ras , ce2a , ce2b , casn dackn, drakn, sck, txd, txd2, cts2 , rts2 a25 ? a0, d31 ? d0 t boff2 software standby normal normal t std2 normal operation normal operation software standby mode note: * these pins can be put into the state od hi g h-impedance with stbcr. * figure 22.14 (2) pin drive timi ng for software standby mode
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 950 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 22.3.3 bus timing table 22.34 bus timing (1) hd6417750r bp240 (v) hd6417750r bg240 (v) hd6417750r ba240hv hd6417750r bp200 (v) hd6417750r bg200 (v) hd6417750r ba240hv * 2 hd6417750r f240 (v) hd6417750r f200 (v) * 1 * 1 * 1 * 1 item symbol min max min max min max min max unit notes address delay time t ad 1.5 5.3 1.5 6 1.5 6 1.5 6 ns bs delay time t bsd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns cs delay time t csd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns rw delay time t rwd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns rd delay time t rsd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns read data setup time t rds 2 ? 2.5 ? 3.5 ? 3.5 ? ns read data hold time t rdh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns we delay time (falling edge) t wedf ? 5.3 ? 6 ? 6 ? 6 ns relative to ckio falling edge we delay time t wed1 1.5 5.3 1.5 6 1.5 6 1.5 6 ns write data delay time t wdd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns rdy setup time t rdys 2 ? 2.5 ? 3.5 ? 3.5 ? ns rdy hold time t rdyh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns ras delay time t rasd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns cas delay time 1 t casd1 1.5 5.3 1.5 6 1.5 6 1.5 6 ns dram cas delay time 2 t casd2 1.5 5.3 1.5 6 1.5 6 1.5 6 ns sdram cke delay time t cked 1.5 5.3 1.5 6 1.5 6 1.5 6 ns sdram dqm delay time t dqmd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns sdram frame delay time t fmd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns mpx iois16 setup time t io16s 2 ? 2.5 ? 3.5 ? 3.5 ? ns pcmcia iois16 hold time t io16h 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns pcmcia iciowr delay time (falling edge) t icwsdf 1.5 5.3 1.5 6 1.5 6 1.5 6 ns pcmcia
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 951 of 1076 sep 24, 2013 hd6417750r bp240 (v) hd6417750r bg240 (v) hd6417750r ba240hv hd6417750r bp200 (v) hd6417750r bg200 (v) hd6417750r ba240hv * 2 hd6417750r f240 (v) hd6417750r f200 (v) * 1 * 1 * 1 * 1 item symbol min max min max min max min max unit notes iciord delay time t icrsd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns pcmcia dack delay time t dacd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns dack delay time (falling edge) t dacdf 1.5 5.3 1.5 6 1.5 6 1.5 6 ns relative to ckio falling edge dtr setup time t dtrs 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns dtr hold time t dtrh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns dbreq setup time t dbqs 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns dbreq hold time t dbqh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns tr setup time t trs 2.0 ? 2.5 ? 3.5 ? 3.5 ? ns tr hold time t trh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns bavl delay time t bavd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns tdack delay time t tdad 1.5 5.3 1.5 6 1.5 6 1.5 6 ns id1, id0 delay time t idd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns notes: 1. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c * 3 , c l = 30 pf, pll2 on 2. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 3. t a = ?40 to 85c for the hd6417750rba240hv.
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 952 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.35 bus timing (2) hd6417750 svf133 (v) hd6417750 svbt133 (v) hd6417750 sf167 (v) hd6417750 sf200 (v) hd6417750 sbp200 (v) hd6417750 sba200v * 1 * 2 * 3 item symbol min max min max min max unit notes address delay time t ad 1.5 10 1.5 8 1.5 6 ns bs delay time t bsd 1.5 10 1.5 8 1.5 6 ns cs delay time t csd 1.5 10 1.5 8 1.5 6 ns rw delay time t rwd 1.5 10 1.5 8 1.5 6 ns rd delay time t rsd 1.5 10 1.5 8 1.5 6 ns read data setup time t rds 3.5 ? 3.5 ? 3 ? ns read data hold time t rdh 1.5 ? 1.5 ? 1.5 ? ns we delay time (falling edge) t wedf ? 10 ? 8 ? 6 ns relative to ckio falling edge we delay time t wed1 1.5 10 1.5 8 1.5 6 ns write data delay time t wdd 1.5 10 1.5 8 1.5 6 ns rdy setup time t rdys 3.5 ? 3.5 ? 3 ? ns rdy hold time t rdyh 1.5 ? 1.5 ? 1.5 ? ns ras delay time t rasd 1.5 10 1.5 8 1.5 6 ns cas delay time 1 t casd1 1.5 10 1.5 8 1.5 6 ns dram cas delay time 2 t casd2 1.5 10 1.5 8 1.5 6 ns sdram cke delay time t cked 1.5 10 1.5 8 1.5 6 ns sdram dqm delay time t dqmd 1.5 10 1.5 8 1.5 6 ns sdram frame delay time t fmd 1.5 10 1.5 8 1.5 6 ns mpx iois16 setup time t io16s 3.5 ? 3.5 ? 3 ? ns pcmcia iois16 hold time t io16h 1.5 ? 1.5 ? 1.5 ? ns pcmcia iciowr delay time (falling edge) t icwsdf 1.5 10 1.5 8 1.5 6 ns pcmcia iciord delay time t icrsd 1.5 10 1.5 8 1.5 6 ns pcmcia dack delay time t dacd 1.5 10 1.5 8 1.5 6 ns dack delay time (falling edge) t dacdf 1.5 10 1.5 8 1.5 6 ns relative to ckio falling edge
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 953 of 1076 sep 24, 2013 hd6417750 svf133 (v) hd6417750 svbt133 (v) hd6417750 sf167 (v) hd6417750 sf200 (v) hd6417750 sbp200 (v) hd6417750 sba200v * 1 * 2 * 3 item symbol min max min max min max unit notes dtr setup time t dtrs 3.5 ? 3.5 ? 3 ? ns dtr hold time t dtrh 1.5 ? 1.5 ? 1.5 ? ns dbreq setup time t dbqs 3.5 ? 3.5 ? 3 ? ns dbreq hold time t dbqh 1.5 ? 1.5 ? 1.5 ? ns tr setup time t trs 3.5 ? 3.5 ? 3 ? ns tr hold time t trh 1.5 ? 1.5 ? 1.5 ? ns bavl delay time t bavd 1.5 10 1.5 8 1.5 6 ns tdack delay time t tdad 1.5 10 1.5 8 1.5 6 ns id1, id0 delay time t idd 1.5 10 1.5 8 1.5 6 ns notes: 1. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 2. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 3. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 954 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.36 bus timing (3) hd6417750 vf128 (v) hd6417750 f167 (v) hd6417750 bp200m (v) * 1 * 2 * 3 item symbol min max min max min max unit notes address delay time t ad 1.3 10 1.3 8 1.2 6 ns bs delay time t bsd 1.3 10 1.3 8 1.2 6 ns cs delay time t csd 1.3 10 1.3 8 1.2 6 ns rw delay time t rwd 1.3 10 1.3 8 1.2 6 ns rd delay time t rsd 1.3 10 1.3 8 1.2 6 ns read data setup time t rds 3.5 ? 3.5 ? 3 ? ns read data hold time t rdh 1.5 ? 1.5 ? 1.5 ? ns we delay time (falling edge) t wedf ? 10 ? 8 ? 6 ns relative to ckio falling edge we delay time t wed1 1.3 10 1.3 8 1.2 6 ns write data delay time t wdd 1.3 10 1.3 8 1.2 6 ns rdy setup time t rdys 3.5 ? 3.5 ? 3 ? ns rdy hold time t rdyh 1.5 ? 1.5 ? 1.5 ? ns ras delay time t rasd 1.3 10 1.3 8 1.2 6 ns cas delay time 1 t casd1 1.3 10 1.3 8 1.2 6 ns dram cas delay time 2 t casd2 1.3 10 1.3 8 1.2 6 ns sdram cke delay time t cked 0.5 10 0.5 8 0.5 6 ns sdram dqm delay time t dqmd 1.3 10 1.3 8 1.2 6 ns sdram frame delay time t fmd 1.3 10 1.3 8 1.2 6 ns mpx iois16 setup time t io16s 3.5 ? 3.5 ? 3 ? ns pcmcia iois16 hold time t io16h 1.5 ? 1.5 ? 1.5 ? ns pcmcia iciowr delay time (falling edge) t icwsdf 1.3 10 1.3 8 1.2 6 ns pcmcia iciord delay time t icrsd 1.3 10 1.3 8 1.2 6 ns pcmcia dack delay time t dacd 1.3 10 1.3 8 1.2 6 ns dack delay time (falling edge) t dacdf 1.3 10 1.3 8 1.2 6 ns relative to ckio falling edge
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 955 of 1076 sep 24, 2013 hd6417750 vf128 (v) hd6417750 f167 (v) hd6417750 bp200m (v) * 1 * 2 * 3 item symbol min max min max min max unit notes dtr setup time t dtrs 3.5 ? 3.5 ? 3 ? ns dtr hold time t dtrh 1.5 ? 1.5 ? 1.5 ? ns dbreq setup time t dbqs 3.5 ? 3.5 ? 3 ? ns dbreq hold time t dbqh 1.5 ? 1.5 ? 1.5 ? ns tr setup time t trs 3.5 ? 3.5 ? 3 ? ns tr hold time t trh 1.5 ? 1.5 ? 1.5 ? ns bavl delay time t bavd 1.3 10 1.3 8 1.2 6 ns tdack delay time t tdad 1.3 10 1.3 8 1.2 6 ns id1, id0 delay time t idd 1.3 10 1.3 8 1.2 6 ns notes: 1. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 2. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 3. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 956 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 t1 t ad t ad t2 ckio a25 ? a0 csn rd/ wr rd d63 ? d0 (read) d63 ? d0 (write) bs dackn (da) t wdd t wdd t wdd t rdh t rds t csd t csd t rwd t rwd t rsd t rsd t rsd t wed1 t wedf t wedf t bsd t bsd t dacd t dacd t dacd t dacd t dacdf t dacdf t dacd rdy wen le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) dackn (sa: io memory) figure 22.15 sram bus cycl e: basic bus cycle (no wait)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 957 of 1076 sep 24, 2013 t wdd t wdd t wdd t dacdf t dacdf ckio a25 ? a0 csn rd/ wr rd d63 ? d0 (read) d63 ? d0 (write) bs dackn (da) rdy wen t1 t ad tw t2 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t rdyh t rdys t bsd t bsd t dacd t dacd t dacd t dacd t dacd dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.16 sram bus cycle: ba sic bus cycle (one internal wait)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 958 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 t wdd t wdd t wdd t dacdf t dacdf ckio a25?a0 csn rd/ wr rd d63?d0 (read) d63?d0 (write) bs dackn (da) rdy wen t1 t ad tw twe t2 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t rdyh t rdys t rdyh t rdys t bsd t bsd t dacd t dacd t dacd t dacd t dacd dackn (sa: io memory) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.17 sram bus cycle: basic bus cycle (one internal wait + one external wait)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 959 of 1076 sep 24, 2013 t wdd t wdd t wdd t dacdf t dacdf t dacd t dacd t dacd ts1 t ad t1 t2 th1 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t bsd t bsd t dacd t dacd ckio a25 ? a0 csn rd/ wr rd d63 ? d0 (read) d63 ? d0 (write) bs dackn (sa: io memory) dackn (sa: io memory) dackn (da) rdy wen * le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h note: * SH7750r only figure 22.18 sram bus cycle: basic bus cycle (no wait, addres s setup/hold time insertion, ans = 1, anh = 1)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 960 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio a25?a5 t1 t2 csn rd/ wr rd d63?d0 (read) bs rdy a4?a0 tb2 tb1 tb2 tb1 tb2 tb1 t csd t ad t rwd t bsd t rds t bsd t rsd t rsd t rdh t ad t ad t csd t rwd t rdh t rsd t rds dackn (sa: io memory) dackn (da) t dacd t dacd t dacd t dacd t dacd legend: io: dack device sa: single address dma transfer da: dual address dma transfer dack set to active-high figure 22.19 burst rom bus cycle (no wait)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 961 of 1076 sep 24, 2013 t1 t2 tb2 tb1 tb2 tb1 tb2 tb1 twb twb twb twe tw t ad t csd t rsd t rdh t rds t bsd t ad t rdh t rsd t rds t ad t csd t rdyh t rdys t rdyh t rdys t rdyh t rdys t dacd t dacd t dacd t dacd t rwd t rwd ckio a25?a5 csn rd/ wr rd d63?d0 (read) bs rdy a4?a0 dackn (sa: io memory) dackn (da) legend: io: dack device sa: single address dma transfer da: dual address dma transfer dack set to active-high figure 22.20 burst rom bus cycle (1st data: one internal wait + one external wait; 2nd/3rd/4th data: one internal wait)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 962 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 t1 tb2 t csd t rwd t bsd t rds t bsd t rsd t ad ts1 t dacd tb1 tb2 t ad t rdh t dacd t dacd tb1 tb2 t2 tb1 t ad t csd t rwd t rdh t rsd t rds th1 ts1 th1 ts1 th1 ts1 th1 ckio a25?a5 csn rd/ wr rd d63?d0 (read) bs rdy a4?a0 dackn (sa: io memory) dackn (da) legend: io: dack device sa: single address dma transfer da: dual address dma transfer dack set to active-high t dacd t dacd figure 22.21 burst rom bus cycle (no wait, address setup/hold time insertion, ans = 1, anh = 1)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 963 of 1076 sep 24, 2013 tw t1 twe tb2 tb1 twb twbe tb1 tb2 twb twbe twb t2 tb2 twbe tb1 ckio a25?a5 a4?a0 d63?d0 (read) t ad t ad t ad t rdh t rds t rdh t rds bs rdy dackn (da) legend: io: dack device sa: single address dma transfer da: dual address dma transfer dack set to active-high rd t dacd t dacd t dacd t bsd t bsd t bsd t bsd t rsd t rsd csn t rwd t csd t rwd t csd t dacd t dacd t rsd rd/ wr t rdyh t rdys t rdyh t rdys t rdyh t rdys t rdyh t rdys dackn (sa: io memory) figure 22.22 burst rom bus cycle (one internal wait + one external wait)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 964 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 trw tr tc1 tc2 tc3 tc4/td1 td2 td4 td3 tpc tpc tpc ckio bank prechar g e-sel d63?d0 (read) address row row row h/l column t ad t ad t ad t rdh d0 t rds dqmn d63?d0 (write) bs cke t wdd t wdd ras t casd2 t casd2 t casd2 cass t dacd t dacd t dacd t rasd t rasd t dqmd t dqmd csn t rwd t bsd t bsd rd/ wr t csd t csd dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h t rwd figure 22.23 synchronous dram auto -precharge read bus cycle: single (rcd[1:0] = 01, cas latency = 3, tpc[2:0] = 011)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 965 of 1076 sep 24, 2013 trw tr tc1 tc2 tc3 tc4/td1 td2 td4 td3 tpc tpc tpc ckio bank prechar g e-sel d63?d0 (read) address t ad row row h/l c0 row t ad t rdh d0 d1 d2 d3 t rds dqmn d63?d0 (write) bs cke t wdd t wdd ras t casd2 t casd2 t casd2 cass t dacd t dacd t dacd t rasd t rasd t dqmd t dqmd csn t rwd t bsd t bsd rd/ wr t csd t csd t ad dackn (sa: io memory) t rwd le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.24 synchronous dram au to-precharge read bus cycle: burst (rcd[1:0] = 01, cas latency = 3, tpc[2:0] = 011)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 966 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tr trw tc1 tc2 tc3 tc4/td1 td3 td2 td4 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs cke t ad row row h/l row c0 t ad t rwd t rwd t ad t rdh t rds d0 d1 d2 d3 t csd t csd t rwd t rwd t rasd t rasd t bsd t bsd t dqmd t dqmd t dacd t dacd t wdd t wdd t dacd t casd2 t casd2 t casd2 d63?d0 (read) d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.25 synchronous dram normal read bus cycle: act + read commands, burst (rasd = 1, rcd[1:0] = 01, cas latency = 3)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 967 of 1076 sep 24, 2013 tpr tpc tr trw tc1 tc2 tc3 tc4/td1 td3 td2 td4 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs cke t ad row row h/l row c0 t ad t ad t ad t rdh t rds d0 d1 d2 d3 t csd t csd t rwd t rwd t rasd t rasd t rasd t rasd t bsd t bsd t dqmd t dacd t dacd t wdd t wdd t dacd t casd2 t casd2 t casd2 t dqmd d63?d0 (read) d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.26 synchronous dram normal read bus cycle: pre + act + read commands, burst ((rasd = 1, rcd[1:0] = 01, tpc[2:0] = 001, cas latency = 3)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 968 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tc1 tc2 tc3 tc4/td1 td3 td2 td4 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs cke t ad row t ad h/l c0 t rdh t rds d0 d1 d2 d3 t csd t csd t rwd t rwd t rasd t rasd t bsd t bsd t dqmd t dqmd t casd2 t casd2 t dacd t dacd t wdd t wdd t dacd d63?d0 (read) d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.27 synchronous dram normal read bus cycle: read command, burst ((rasd = 1, cas latency = 3)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 969 of 1076 sep 24, 2013 trw tr tc1 tc2 tc3 tc4 trwl trwl tpc ckio bank prechar g e-sel address t ad t ad t ad h/l column row row row t wdd c0 t wdd dqmn bs cke t wdd ras t casd2 t casd2 t casd2 cass t dacd t dacd t rwd t rwd t rasd t rasd t dqmd t dqmd csn t bsd t bsd rd/ wr t csd t csd d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.28 synchronous dram auto -precharge write bus cycle: single (rcd[1:0] = 01, tpc[2:0] = 001, trwl[2:0] = 010)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 970 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 trw tr tc1 tc2 tc3 tc4 trwl trwl tpc ckio bank prechar g e-sel address t ad t ad t ad h/l c0 row row row t wdd d0 t wdd d1 d2 d3 dqmn bs cke t wdd ras t casd2 t casd2 t casd2 cass t dacd t dacd t rwd t rwd t rasd t rasd t dqmd t dqmd csn t bsd t bsd rd/ wr t csd t csd d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.29 synchronous dram au to-precharge write bus cycle: burst (rcd[1:0] = 01, tpc[2:0] = 001, trwl[2:0] = 010)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 971 of 1076 sep 24, 2013 trw tr tc1 tc2 tc3 tc4 trwl trwl ckio bank prechar g e-sel address t ad t ad t ad h/l c0 row row row t wdd d0 t wdd d1 d2 d3 dqmn bs cke t wdd ras t casd2 t casd2 t casd2 cass t dacd t dacd t rwd t rwd t rasd t rasd t dqmd t dqmd csn t bsd t bsd rd/ wr t csd t csd d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.30 synchronous dram normal write bus cycle: act + write commands, burst (rasd = 1, rcd[1:0] = 01, trwl[2:0] = 010)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 972 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 trw tr tpc tpr tc1 tc2 tc3 tc4 trwl trwl ckio bank prechar g e-sel address t ad t ad t ad h/l h/l c0 row row row row t ad t wdd d0 t wdd d1 d2 d3 dqmn bs cke t wdd ras t casd2 t casd2 t casd2 cass t dqmd t dqmd t dacd t rwd t rwd t rwd t rwd t rasd t rasd t rasd t rasd t dacd t dacd csn t bsd t bsd rd/ wr t csd t csd d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.31 synchronous dram normal write bus cycle: pre + act + write commands, burst (rasd = 1, rcd[1:0] = 01, tpc[2:0] = 001, trwl[2:0] = 010)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 973 of 1076 sep 24, 2013 (tnop) tnop tc1 tc2 tc3 tc4 trwl trwl t ad t ad h/l c0 row t wdd d0 t wdd d1 d2 d3 t wdd t dqmd t dqmd t dacd t rwd t rwd t casd2 t casd2 t dacd t bsd t bsd t csd t csd ckio bank prechar g e-sel address dqmn bs cke ras cass csn rd/ wr d63?d0 (write) dackn (sa: io memory) normal write sa-dma le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h note: in the case of sa-dma only, the (tnop) cycle is inserted, and the dackn si g nal is output as shown by the solid line. in a normal write, the (tnop) cycle is omitted and the dackn si g nal is output as shown by the dotted line. figure 22.32 synchronous dram normal write bus cycle: write command, burst (rasd = 1, trwl[2:0] = 010)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 974 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tpc tpr ckio bank prechar g e-sel address t ad t ad h/l row dqmn bs cke ras t casd2 t casd2 cass t dqmd t dqmd t rwd t rwd dackn t rasd t rasd t dacd t dacd csn t bsd t wdd t wdd rd/ wr t csd t csd d63?d0 (write) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.33 synchronous dram bus cycle: synchronou s dram precharge command (rasd = 1, tpc[2:0] = 001)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 975 of 1076 sep 24, 2013 trr1 trr2 trr3 trr4 trrw trr5 trc trc trc ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs dackn le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h cke t ad t ad t rwd t rwd t dqmd t dqmd t bsd t dacd t wdd t wdd t casd2 t casd2 t casd2 t casd2 t rasd t rasd t rasd t rasd t csd t csd t csd t csd t dacd d63?d0 (write) figure 22.34 synchronous dram bus cy cle: synchronous dram auto-refresh (tras = 1, trc[2:0] = 001)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 976 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs dackn le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h cke trs1 trs2 trs3 trs4 trs5 trc trc trc t ad t ad t rwd t dqmd t dqmd t dacd t dacd t wdd t wdd t casd2 t casd2 t casd2 t cked t cked t rasd t rasd t rasd t rasd t csd t csd t csd t csd d63?d0 (write) t rwd t casd2 t bsd figure 22.35 synchronous dram bus cy cle: synchronous dram self-refresh (trc[2:0] = 001)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 977 of 1076 sep 24, 2013 trp1 trp2 trp3 trp4 tmw tmw2 tmw4 tmw3 tmw5 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs dackn le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h cke t ad t ad t ad t rwd t rwd t rwd t csd t csd t csd t bsd t dqmd t dacd t wdd t wdd t dacd t casd2 t casd2 t casd2 t casd2 t rasd t rasd t rasd t dqmd d63?d0 (write) figure 22.36 (a) synchronous dram bus cycle: synchronous dram mode register setting (pall)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 978 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 trp1 trp2 trp3 trp4 tmw tmw2 tmw4 tmw3 tmw5 ckio bank prechar g e-sel address csn rd/ wr ras cass dqmn bs dackn le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h cke t ad t ad t ad t rwd t rwd t rwd t csd t csd t csd t bsd t dqmd t dacd t wdd t wdd t dacd t casd2 t casd2 t casd2 t casd2 t rasd t rasd t rasd t dqmd d63?d0 (write) figure 22.36 (b) synchronous dram bus cycle: synchronous dram mode register setting (set)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 979 of 1076 sep 24, 2013 tr2 tr1 trw tc1 tcw tc2 tpc tpc t ad t ad t ad row column t wdd t wdd t wdd t casd1 t casd1 t casd1 t bsd t bsd t dacd t dacd t dacd t csd t csd t dacd t dacd t dacd t rwd t rwd t rasd t rasd t rasd t rdh t rds ckio a25?a0 bs ras casn csn rd/ wr tr2 tr1 tc1 tc2 tpc t ad t ad t ad row column t wdd t wdd t wdd t casd1 t casd1 t casd1 t bsd t bsd t dacd t dacd t dacd t csd t csd t dacd t dacd t dacd t rwd t rwd t rasd t rasd t rasd t rdh t rds (1) (2) dackn (sa: io memory) dackn (sa: io memory) d63?d0 (read) d63?d0 (write) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.37 d ram bus cycles (1) rcd[1:0] = 00, anw[2:0] = 000, tpc[2:0] = 001 (2) rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 010
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 980 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tr2 t1r tc1 tc2 tce tpc ckio t ad t ad t ad row column bs t wdd ras t rasd t rasd t rasd casn csn t rwd t casd1 t casd1 t casd1 t bsd t bsd rd/ wr t csd t csd t dacd t dacd t rdh t rds a25?a0 dackn (sa: io memory) d63?d0 (read) d63?d0 (write) t rwd le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.38 d ram bus cycle (edo mode, rcd[1:0] = 00, anw[2:0] = 000, tpc[2:0] = 001)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 981 of 1076 sep 24, 2013 tr2 t1r tc1 tc2 tc1 tc2 tc1 tc1 tc2 tc2 tce tpc t ad t ad t ad t ad row c0 c1 c2 c3 t wdd t rasd t rasd t rasd t rwd t rwd t casd1 t casd1 t casd1 t casd1 t bsd t bsd t bsd t bsd t dacd t csd t csd t dacd t dacd t rwd t rdh t rds d0 t rdh t rds d3 d2 d1 ckio bs ras casn csn rd/ wr a25?a0 dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h d63?d0 (read) d63?d0 (write) figure 22.39 dram burst bus cycle (edo mode, rcd[1:0] = 00, anw[2:0] = 000, tpc[2:0] = 001)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 982 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tr2 tr1 trw tc1 tcw tc2 tc1 tc2 tcw tc1 tcw tc1 tc2 tce tpc tcw tc2 ckio t ad t ad t ad t rdh d0 t rds t rdh d3 d2 d1 t rds bs ras t rasd t rasd csn casn row c0 c1 c2 c3 rd/ wr t csd t csd t casd1 t casd1 t casd1 t casd1 t rasd t casd1 t casd1 t bsd t bsd t dacd t dacd t dacd t rwd t rwd t wdd a25?a0 dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h d63?d0 (read) d63?d0 (write) figure 22.40 dram burst bus cycle (edo mode, rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 001)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 983 of 1076 sep 24, 2013 tr2 tr1 trw tc1 tcw tc2 tcnw tcw tc1 tc2 tc2 tcw tcnw tc1 tcw tcnw tc1 tc2 tcnw tce tpc ckio t ad t ad t ad t rdh d0 t rds t rdh d3 d2 d1 t rds bs ras t rasd t rasd csn casn row c0 c1 c2 c3 rd/ wr t csd t csd t casd1 t casd1 t casd1 t rasd t casd1 t casd1 t bsd t bsd t dacd t dacd t dacd t rwd t rwd t wdd a25?a0 dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h d63?d0 (read) d63?d0 (write) figure 22.41 dram burst bus cycle (edo mode, rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 001, 2-cycle cas negate pulse width)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 984 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tr1 t ad row tc1 tc2 tc1 tc2 tr2 tpc c0 c1 c2 c3 ckio csn rd/ wr ras casn bs t ad t ad t ad t rdh t rds t rdh t rds t csd t rwd t rwd t csd t casd1 t rasd t wdd t rasd t casd1 t casd1 t casd1 t casd1 d3 d2 d1 d0 t bsd t bsd t bsd t bsd t dacd t dacd t dacd tc1 tc1 tc2 tce tc2 a25?a0 dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h d63?d0 (read) d63?d0 (write) figure 22.42 dram burst bus cycle: ras down mode state (edo mode, rcd[1:0] = 00, anw[2:0] = 000)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 985 of 1076 sep 24, 2013 tr1 tc1 tc2 tc1 tc2 tr2 c0 c1 c2 c3 ckio a25?a0 csn rd/ wr ras casn bs t ad t ad t ad t rdh t rds t rdh t rds t csd t rwd t rwd t rasd ras-down mode ended t csd t casd1 t wdd t casd1 t casd1 t casd1 t casd1 d3 d2 d1 d0 t bsd t bsd t bsd t bsd t dacd t dacd tc1 tce tc2 dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h d63?d0 (read) d63?d0 (write) figure 22.43 dram burst bus cycle: ras down mode continuation (edo mode, rcd[1:0] = 00, anw[2:0] = 000)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 986 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tr1 tr2 tc1 tc2 tc1 tc2 tc2 tc1 tc1 tc2 tpc ckio a25?a0 csn rd/ wr ras casn d63?d0 (read) d63?d0 (write) bs dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) t ad c0 row c1 c2 c3 t ad t ad t rwd t rwd t rdh t rds d0 t wdd d0 d1 d2 d3 t bsd t bsd t wdd d1 d2 t rdh t wdd t rds d3 t wdd t csd t csd t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t rasd t rasd t rasd t dacd t dacd t dacd figure 22.44 dram burst bus cycle (fast page mode, rcd[1:0] = 00, anw[2:0] = 000, tpc[2:0] = 001)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 987 of 1076 sep 24, 2013 tr1 tr2 trw tc1 tcw tc2 tcw tc1 tc2 tc1 tcw ckio csn rd/ wr ras casn bs t ad c0 row c1 c2 c3 t ad t ad t rwd t rwd t rdh t rds d0 t wdd d0 d1 d2 d3 t bsd t bsd t wdd d1 d2 t rdh t wdd t rds d3 t wdd t csd t csd t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t rasd t rasd t rasd t dacd t dacd t dacd tc1 tc2 tc2 tcw tpc a25?a0 d63?d0 (read) d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) figure 22.45 dram burst bus cycle (fast page mode, rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 001)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 988 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tr1 tr2 trw tc1 tcw tc2 tc1 tcnw tcw tc2 tcnw ckio csn rd/ wr ras casn bs t ad c0 row c1 c2 c3 t ad t ad t rwd t rwd t rdh t rds d0 t wdd d0 d1 d2 d3 t bsd t bsd t wdd d1 d2 t rdh t wdd t rds d3 t wdd t csd t csd t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t rasd t rasd t rasd t dacd t dacd t dacd tcw tc1 tcnw tc2 tc1 tpc tc2 tcnw tcw a25?a0 d63?d0 (read) d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) figure 22.46 dram burst bus cycle (fast page mode, rcd[1:0] = 01, anw[2:0] = 001, tpc[2:0] = 001, 2-cycle cas negate pulse width)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 989 of 1076 sep 24, 2013 tpc tr1 tr2 tc1 tc2 tc1 tc1 tc2 tc2 tc1 tc2 ckio a25?a0 csn rd/ wr ras casn d63?d0 (read) d63?d0 (write) bs dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) t ad c0 row c1 c2 c3 t ad t ad t ad t rwd t rwd t rwd t rdh t rds d0 t wdd d0 d1 d2 d3 t bsd t bsd t wdd d1 d2 t rdh t wdd t rds d3 t wdd t csd t csd t csd t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t dacd t dacd t dacd t rasd t rasd figure 22.47 dram burst bus cycle: ras down mode state (fast page mode, rcd[1:0] = 00, anw[2:0] = 000)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 990 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio csn rd/ wr ras casn bs t ad c0 c1 c2 c3 t ad t rwd t rwd t rwd t rdh t rds d0 t wdd d0 d1 d2 d3 t bsd t bsd t wdd d1 d2 t rdh t wdd t rds d3 t wdd t csd t csd t csd t rasd ras down mode ended t dacd t dacd t dacd t casd1 t casd1 t casd1 t casd1 t casd1 t dacd t dacd t dacd tnop tc1 tc2 tc1 tc1 tc2 tc2 tc1 tc2 a25?a0 d63?d0 (read) d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) figure 22.48 dram burst bus cycle: ras down mode continuation (fast page mode, rcd[1:0] = 00, anw[2:0] = 000)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 991 of 1076 sep 24, 2013 trr1 trr2 trr3 trr4 trr5 trc trc trc ckio a25?a0 csn rd/ wr ras casn d63?d0 (write) bs dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) t ad t wdd t dacd t dacd t csd t rwd t rasd t rasd t rasd t casd1 t casd1 t casd1 figure 22.49 dram bus cycle: dram cas- before-ras refresh (tras[2:0] = 000, trc[2:0] = 001)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 992 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 trr1 trr2 trr3 trr4 trr5 trr4w trc trc trc ckio csn rd/ wr ras casn bs t ad t wdd t dacd t dacd t csd t rwd t rasd t rasd t rasd t casd1 t casd1 t casd1 a25?a0 d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) figure 22.50 dram bus cycle: dram cas- before-ras refresh (tras[2:0] = 001, trc[2:0] = 001)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 993 of 1076 sep 24, 2013 trr1 trr2 trr3 trr4 trr5 trc trc trc ckio csn rd/ wr ras casn bs t ad t wdd t dacd t dacd t csd t rwd t rasd t rasd t rasd t casd1 t casd1 t casd1 a25?a0 d63?d0 (write) dackn (sa: io memory) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h dackn (sa: io memory) figure 22.51 dram bu s cycle: dram self-ref resh (trc[2:0] = 001)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 994 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tpcm1 tpcm2 tpcm0 tpcm1 tpcm2 tpcm1w tpcm1w tpcm2w ckio cexx reg ( we7 ) rd/ wr rd d15?d0 (read) d15?d0 (write) bs dackn (da) rdy we1 t ad t ad t wdd t bsd t bsd t bsd t bsd t wdd t wdd t rwd t csd t csd t rwd t rsd t rsd t rsd t wedf t wed1 t wedf t dacd t rdh t rds t rdyh t rdys t rdyh t rdys t dacd t ad t ad t wdd t wdd t wdd t rwd t csd t csd t rwd t rsd t rsd t rsd t wedf t wed1 t wedf t dacd ted teh t rdh t rds t dacd (1) (2) a25?a0 le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h note: * : SH7750s and SH7750r * figure 22.52 pcmcia memory bus cycle (1) ted[2:0] = 000, teh[2:0] = 000, no wait (2) ted[2:0] = 001, teh[2:0] = 001, one internal wait + one external wait
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 995 of 1076 sep 24, 2013 tpci1 tpci2 tpci0 tpci1 tpci2 tpci1w tpci1w tpci2w ckio cexx reg ( we7 ) rd/ wr iciord ( we2 ) bs dackn (da) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h rdy iois16 iciowr ( we3 ) t ad t ad t bsd t bsd t bsd t bsd t wdd t wdd t rwd t csd t csd t rwd t icrsd t icrsd t icwsdf t icwsdf t dacd t rdh t rds t rdyh t rdys t rdyh t rdys t io16h t io16s t io16h t io16s t dacd t ad t ad t wdd t wdd t wdd t rwd t csd t csd t rwd t icrsd t icrsd t icrsd t icwsdf t icwsdf t icwsdf t dacd t rdh t rds t dacd d15?d0 (read) d15?d0 (write) (1) (2) a25?a0 figure 22.53 pcmc ia i/o bus cycle (1) ted[2:0] = 000, teh[2:0] = 000, no wait (2) ted[2:0] = 001, teh[2:0] = 001, one internal wait + one external wait
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 996 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tpci0 tpci1 tpci2w tpci2 tpci1w tpci0 tpci1 tpci2w tpci2 tpci1w ckio a25?a1 a0 cexx reg ( we7 ) rd/ wr iciord ( we2 ) d15?d0 (read) d15?d0 (write) bs rdy iois16 le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h iciowr ( we3 ) t bsd t bsd t ad t ad t wdd t wdd t wdd t wdd t wdd t rwd t rwd t ad t csd t csd t csd t icrsd t icrsd t icrsd t icwsdf t icwsdf t icwsdf t icwsdf t icwsdf t rdh t rds t rdys t rdyh t io16s t io16h t rdys t rdyh figure 22.54 pcmc ia i/o bus cycle (ted[2:0] = 001, teh[2:0] = 001, one internal wait, bus sizing)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 997 of 1076 sep 24, 2013 tm1 tmd1w tmd1 tm0 tmd1w tmd1 tmd1w ckio csn rd/ wr wen d63?d0 bs dackn (da) rdy rd / frame t fmd t fmd t bsd t bsd t bsd t bsd t csd t csd t dacd t rdh t rds d0 t rdyh t rdys t dacd t rwd t rwd t wed1 t wed1 t fmd t fmd t csd t csd t rdh t rds t wdd ad0 t wdd t wdd a t wdd t rwd t rwd t wed1 t wed1 t dacd t dacd t rdyh t rdys t rdyh t rdys 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h (1) (2) figure 22.55 mpx basic bus cycle: read (1) 1st data (one internal wait) (2) 1st data (one internal wait + one external wait)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 998 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 tm1 tmd1w tmd1 ckio csn rd/ wr wen d63?d0 bs dackn (da) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h rdy rd / frame t fmd t fmd t bsd t bsd t csd t csd t dacd t rdyh t rdys t dacd t wed1 t wed1 tm1 tmd1 t fmd t fmd t bsd t bsd t csd t csd t dacd d0 d0 t rdyh t rdys t dacd t rwd t rwd t rwd t rwd t wed1 t wed1 a t rdyh t rdys t rdyh t rdys t wdd t wdd t wdd a t wdd t wdd t wdd tm1 tmd1w tmd1w tmd1 t fmd t fmd t bsd t bsd t csd t csd t dacd t dacd t wed1 t wed1 d0 t rwd t rwd a t wdd t wdd t wdd 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address (1) (2) (3) figure 22.56 mpx basic bus cycle: write (1) 1st data (no wait) (2) 1st data (one internal wait) (3) 1st data (one internal wait + one external wait)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 999 of 1076 sep 24, 2013 ckio csn rd/ wr wen d63?d0 bs dackn (da) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h rdy rd / frame tm1 tmd1w tmd1 tmd2 tmd3 tmd4 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t dacd t dacd t wed1 t wed1 d3 t rwd t rwd a t wdd d2 d1 d0 t wdd t rdh t rds tm1 tmd1w tmd1 tmd2w tmd2 tmd3 tmd4w tmd4 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t rdyh t rdys t dacd t dacd t wed1 t wed1 d3 t rwd t rwd a t wdd d2 d1 d0 t wdd t rdh t rds 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address (1) (2) figure 22.57 mpx bus cycle: burst read (1) 1st data (one internal wait), 2nd to 8th data (one internal wait) (2) 1st data (one internal wait), 2nd to 4th data (one internal wait + one external wait)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1000 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio csn rd/ wr wen d63?d0 bs dackn (da) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h rdy rd / frame tm1 tmd1 tmd2 tmd3 tmd4 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t dacd t dacd t wed1 t wed1 d3 t rwd t rwd a t wdd d2 d1 d0 d3 d2 d1 d0 t wdd tm1 tmd1w tmd1 tmd2w tmd2 tmd3 tmd4w tmd4 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t rdyh t rdys t dacd t dacd t wed1 t wed1 t rwd t rwd a t wdd t wdd 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address 1st data bus cycle information d63?d61: access size 000: byte 001: word (2 bytes) 010: lon g (4 bytes) 011: quad (8 bytes) 1xx: burst (32 bytes) d25?d0: address (1) (2) figure 22.58 mpx bu s cycle: burst write (1) no internal wait (2) 1st data (one internal wait), 2nd to 4th data (no internal wait + external wait control)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 1001 of 1076 sep 24, 2013 t1 tw t2 ckio csn rd/ wr rd (1) wen d63?d0 (read) bs dackn (da) rdy a25?a0 t dacd t dacd t csd t csd t dacd t rdyh t rdys t dacd t dacd t rwd t rwd t1 t2 t dacd t dacd t csd t csd t dacd t dacd t wed1 t dacd t rwd t rwd t rdyh t rdys t rdyh t rdys t ad t ad t ad t ad t1 tw twe t2 t dacd t dacd t rsd t rsd t rsd t rsd t rsd t rsd t rsd t rsd t wed1 t wed1 t wedf t wed1 t wedf t wed1 t wedf t wed1 t csd t csd t dacd t bsd t bsd t bsd t bsd t bsd t bsd t dacd t dacd t rwd t rwd t rsd t ad t ad t rdh t rds t rdh t rds t rdh t rds dackn (sa: io memory) (2) (3) le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.59 memory byte control sram bus cycles (1) basic read cycle (no wait) (2) basic read cycle (one internal wait) (3) basic read cycle (one internal wait + one external wait)
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1002 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio csn rd/ wr rd wen d63?d0 (read) bs dackn (da) rdy a25?a0 ts1 t1 t2 th1 t rsd t rsd t wed1 t wedf t wed1 t csd t csd t dacd t bsd t bsd t dacd t rwd t rwd t rsd t ad t ad t rdh t rds dackn (sa: io memory) t dacd t dacd le g end: io: dack device sa: sin g le address dma transfer da: dual address dma transfer dack set to active-hi g h figure 22.60 memory byte control sram bu s cycle: basic read cycle (no wait, address setup/hold time insertion, ans[0] = 1, anh[1:0] =0 1)
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 1003 of 1076 sep 24, 2013 22.3.4 peripheral module signal timing table 22.37 peripheral module signal timing (1) hd6417750 rbp240 (v) hd6417750 rbg240 (v) hd6417750 rba240hv hd6417750 rbp200 (v) hd6417750r bg200 (v) hd6417750 rba240hv * 3 hd6417750 f240 (v) hd6417750 rf200 (v) * 2 * 2 * 2 * 2 module item symbol min max min max min max min max unit figure tmu, rtc timer clock pulse width (high) t tclkwh 4 ? 4 ? 4 ? 4 ? pcyc * 1 22.61 timer clock pulse width (low) t tclkwl 4 ? 4 ? 4 ? 4 ? pcyc * 1 22.61 timer clock rise time t tclkr ? 0.8 ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.61 timer clock fall time t tclkf ? 0.8 ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.61 oscillation settling time t rosc ? 3 ? 3 ? 3 ? 3 s 22.62 sci input clock cycle (asyn- chronous) t scyc 4 ? 4 ? 4 ? 4 ? pcyc * 1 22.63 input clock cycle (syn- chronous) t scyc 6 ? 6 ? 6 ? 6 ? pcyc * 1 22.63 input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t scyc 22.63 input clock rise time t sckr ? 0.8 ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.63 input clock fall time t sckf ? 0.8 ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.63 transfer data delay time t txd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns 22.64 receive data setup time (synchronous) t rxs 16 ? 16 ? 16 ? 16 ? ns 22.64 receive data hold time (synchronous) t rxh 16 ? 16 ? 16 ? 16 ? ns 22.64 i/o ports output data delay time t portd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns 22.65 input data setup time t ports 2 ? 2.5 ? 3.5 ? 3.5 ? ns 22.65 input data hold time t porth 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 22.65
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1004 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 hd6417750 rbp240 (v) hd6417750 rbg240 (v) hd6417750 rba240hv hd6417750 rbp200 (v) hd6417750r bg200 (v) hd6417750 rba240hv * 3 hd6417750 f240 (v) hd6417750 rf200 (v) * 2 * 2 * 2 * 2 module item symbol min max min max min max min max unit figure dmac dreqn setup time t drqs 2 ? 2.5 ? 3.5 ? 3.5 ? ns 22.66 dreqn hold time t drqh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 22.66 drakn delay time t drakd 1.5 5.3 1.5 6 1.5 6 1.5 6 ns 22.66 5 ? 5 ? 5 ? 5 ? t cyc 22.71 normal or sleep mode nmi pulse width (high) t nmih 30 ? 30 ? 30 ? 30 ? ns 22.71 standby mode 5 ? 5 ? 5 ? 5 ? t cyc 22.71 normal or sleep mode intc nmi pulse width (low) t nmil 30 ? 30 ? 30 ? 30 ? ns 22.71 standby mode h-udi input clock cycle t tckcyc 50 ? 50 ? 50 ? 50 ? ns 22.67 input clock pulse width (high) t tckh 15 ? 15 ? 15 ? 15 ? ns 22.67 input clock pulse width (low) t tckl 15 ? 15 ? 15 ? 15 ? ns 22.67 input clock rise time t tckr ? 10 ? 10 ? 10 ? 10 ns 22.67 input clock fall time t tckf ? 10 ? 10 ? 10 ? 10 ns 22.67 asebrk setup time t asebrks 10 ? 10 ? 10 ? 10 ? t cyc 22.68 asebrk hold time t asebrkh 10 ? 10 ? 10 ? 10 ? t cyc 22.68 tdi/tms setup time t tdis 15 ? 15 ? 15 ? 15 ? ns 22.69 tdi/tms hold time t tdih 15 ? 15 ? 15 ? 15 ? ns 22.69 tdo delay time t tdo 0 10 0 10 0 10 0 10 ns 22.69 ase-pinbrk pulse width t pinbrk 2 ? 2 ? 2 ? 2 ? pcyc * 1 22.70 notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf * 4 , pll2 on
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 1005 of 1076 sep 24, 2013 3. this is the case when the device in use is an hd6417750rba240hv running at 200 mhz. 4. t a = ?40 to 85c for the hd6417750rba240hv. table 22.38 peripheral module signal timing (2) hd6417750s vf133 (v) hd6417750s vbt133 (v) hd6417750 sf167 (v) hd6417750 sf200 (v) hd6417750 sbp200 (v) hd6417750 sba200v * 2 * 3 * 4 module item symbol min max min max min max unit figure tmu, rtc timer clock pulse width (high) t tclkwh 4 ? 4 ? 4 ? pcyc * 1 22.61 timer clock pulse width (low) t tclkwl 4 ? 4 ? 4 ? pcyc * 1 22.61 timer clock rise time t tclkr ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.61 timer clock fall time t tclkf ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.61 oscillation settling time t rosc ? 3 ? 3 ? 3 s 22.62 sci input clock cycle (asyn- chronous) t scyc 4 ? 4 ? 4 ? pcyc * 1 22.63 input clock cycle (syn- chronous) t scyc 6 ? 6 ? 6 ? pcyc * 1 22.63 input clock pulse width t sckw 0.4 0.6 0.4 0. 6 0.4 0.6 t scyc 22.63 input clock rise time t sckr ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.63 input clock fall time t sckf ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.63 transfer data delay time t txd 1.5 10 1.5 8 1.5 6 ns 22.64 receive data setup time (synchronous) t rxs 16 ? 16 ? 16 ? ns 22.64 receive data hold time (synchronous) t rxh 16 ? 16 ? 16 ? ns 22.64
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1006 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 hd6417750s vf133 (v) hd6417750s vbt133 (v) hd6417750 sf167 (v) hd6417750 sf200 (v) hd6417750 sbp200 (v) hd6417750 sba200v * 2 * 3 * 4 module item symbol min max min max min max unit figure i/o ports output data delay time t portd 1.5 10 1.5 8 1.5 6 ns 22.65 input data setup time t ports 3.5 ? 3.5 ? 3 ? ns 22.65 input data hold time t porth 1.5 ? 1.5 ? 1.5 ? ns 22.65 dmac dreqn setup time t drqs 3.5 ? 3.5 ? 3 ? ns 22.66 dreqn hold time t drqh 1.5 ? 1.5 ? 1.5 ? ns 22.66 drakn delay time t drakd 1.5 10 1.5 8 1.5 6 ns 22.66 notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 3. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 4. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 1007 of 1076 sep 24, 2013 table 22.39 peripheral module signal timing (3) hd6417750s vf133 (v) hd6417750s vbt133 (v) hd6417750 sf167 (v) hd6417750 sf200 (v) hd6417750 sbp200 (v) hd6417750 sba200v * 2 * 3 * 4 module item symbol min max min max min max unit figure 5 ? 5 ? 5 ? t cyc 22.71 normal or sleep mode nmi pulse width (high) t nmih 30 ? 30 ? 30 ? ns 22.71 standby mode 5 ? 5 ? 5 ? t cyc 22.71 normal or sleep mode intc nmi pulse width (low) t nmil 30 ? 30 ? 30 ? ns 22.71 standby mode h-udi input clock cycle t tckcyc 50 ? 50 ? 50 ? ns 22.67 input clock pulse width (high) t tckh 15 ? 15 ? 15 ? ns 22.67 input clock pulse width (low) t tckl 15 ? 15 ? 15 ? ns 22.67 input clock rise time t tckr ? 10 ? 10 ? 10 ns 22.67 input clock fall time t tckf ? 10 ? 10 ? 10 ns 22.67 asebrk setup time t asebrks 10 ? 10 ? 10 ? t cyc 22.68 asebrk hold time t asebrkh 10 ? 10 ? 10 ? t cyc 22.68 tdi/tms setup time t tdis 15 ? 15 ? 15 ? ns 22.69 tdi/tms hold time t tdih 15 ? 15 ? 15 ? ns 22.69 tdo delay time t tdo 0 10 0 10 0 10 ns 22.69 ase-pinbrk pulse width t pinbrk 2 ? 2 ? 2 ? pcyc * 1 22.70 notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 3. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 4. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1008 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.40 peripheral module signal timing (4) hd6417750 vf128 (v) hd6417750 f167 (v) hd6417750 bp200m (v) * 2 * 3 * 4 module item symbol min max min max min max unit figure tmu, rtc timer clock pulse width (high) t tclkwh 4 ? 4 ? 4 ? pcyc * 1 22.61 timer clock pulse width (low) t tclkwl 4 ? 4 ? 4 ? pcyc * 1 22.61 timer clock rise time t tclkr ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.61 timer clock fall time t tclkf ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.61 oscillation settling time t rosc ? 3 ? 3 ? 3 s 22.62 sci input clock cycle (asyn- chronous) t scyc 4 ? 4 ? 4 ? pcyc * 1 22.63 input clock cycle (syn- chronous) t scyc 6 ? 6 ? 6 ? pcyc * 1 22.63 input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc 22.63 input clock rise time t sckr ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.63 input clock fall time t sckf ? 0.8 ? 0.8 ? 0.8 pcyc * 1 22.63 transfer data delay time t txd 1.3 10 1.3 8 1.2 6 ns 22.64 receive data setup time (synchronous) t rxs 16 ? 16 ? 16 ? ns 22.64 receive data hold time (synchronous) t rxh 16 ? 16 ? 16 ? ns 22.64 i/o ports output data delay time t portd 0.5 10 0.5 8 0.5 6 ns 22.65 input data setup time t ports 3.5 ? 3.5 ? 3 ? ns 22.65 input data hold time t porth 1.5 ? 1.5 ? 1.5 ? ns 22.65
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 1009 of 1076 sep 24, 2013 hd6417750 vf128 (v) hd6417750 f167 (v) hd6417750 bp200m (v) * 2 * 3 * 4 module item symbol min max min max min max unit figure dmac dreqn setup time t drqs 3.5 ? 3.5 ? 3 ? ns 22.66 dreqn hold time t drqh 1.5 ? 1.5 ? 1.5 ? ns 22.66 drakn delay time t drakd 1.0 10 1.0 8 1.0 6 ns 22.66 notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 3. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 4. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1010 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 table 22.41 peripheral module signal timing (5) hd6417750 vf128 (v) hd6417750 f167 (v) hd6417750 bp200m (v) * 2 * 3 * 4 module item symbol min max min max min max unit figure 5 ? 5 ? 5 ? t cyc 22.71 normal or sleep mode nmi pulse width (high) t nmih 30 ? 30 ? 30 ? ns 22.71 standby mode 5 ? 5 ? 5 ? t cyc 22.71 normal or sleep mode intc nmi pulse width (low) t nmil 30 ? 30 ? 30 ? ns 22.71 standby mode h-udi input clock cycle t tckcyc 50 ? 50 ? 50 ? ns 22.67 input clock pulse width (high) t tckh 15 ? 15 ? 15 ? ns 22.67 input clock pulse width (low) t tckl 15 ? 15 ? 15 ? ns 22.67 input clock rise time t tckr ? 10 ? 10 ? 10 ns 22.67 input clock fall time t tckf ? 10 ? 10 ? 10 ns 22.67 asebrk setup time t asebrks 10 ? 10 ? 10 ? t cyc 22.68 asebrk hold time t asebrkh 10 ? 10 ? 10 ? t cyc 22.68 tdi/tms setup time t tdis 15 ? 15 ? 15 ? ns 22.69 tdi/tms hold time t tdih 15 ? 15 ? 15 ? ns 22.69 tdo delay time t tdo 0 10 0 10 0 10 ns 22.69 ase-pinbrk pulse width t pinbrk 2 ? 2 ? 2 ? pcyc * 1 22.70 notes: 1. pcyc: p clock cycles 2. v ddq = 3.0 to 3.6 v, v dd = 1.5 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 3. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on 4. v ddq = 3.0 to 3.6 v, v dd = 1.8 v, t a = ?20 to +75c, c l = 30 pf, pll2 on
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 1011 of 1076 sep 24, 2013 tclk t tclkf t tclkwh t tclkwl t tclkr figure 22.61 tclk input timing rtc internal clock t rosc stable oscillation v dd-rtc v dd-rtc min figure 22.62 rtc oscillatio n settling time at power-on sck, sck2 t sckf t scyc t sckw t sckr figure 22.63 sck input clock timing
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1012 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 t txd sck txd rxd t txd t rxs t rxh t scyc figure 22.64 sci i/o synchronous mode clock timing t portd t portd ckio ports 19?0 (read) ports 19?0 (write) t ports t porth figure 22.65 i/o port input/output timing t drakd t drqh t drqh t drqs t drqs ckio dreqn drakn figure 22.66 (a) dreq /drak timing
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 1013 of 1076 sep 24, 2013 t dbqh t dbqs ckio d63 to d0 (read) dbreq bavl tr t bavd t bavd t trh (2) t trs t dtrh t dtrs (1) (1): [2ckio cycle ? t dtrs ] (= 18 ns: 100 mhz) (2): dtr = 1ckio cycle (= 10 ns: 100 mhz) (t dtrs + t dtrh ) < dtr < 10 ns figure 22.66 (b) dbreq / tr input timing and bavl output timing t tckcyc t tckh t tckl t tckr t tckf 1/2v ddq v ih v ih v il v il v ih 1/2v ddq note: when clock is input from tck pin figure 22.67 tck input timing
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1014 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 asebrk / brkack reset sck2/ mreset t asebrkh t asebrks t asebrks t asebrkh (low) (hi g h) figure 22.68 reset hold timing tdi tms tck tdo t tckcyc t tdo t tdih t tdis figure 22.69 h-udi data transfer timing asebrk t pinbrk figure 22.70 pin break timing t nmih t nmil nmi figure 22.71 nmi input timing
SH7750, SH7750s, SH7750r group section 22 electrical characteristics r01uh0456ej0702 rev. 7.02 page 1015 of 1076 sep 24, 2013 22.3.5 ac characteristic test conditions the ac characteristic test conditions are as follows: ? input/output signal reference level: 1.5 v (v ddq = 3.3 0.3 v) ? input pulse level: v ssq to 3.0 v (v ssq to v ddq for reset , trst , nmi, and asebrk /brkack) ? input rise/fall time: 1 ns the output load circuit is shown in figure 22.72. i ol i oh c l v ref lsi output pin dut output notes: c l is the total value, includin g the capacitance of the test ji g , etc. the capacitance of each pin is set to 30 pf. i ol and i oh values are as shown in table 22.16, permissible output currents. figure 22.72 output load circuit
section 22 electrical characte ristics SH7750, SH7750s, SH7750r group page 1016 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 22.3.6 delay time variation du e to load capacitance a graph (reference data) of the variation in dela y time when a load capacitance greater than that stipulated (30 pf) is connected to this lsi' pins is shown below. the graph shown in figure 22.73 should be taken into consideration if the stipulated capacitance is exceeded when connecting an external device. the graph will not be linear if the connected load capacitance exceeds the range shown in figure 22.73. +4.0 ns +3.0 ns +2.0 ns +1.0 ns +0.0 ns +0 pf +25 pf +50 pf load capacitance delay time figure 22.73 load capacitance vs. delay time
SH7750, SH7750s, SH7750r group appendix a address list r01uh0456ej0702 rev. 7.02 page 1017 of 1076 sep 24, 2013 appendix a address list table a.1 address list module register p4 address area 7 address * 1 size power-on reset manual reset sleep standby synchro- nization clock ccn pteh h'ff00 0000 h'1f00 0000 32 undefined undefined held held ick ccn ptel h'ff00 0004 h'1f00 0004 32 undefined undefined held held ick ccn ttb h'ff00 0008 h'1f00 0008 32 undefined undefined held held ick ccn tea h'ff00 000c h'1f00 000c 32 undefined held held held ick ccn mmucr h'ff00 0010 h'1f00 0010 32 h'0000 0000 h'0000 0000 held held ick ccn basra h'ff00 0014 h'1f00 0014 8 undefined held held held ick ccn basrb h'ff00 0018 h'1f00 0018 8 undefined held held held ick ccn ccr h'ff00 001c h'1f00 001c 32 h'0000 0000 h'0000 0000 held held ick ccn tra h'ff00 0020 h'1f00 0020 32 undefined undefined held held ick ccn expevt h'ff00 0024 h'1f00 0024 32 h'0000 0000 h'0000 0020 held held ick ccn intevt h'ff00 0028 h'1f00 0028 32 undefined undefined held held ick ccn ptea h'ff00 0034 h'1f00 0034 32 undefined undefined held held ick ccn qacr0 h'ff00 0038 h'1f00 0038 32 undefined undefined held held ick ccn qacr1 h'ff00 003c h'1f00 003c 32 undefined undefined held held ick ubc bara h'ff20 0000 h'1f20 0000 32 undefined held held held ick ubc bamra h'ff20 0004 h'1f20 0004 8 undefined held held held ick ubc bbra h'ff20 0008 h'1f20 0008 16 h'0000 held held held ick ubc barb h'ff20 000c h'1f20 000c 32 undefined held held held ick ubc bamrb h'ff20 0010 h'1f20 0010 8 undefined held held held ick ubc bbrb h'ff20 0014 h'1f20 0014 16 h'0000 held held held ick ubc bdrb h'ff20 0018 h'1f20 0018 32 undefined held held held ick ubc bdmrb h'ff20 001c h'1f20 001c 32 undefined held held held ick ubc brcr h'ff20 0020 h'1f20 0020 16 h'0000 * 2 held held held ick bsc bcr1 h'ff80 0000 h'1f80 0000 32 h'0000 0000 * 2 held held held bck bsc bcr2 h'ff80 0004 h'1f80 0004 16 h'3ffc * 2 held held held bck bsc bcr3 * 5 h'ff80 0050 h'1f80 0050 16 h'0000 held held held bck bsc bcr4 * 5 h'fe0a00f0 h'1e0a00f0 32 h'0000 0000 held held held bck
appendix a address list SH7750, SH7750s, SH7750r group page 1018 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 module register p4 address area 7 address * 1 size power-on reset manual reset sleep standby synchro- nization clock bsc wcr1 h'ff80 0008 h'1f80 0008 32 h'7777 7777 held held held bck bsc wcr2 h'ff80 000c h'1f80 000c 32 h'fffe efff held held held bck bsc wcr3 h'ff80 0010 h'1f80 0010 32 h'0777 7777 held held held bck bsc mcr h'ff80 0014 h'1f80 0014 32 h'0000 0000 held held held bck bsc pcr h'ff80 0018 h'1f80 0018 16 h'0000 held held held bck bsc rtcsr h'ff80 001c h'1f80 001c 16 h'0000 held held held bck bsc rtcnt h'ff80 0020 h'1f80 0020 16 h'0000 held held held bck bsc rtcor h'ff80 0024 h'1f80 0024 16 h'0000 held held held bck bsc rfcr h'ff80 0028 h'1f80 0028 16 h'0000 held held held bck bsc pctra h'ff80 002c h'1f80 002c 32 h'0000 0000 held held held bck bsc pdtra h'ff80 0030 h'1f80 0030 16 undefined held held held bck bsc pctrb h'ff80 0040 h'1f80 0040 32 h'0000 0000 held held held bck bsc pdtrb h'ff80 0044 h'1f80 0044 16 undefined held held held bck bsc gpioic h'ff80 0048 h'1f80 0048 16 h'0000 0000 held held held bck bsc sdmr2 h'ff90 xxxx h'1f90 xxxx 8 write-only bck bsc sdmr3 h'ff94 xxxx h'1f94 xxxx 8 bck dmac sar0 h'ffa0 0000 h'1fa0 0000 32 undefined undefined held held bck dmac dar0 h'ffa0 0004 h'1fa0 0004 32 undefined undefined held held bck dmac dmatcr0 h'ffa0 0008 h'1fa0 0008 32 undefined undefined held held bck dmac chcr0 h'ffa0 000c h'1fa0 000c 32 h'0000 0000 h'0000 00 00 held held bck dmac sar1 h'ffa0 0010 h'1fa0 0010 32 undefined undefined held held bck dmac dar1 h'ffa0 0014 h'1fa0 0014 32 undefined undefined held held bck dmac dmatcr1 h'ffa0 0018 h'1fa0 0018 32 undefined undefined held held bck dmac chcr1 h'ffa0 001c h'1fa0 001c 32 h'0000 0000 h'0000 00 00 held held bck dmac sar2 h'ffa0 0020 h'1fa0 0020 32 undefined undefined held held bck dmac dar2 h'ffa0 0024 h'1fa0 0024 32 undefined undefined held held bck dmac dmatcr2 h'ffa0 0028 h'1fa0 0028 32 undefined undefined held held bck dmac chcr2 h'ffa0 002c h'1fa0 002c 32 h'0000 0000 h'0000 00 00 held held bck dmac sar3 h'ffa0 0030 h'1fa0 0030 32 undefined undefined held held bck dmac dar3 h'ffa0 0034 h'1fa0 0034 32 undefined undefined held held bck dmac dmatcr3 h'ffa0 0038 h'1fa0 0038 32 undefined undefined held held bck dmac chcr3 h'ffa0 003c h'1fa0 003c 32 h'0000 0000 h'0000 00 00 held held bck
SH7750, SH7750s, SH7750r group appendix a address list r01uh0456ej0702 rev. 7.02 page 1019 of 1076 sep 24, 2013 module register p4 address area 7 address * 1 size power-on reset manual reset sleep standby synchro- nization clock dmac dmaor h'ffa0 0040 h'1fa0 0040 32 h'0000 0000 h'0000 0000 held held bck dmac sar4 * 5 h'ffa0 0050 h'1fa0 0050 32 undefined undefined held held bck dmac dar4 * 5 h'ffa0 0054 h'1fa0 0054 32 undefined undefined held held bck dmac dmatcr4 * 5 h'ffa0 0058 h'1fa0 0058 32 undefined undefined held held bck dmac chcr4 * 5 h'ffa0 005c h'1fa0 005c 32 h'000 0 0000 h'0000 0000 held held bck dmac sar5 * 5 h'ffa0 0060 h'1fa0 0060 32 undefined undefined held held bck dmac dar5 * 5 h'ffa0 0064 h'1fa0 0064 32 undefined undefined held held bck dmac dmatcr5 * 5 h'ffa0 0068 h'1fa0 0068 32 undefined undefined held held bck dmac chcr5 * 5 h'ffa0 006c h'1fa0 006c 32 h'000 0 0000 h'0000 0000 held held bck dmac sar6 * 5 h'ffa0 0070 h'1fa0 0070 32 undefined undefined held held bck dmac dar6 * 5 h'ffa0 0074 h'1fa0 0074 32 undefined undefined held held bck dmac dmatcr6 * 5 h'ffa0 0078 h'1fa0 0078 32 undefined undefined held held bck dmac chcr6 * 5 h'ffa0 007c h'1fa0 007c 32 h'000 0 0000 h'0000 0000 held held bck dmac sar7 * 5 h'ffa0 0080 h'1fa0 0080 32 undefined undefined held held bck dmac dar7 * 5 h'ffa0 0084 h'1fa0 0084 32 undefined undefined held held bck dmac dmatcr7 * 5 h'ffa0 0088 h'1fa0 0088 32 undefined undefined held held bck dmac chcr7 * 5 h'ffa0 008c h'1fa0 008c 32 h'000 0 0000 h'0000 0000 held held bck cpg frqcr h'ffc0 0000 h'1fc0 0000 16 * 2 held held held pck cpg * 6 stbcr h'ffc0 0004 h'1fc0 0004 8 h'00 held held held pck cpg * 6 wtcnt h'ffc0 0008 h'1fc0 0008 8/16 * 3 h'00 held held held pck cpg * 6 wtcsr h'ffc0 000c h'1fc0 000c 8/16 * 3 h'00 held held held pck cpg * 6 stbcr2 h'ffc0 0010 h'1fc0 0010 8 h'00 held held held pck rtc r64cnt h'ffc8 0000 h'1fc8 0000 8 held held held held pck rtc rseccnt h'ffc8 0004 h'1fc8 0004 8 held held held held pck rtc rmincnt h'ffc8 0008 h'1fc8 0008 8 held held held held pck rtc rhrcnt h'ffc8 000c h'1fc8 000c 8 held held held held pck rtc rwkcnt h'ffc8 0010 h'1fc8 0010 8 held held held held pck rtc rdaycnt h'ffc8 0014 h'1fc8 0014 8 held held held held pck rtc rmoncnt h'ffc8 0018 h'1fc8 0018 8 held held held held pck rtc ryrcnt h'ffc8 001c h'1fc8 001c 16 held held held held pck rtc rsecar h'ffc8 0020 h'1fc8 0020 8 held * 2 held held held pck
appendix a address list SH7750, SH7750s, SH7750r group page 1020 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 module register p4 address area 7 address * 1 size power-on reset manual reset sleep standby synchro- nization clock rtc rminar h'ffc8 0024 h'1fc8 0024 8 held * 2 held held held pck rtc rhrar h'ffc8 0028 h'1fc8 0028 8 held * 2 held held held pck rtc rwkar h'ffc8 002c h'1fc8 002c 8 held * 2 held held held pck rtc rdayar h'ffc8 0030 h'1fc8 0030 8 held * 2 held held held pck rtc rmonar h'ffc8 0034 h'1fc8 0034 8 held * 2 held held held pck rtc rcr1 h'ffc8 0038 h'1fc8 0038 8 h'00 * 2 h'00 * 2 held held pck rtc rcr2 h'ffc8 003c h'1fc8 003c 8 h'09 * 2 h'00 * 2 held held pck rtc rcr3 * 5 h'ffc8 0050 h'1fc8 0050 8 h'00 held held held pck rtc ryrar * 5 h'ffc8 0054 h'1fc8 0054 16 undefined held held held pck intc icr h'ffd0 0000 h'1fd0 0000 16 h'0000 * 2 h'0000 * 2 held held pck intc ipra h'ffd0 0004 h'1fd0 0004 16 h'0000 h'0000 held held pck intc iprb h'ffd0 0008 h'1fd0 0008 16 h'0000 h'0000 held held pck intc iprc h'ffd0 000c h'1fd0 000c 16 h'0000 h'0000 held held pck intc iprd * 4 h'ffd00010 h'1f000010 16 h'da74 h'da74 held held pck intc intpri00 * 5 h'fe08 0000 h'1e08 0000 32 h'0000 0000 held held held pck intc intreq00 * 5 h'fe08 0020 h'1e08 0020 32 h'0000 0000 held held held pck intc intmsk00 * 5 h'fe08 0040 h'1e08 0040 32 h'0000 0300 held held held pck intc intmskc lr00 * 5 h'fe08 0060 h'1e08 0060 32 write-only pck cpg * 6 clkstp 00 * 5 h'fe0a 0000 h'1e0a 0000 32 h'0000 0000 held held held pck cpg * 6 clkstpc lr00 * 5 h'fe0a 0008 h'1e0a 0008 32 write-only pck tmu tstr2 * 5 h'fe10 0004 h'1e10 0004 8 h'00 held held held pck tmu tcor3 * 5 h'fe10 0008 h'1e10 0008 32 h'ffff ffff held held held pck tmu tcnt3 * 5 h'fe10 000c h'1e10 000c 32 h'ffff ffff held held held pck tmu tcr3 * 5 h'fe10 0010 h'1e10 0010 16 h'0000 held held held pck tmu tcor4 * 5 h'fe10 0014 h'1e10 0014 32 h'ffff ffff held held held pck tmu tcnt4 * 5 h'fe10 0018 h'1e10 0018 32 h'ffff ffff held held held pck
SH7750, SH7750s, SH7750r group appendix a address list r01uh0456ej0702 rev. 7.02 page 1021 of 1076 sep 24, 2013 module register p4 address area 7 address * 1 size power-on reset manual reset sleep standby synchro- nization clock tmu tcr4 * 5 h'fe10 001c h'1e10 001c 16 h'0000 held held held pck tmu tocr h'ffd8 0000 h'1fd8 0000 8 h'00 h'00 held held pck tmu tstr h'ffd8 0004 h'1fd8 0004 8 h'00 h'00 held h'00 * 2 pck tmu tcor0 h'ffd8 0008 h'1fd8 0008 32 h'ffff ffff h'ffff ffff held held pck tmu tcnt0 h'ffd8 000c h'1fd8 000c 32 h'ffff ffff h'ffff ffff held held pck tmu tcr0 h'ffd8 0010 h'1fd8 0010 16 h'0000 h'0000 held held pck tmu tcor1 h'ffd8 0014 h'1fd8 0014 32 h'ffff ffff h'ffff ffff held held pck tmu tcnt1 h'ffd8 0018 h'1fd8 0018 32 h'ffff ffff h'ffff ffff held held pck tmu tcr1 h'ffd8 001c h'1fd8 001c 16 h'0000 h'0000 held held pck tmu tcor2 h'ffd8 0020 h'1fd8 0020 32 h'ffff ffff h'ffff ffff held held pck tmu tcnt2 h'ffd8 0024 h'1fd8 0024 32 h'ffff ffff h'ffff ffff held held pck tmu tcr2 h'ffd8 0028 h'1fd8 0028 16 h'0000 h'0000 held held pck tmu tcpr2 h'ffd8 002c h'1fd8 002c 32 held held held held pck sci scsmr1 h'ffe0 0000 h'1fe0 0000 8 h'00 h'00 held h'00 pck sci scbrr1 h'ffe0 0004 h'1fe0 0004 8 h'ff h'ff held h'ff pck sci scscr1 h'ffe0 0008 h'1fe0 0008 8 h'00 h'00 held h'00 pck sci sctdr1 h'ffe0 000c h'1fe0 000c 8 h'ff h'ff held h'ff pck sci scssr1 h'ffe0 0010 h'1fe0 0010 8 h'84 h'84 held h'84 pck sci scrdr1 h'ffe0 0014 h'1fe0 0014 8 h'00 h'00 held h'00 pck sci scscmr1 h'ffe0 0018 h'1fe0 0018 8 h'00 h'00 held h'00 pck sci scsptr1 h'ffe0 001c h'1fe0 001c 8 h'00 * 2 h'00 * 2 held h'00 * 2 pck scif scsmr2 h'ffe8 0000 h'1fe8 0000 16 h'0000 h'0000 held held pck scif scbrr2 h'ffe8 0004 h'1fe8 0004 8 h'ff h'ff held held pck scif scscr2 h'ffe8 0008 h'1fe8 0008 16 h'0000 h'0000 held held pck scif scftdr2 h'ffe8 000c h'1fe8 000c 8 undefined unde fined held held pck scif scfsr2 h'ffe8 0010 h'1fe8 0010 16 h'0060 h'0060 held held pck scif scfrdr2 h'ffe8 0014 h'1fe8 0014 8 undefined undefined held held pck scif scfcr2 h'ffe8 0018 h'1fe8 0018 16 h'0000 h'0000 held held pck scif scfdr2 h'ffe8 001c h'1fe8 00 1c 16 h'0000 h'0000 held held pck scif scsptr2 h'ffe8 0020 h'1fe8 0020 16 h'0000 * 2 h'0000 * 2 held held pck scif sclsr2 h'ffe8 0024 h'1fe8 0024 16 h'0000 h'0000 held held pck
appendix a address list SH7750, SH7750s, SH7750r group page 1022 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 module register p4 address area 7 address * 1 size power-on reset manual reset sleep standby synchro- nization clock h-udi sdir h'fff0 0000 h'1ff0 0000 16 h'ffff * 2 held held held pck h-udi sddr h'fff0 0008 h'1ff0 0008 32 undefined held held held pck h-udi sdint * 5 h'fff0 0014 h'1ff0 0014 16 h'0000 held held held pck notes: 1. with control registers, the above addresses in the physical page number field can be accessed by means of a tlb setting. when t hese addresses are referenced directly without using the tlb, operations are limited. 2. includes undefined bits. see the de scriptions of the individual modules. 3. use word-size access when writing. perform the write with the upper byte set to h'5a or h'a5, respectively. byte- and longword-size writes cannot be used. use byte-size access when reading. 4. SH7750s, SH7750r only 5. SH7750r only 6. includes power-down states
SH7750, SH7750s, SH7750r group appendix b package dimensions r01uh0456ej0702 rev. 7.02 page 1023 of 1076 sep 24, 2013 appendix b package dimensions y w v u t r p n m l k j h g f e d c b 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 a a b s s y v s y 1 sab s a a prbg0256de-b p-bga256-27x27-1.27 d e s d s e z d z e mass[typ.] 3.0g bp-256a/bp-256av renesas code jeita package code previous code 0.20 0.35 y 1 0.635 0.635 w v 0.30 27.0 2.5 0.7 0.6 0.5 0.90 0.75 0.60 1.27 0.20 27.0 y x b a reference symbol dimension in millimeters min nom max a 1 e e e b m m 0.10 4 e d s s d e figure b.1 package dimensions (256-pin bga: devices other than hd6417750rba240hv and hd6417750sba200v)
appendix b package dimensions SH7750, SH7750s, SH7750r group page 1024 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. index mark * 1 * 2 * 3 p e d e d xm y 105 156 53 104 157 52 208 1 f z z e b h d h 2 1 1 detail f c a a l a l terminal cross section p 1 1 b c c b 1.25 1.25 0.10 0.10 0.5 8 0 30.8 30.4 30.6 0.15 0.20 3.56 0.25 0.15 0.00 0.27 0.22 0.17 0.22 0.17 0.12 d l 1 z e z d y x c b 1 b p a h d a 2 e a 1 c 1 e e l h e 0.6 0.5 0.4 max nom min dimension in millimeters symbol reference 28 3.20 30.8 30.6 30.4 1.3 28 p-hqfp208-28x28-0.50 5.3g mass[typ.] fp-208e/fp-208ev prqp0208ke-b renesas code jeita package code previous code figure b.2 package dimensions (208-pin qfp)
SH7750, SH7750s, SH7750r group appendix b package dimensions r01uh0456ej0702 rev. 7.02 page 1025 of 1076 sep 24, 2013 e a 1 max nom min dimension in millimeters symbol reference a b x y 15.00 0.10 0.80 0.45 0.50 0.55 0.35 0.40 0.45 1.40 15.00 0.08 v w 1.10 1.10 y 1 0.2 0.20 0.15 previous code jeita package code renesas code bp-264/bp-264v 0.6g mass[typ.] z e z d s e s d e d p-lfbga264-15x15-0.80 plbg0264ga-a 1 1 a a b s s y s wa s wb v s y 1 234567891011121314151617 b c d e f g h j k l m n p r t u a a e e b a s b m 4 e d z z d e figure b.3 package dimensions (264-pin csp)
appendix b package dimensions SH7750, SH7750s, SH7750r group page 1026 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 e a 1 max nom min dimension in millimeters symbol reference a b x y 17.00 0.10 0.80 0.45 0.50 0.40 0.40 0.55 0.35 0.40 0.45 2.00 17.00 0.08 v w 0.9 0.9 y 1 0.20 0.20 0.15 previous code jeita package code renesas code ? 0.9g mass[typ.] z e z d z d z e s d s e s e s d e d p-fbga292-17x17-0.80 prbg0292ga-a 1 1 a b a s s y s wb s wa v s y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 b c d e f g h j k l m n p r t u v w y a a e e b a s b m 4 e d figure b.4 package dimensions (292-pin bga)
SH7750, SH7750s, SH7750r group appendix b package dimensions r01uh0456ej0702 rev. 7.02 page 1027 of 1076 sep 24, 2013 b a s z e e z d y w v u t r p n m l k j h g f e d c b a 20 19 18 17 16 15 1 4 13 12 11 10 9 8 7 6 5 4 3 2 1 sab a 1 a m v y s 4 e 1 e d 1 d e 0 . 20 0 . 30 0 . 35 y 1 1 .4 35 1 .4 35 w v 0 . 15 27 . 0 2 . 6 0 . 70 0 . 60 0 . 50 0 . 85 0 . 75 0 . 65 1 . 27 0 . 20 27 . 0 2 4. 0 2 4. 0 y x b a reference symbo l d i mens i on i n m illi meters m i n n om max a 1 e e 1 d 1 z e z d e d mass [t yp .] 2 . 8g ? r ene sas code j eit a package code prev i ous code p - bga256 - 27x27 - 1 . 27 prbg0256dm - a y 1 s s wa s wb b figure b.5 package dimensions (256-pin bga: hd6417750rba240hv and hd6417750sba200v)
appendix b package dimensions SH7750, SH7750s, SH7750r group page 1028 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group appendix c mode pin settings r01uh0456ej0702 rev. 7.02 page 1029 of 1076 sep 24, 2013 appendix c mode pin settings the md8?md0 pin values are input in th e event of a power-on reset via the reset or sck2/ mreset pin. (1) clock modes ? clock operating modes (SH7750, SH7750s) external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 1/2 frequency divider pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 0 off on on 6 3/2 3/2 h'0e1a 1 0 1 off on on 6 1 1 h'0e23 2 0 on on on 3 1 1/2 h'0e13 3 0 1 1 off on on 6 2 1 h'0e13 4 1 0 0 on on on 3 3/2 3/4 h'0e0a 5 1 off on on 6 3 3/2 h'0e0a notes: 1. turning on/off of the ? frequency divi der is solely determined by the clock operating mode. 2. for the ranges of input clock frequency, see the descriptions of the extal clock input frequency (f ex ) and ckio clock output (f op ) in section 22.3.1, clock and control signal timing.
appendix c mode pin settings SH7750, SH7750s, SH7750r group page 1030 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? clock operating modes (SH7750r) external pin combination frequency (vs. input clock) clock operating mode md2 md1 md0 pll1 pll2 cpu clock bus clock peripheral module clock frqcr initial value 0 0 on ( 12) on 12 3 3 h'0e1a 1 0 1 on ( 12) on 12 3/2 3/2 h'0e2c 2 0 on ( 6) on 6 2 1 h'0e13 3 0 1 1 on ( 12) on 12 4 2 h'0e13 4 1 0 0 on ( 6) on 6 3 3/2 h'0e0a 5 1 on ( 12) on 12 6 3 h'0e0a 6 1 0 off ( 6) off 1 1/2 1/2 h'0808 notes: 1. the multiplication factor of pll 1 is solely determined by the clock operating mode. 2. for the ranges of input clock frequency, see the descriptions of the extal clock input frequency (f ex ) and ckio clock output (f op ) in section 22.3.1, clock and control signal timing. (2) area 0 bus width pin value md6 md4 md3 bus width memory type 0 0 0 64 bits mpx interface 1 8 bits reserved (setting prohibited) 1 0 16 bits reserved 1 32 bits mpx interface 1 0 0 64 bits sram interface 1 8 bits sram interface 1 0 16 bits sram interface 1 32 bits sram interface
SH7750, SH7750s, SH7750r group appendix c mode pin settings r01uh0456ej0702 rev. 7.02 page 1031 of 1076 sep 24, 2013 (3) endian pin value md5 endian 0 big endian 1 little endian (4) master/slave pin value md7 master/slave 0 slave 1 master (5) clock input pin value md8 clock input 0 external input clock 1 crystal resonator
appendix c mode pin settings SH7750, SH7750s, SH7750r group page 1032 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group appendix d ckio2enb pin configuration r01uh0456ej0702 rev. 7.02 page 1033 of 1076 sep 24, 2013 appendix d ckio2enb pin configuration rd_pullup_control rd_dt_ rd_hiz_control rdwr_pullup_control rdwr_dt_ rdwr_hiz_control bus clock ckio_hiz_control vssq ckio2enb ckio2 ckio rd/ wr2 rd/ wr rd2 rd / cass / fram e vddq vddq vddq vddq vddq SH7750 SH7750s SH7750r pll2 figure d.1 ckio2enb pin configuration
appendix d ckio2enb pin configuration SH7750, SH7750s, SH7750r group page 1034 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ckio2enb description 0 rd2 , rd/ wr2 , and ckio2 have the same pin states as rd , rd/ wr , and ckio, respectively 1 rd2 , rd/ wr2 , and ckio2 are in the high-impedance state note: ckio is fed back to pll2 to coordinate the external clock and internal clock phases. however, ckio2 is not fed back.
SH7750, SH7750s, SH7750r group appendix e pin functions r01uh0456ej0702 rev. 7.02 page 1035 of 1076 sep 24, 2013 appendix e pin functions e.1 pin states table e.1 pin states in reset, power- down state, and bus-released state reset (power-on) reset (manual) signal name i/o master slave master slave standby bus released hardware standby d0?d7 i/o z z z * 19 z * 19 z * 19 z * 19 z d8?d15 i/o z z z * 19 z * 19 z * 19 z * 19 z d16?d23 i/o z z z * 19 z * 19 z * 19 z * 19 z d24?d31 i/o z z z * 19 z * 19 z * 19 z * 19 z d32?d51 i/o z z z * 19 k * 18 z * 19 k * 18 z * 19 k * 18 z * 19 k * 18 z d52?d55 i/o z z z * 19 z * 19 z * 19 z * 19 z d56?d63 i/o z z z * 19 z * 19 z * 19 z * 19 z a0, a1, a18?a25 o p p z * 13 o * 15 z * 13 z * 13 o * 6 z * 13 z a2?a17 o p p z * 13 o * 8 z * 13 z * 13 o * 6 z * 13 z reset i i i i i i i i back / bsreq o h h h h h o z breq / bsack i p p i * 12 i * 12 i * 12 i * 12 z bs o h pz h z * 13 z * 13 h * 6 z * 13 z cke o h h o o l o z cs6 ? cs0 o h pz h z * 13 z * 13 h * 6 z * 13 z ras o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z rd / cass / frame o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z rd/ wr o h pz h z * 13 z * 13 h * 6 z * 13 z rdy i pi pi i * 12 i * 12 z * 12 i * 12 z we7 / cas7 /dqm7 o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z we6 / cas6 /dqm6 o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z we5 / cas5 /dqm5 o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z we4 / cas4 /dqm4 o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z we3 / cas3 /dqm3 o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z we2 / cas2 /dqm2 o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z
appendix e pin functions SH7750, SH7750s, SH7750r group page 1036 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 reset (power-on) reset (manual) signal name i/o master slave master slave standby bus released hardware standby we1 / cas1 /dqm1 o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z we0 / cas0 /dqm0 o h pz o z * 13 z * 13 o * 4 z * 13 o * 4 z dack1?dack0 o l l l l z * 11 o * 7 o z md7/txd i/o pi * 14 pi * 14 z * 11 z * 11 z * 11 k * 18 o * 7 z * 11 k * 18 o * 7 z md6/ iois16 i pi * 14 pi * 14 i * 12 i * 12 z * 12 i * 12 z md5/ ras2 i/o * 1 pi * 14 pi * 14 z * 13 o * 5 z * 13 z * 13 o * 4 z * 13 o * 4 z md4/ ce2b i/o * 3 pi * 14 pi * 14 z * 13 h * 6 z * 13 z * 13 h * 6 z * 13 z md3/ ce2a i/o * 2 pi * 14 pi * 14 z * 13 h * 6 z * 13 z * 13 h * 6 z * 13 z ckio o o o o * 10 z * 10 o * 10 z * 10 pz o * 10 z * 10 z status1?status0 o o o o o o o zo * 16 irl3 ? irl0 i pi pi i * 12 i * 12 i * 12 i * 12 i nmi i pi pi i * 12 i * 12 i * 12 i * 12 i dreq1 ? dreq0 i pi pi i * 11 i * 11 z * 11 i * 11 i drak1?drak0 o l l l l z * 11 o * 7 o z md0/sck i/o pi * 14 pi * 14 i * 11 i * 11 z * 11 k * 18 o * 7 i * 11 ok * 18 z rxd i pi pi i * 11 i * 11 z * 11 i * 11 z sck2/ mreset i pi pi i * 11 i * 11 i * 11 i * 11 z md1/txd2 i/o pi * 14 pi * 14 z * 11 z * 11 z * 11 k * 18 o * 7 z * 11 k * 18 o * 7 z md2/rxd2 i pi * 14 pi * 14 i * 11 i * 11 z * 11 i * 11 z cts2 i/o pi pi i * 11 i * 11 z * 11 k * 18 i * 11 k * 18 z md8/ rts2 i/o pi * 14 pi * 14 i * 11 i * 11 z * 11 k * 18 i * 11 k * 18 z tclk i/o pi pi i * 11 i * 11 k * 11 o * 17 i * 11 o * 17 z tdo o o o o o o o z tms i pi pi pi pi pz pi z tck i pi pi pi pi pz pi z tdi i pi pi pi pi pz pi z trst i pi pi pi pi pz pi z ckio2 * 21 o pz * 20 o * 9 pz * 20 o * 9 pz * 20 o * 9 * 20 pz * 20 o * 9 * 20 pz pz * 20 o * 9 * 20 z
SH7750, SH7750s, SH7750r group appendix e pin functions r01uh0456ej0702 rev. 7.02 page 1037 of 1076 sep 24, 2013 reset (power-on) reset (manual) signal name i/o master slave master slave standby bus released hardware standby rd2 * 21 o z * 20 h * 9 * 20 z * 20 pz * 9 z * 13 * 20 o * 9 z * 9 * 13 z * 9 * 13 o * 4 z * 9 * 13 o * 4 z rd/ wr2 * 21 o z * 20 h * 9 * 20 z * 20 pz * 9 z * 13 * 20 h * 9 z * 9 * 13 z * 9 * 13 h * 4 z * 9 * 13 z ckio2enb i pi pi pi pi pi pi z ca i i i i i i i i asebrk /brkack i/o pi * 22 o * 22 pi * 22 o * 22 pi * 22 o * 22 pi * 22 o * 22 pi * 22 o * 22 pi * 22 o * 22 z legend: i: input (not pulled up) o: output z: high-impedance (not pulled up) h: high-level output l: low-level output k: output state held pi: input (pulled up) pz: high-impedance (pulled up) notes: 1. output when area 2 is used as dram. 2. output when area 5 is used as pcmcia. 3. output when area 6 is used as pcmcia. 4. z (i) or o on refresh operations, depen ding on register setting (bcr1.hizcnt). 5. depends on refresh operations. 6. z (i) or h (state held), dependi ng on register setting (bcr1.hizmem). 7. z or o, depending on register setting (stbcr.phz). 8. output when refreshing is set. 9. operation in respective state when ckio2enb = 0 (SH7750/SH7750s) (high-level outputs as SH7750r). 10. pz or o, depending on register setting (frqcr.ckoen). 11. pulled up or not pulled up, depen ding on register setting (stbcr.ppu). 12. pulled up or not pulled up, depending on register setting (bcr1.ipup). 13. pulled up or not pulled up, depending on register setting (bcr1.opup). 14. pulled up with a built-in pull-up resistance. however it, cannot use for fixation of an input md pin at the time of power-on reset. pull up or down outside this lsi. 15. output when refreshing is set (SH7750r only). 16. z or o, depending on register se tting (stbcr2.sthz) (SH7750r only). 17. z or o, depending on register setting (tocr, tcoe) 18. output state held when used as port.
appendix e pin functions SH7750, SH7750s, SH7750r group page 1038 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 19. pulled up or not pulled up, depending on register setting (bcr1.dpup) (SH7750r only). 20. z when ckio2enb = 1 21. bga package only. 22. depends on emulator operations. e.2 handling of unused pins ? when rtc is not used ? extal2: pull up to 3.3 v ? xtal2: leave unconnected ? vdd-rtc: power supply (3.3 v) ? vss-rtc: power supply (0 v) ? when pll1 is not used ? vdd-pll1: power supply (3.3 v) ? vss-pll1: power supply (0 v) ? when pll2 is not used ? vdd-pll2: power supply (3.3 v) ? vss-pll2: power supply (0 v) ? when on-chip crystal oscillator is not used ? xtal: leave unconnected ? vdd-cpg: power supply (3.3 v) ? vss-cpg: power supply (0 v) note: to prevent unwanted effects on other pins when using external pull-up or pull-down resistors, use independent pull-up or pull-down resistors for individual pins.
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1039 of 1076 sep 24, 2013 appendix f synchronous dram address multiplexing tables (1) bus 64 (16m: 512k 16b 2) 4 * amx 0 amxext 0 16m, column-addr-8bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a22 a22 a11 bank selects bank address a13 a21 h/l a10 address precharge setting a12 a20 0 a9 a11 a19 0 a8 a10 a18 a10 a7 a9 a17 a9 a6 a8 a16 a8 a5 a7 a15 a7 a4 a6 a14 a6 a3 a5 a13 a5 a2 a4 a12 a4 a1 a3 a11 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1040 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (2) bus 32 (16m: 512k 16b 2) 2 * amx 0 amxext 0 16m, column-addr-8bit 4mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a13 a21 a21 a11 bank selects bank address a12 a20 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1041 of 1076 sep 24, 2013 (3) bus 64 (16m: 512k 16b 2) 4 * amx 0 amxext 1 16m, column-addr-8bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a21 a21 a11 bank selects bank address a13 a22 h/l a10 address precharge setting a12 a20 0 a9 a11 a19 0 a8 a10 a18 a10 a7 a9 a17 a9 a6 a8 a16 a8 a5 a7 a15 a7 a4 a6 a14 a6 a3 a5 a13 a5 a2 a4 a12 a4 a1 a3 a11 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1042 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (4) bus 32 (16m: 512k 16b 2) 2 * amx 0 amxext 1 16m, column-addr-8bit 4mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a13 a20 a20 a11 bank selects bank address a12 a21 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1043 of 1076 sep 24, 2013 (5) bus 64 (16m: 1m 8b 2) 8 * amx 1 amxext 0 16m, column-addr-9bit 16mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a23 a23 a11 bank selects bank address a13 a22 h/l a10 address precharge setting a12 a21 0 a9 a11 a20 a11 a8 a10 a19 a10 a7 a9 a18 a9 a6 a8 a17 a8 a5 a7 a16 a7 a4 a6 a15 a6 a3 a5 a14 a5 a2 a4 a13 a4 a1 a3 a12 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1044 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (6) bus 32 (16m: 1m 8b 2) 4 * amx 1 amxext 0 16m, column-addr-9bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a13 a22 a22 a11 bank selects bank address a12 a21 h/l a10 address precharge setting a11 a20 0 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1045 of 1076 sep 24, 2013 (7) bus 64 (16m: 1m 8b 2) 8 * amx 1 amxext 1 16m, column-addr-9bit 16mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a22 a22 a11 bank selects bank address a13 a23 h/l a10 address precharge setting a12 a21 0 a9 a11 a20 a11 a8 a10 a19 a10 a7 a9 a18 a9 a6 a8 a17 a8 a5 a7 a16 a7 a4 a6 a15 a6 a3 a5 a14 a5 a2 a4 a13 a4 a1 a3 a12 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1046 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (8) bus 32 (16m: 1m 8b 2) 4 * amx 1 amxext 1 16m, column-addr-9bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a14 a13 a21 a21 a11 bank selects bank address a12 a22 h/l a10 address precharge setting a11 a20 0 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1047 of 1076 sep 24, 2013 (9) bus 64 (64m: 1m 16b 4) 4 * amx 2 64m, column-addr-8bit 32mb lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a24 a24 a13 a15 a23 a23 a12 bank selects bank address a14 a22 0 a11 a13 a21 h/l a10 address precharge setting a12 a20 0 a9 a11 a19 0 a8 a10 a18 a10 a7 a9 a17 a9 a6 a8 a16 a8 a5 a7 a15 a7 a4 a6 a14 a6 a3 a5 a13 a5 a2 a4 a12 a4 a1 a3 a11 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1048 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (10) bus 32 (64m: 1m 16b 4) 2 * amx 2 64m, column-addr-8bit 16mb lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a15 a23 a23 a13 a14 a22 a22 a12 bank selects bank address a13 a21 0 a11 a12 a20 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1049 of 1076 sep 24, 2013 (11) bus 64 (64m: 2m 8b 4) 8 * (128m: 2m 16b 4) 4 * amx 3 64m, column-addr-9bit 64mb lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a25 a25 a13 a15 a24 a24 a12 bank selects bank address a14 a23 0 a11 a13 a22 h/l a10 address precharge setting a12 a21 0 a9 a11 a20 a11 a8 a10 a19 a10 a7 a9 a18 a9 a6 a8 a17 a8 a5 a7 a16 a7 a4 a6 a15 a6 a3 a5 a14 a5 a2 a4 a13 a4 a1 a3 a12 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1050 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (12) bus 32 (64m: 2m 8b 4) 4 * (128m: 2m 16b 4) 2 amx 3 64m, column-addr-9bit 32mb lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a15 a24 a24 a13 a14 a23 a23 a12 bank selects bank address a13 a22 0 a11 a12 a21 h/l a10 address precharge setting a11 a20 0 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1051 of 1076 sep 24, 2013 (13) bus 64 (64m: 512k 32b 4) 2 * amx 4 64m, column-addr-8bit 16mb lsi address pins ras cycle cas cycle synchronous dram address pins function a15 a23 a23 a12 a14 a22 a22 a11 bank selects bank address a13 a21 h/l a10 address precharge setting a12 a20 0 a9 a11 a19 0 a8 a10 a18 a10 a7 a9 a17 a9 a6 a8 a16 a8 a5 a7 a15 a7 a4 a6 a14 a6 a3 a5 a13 a5 a2 a4 a12 a4 a1 a3 a11 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1052 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (14) bus 32 (64m: 512k 32b 4) 1 * amx 4 64m, column-addr-8bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a15 a14 a22 a22 a12 a13 a21 a21 a11 bank selects bank address a12 a20 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1053 of 1076 sep 24, 2013 (15) bus 64 (64m: 1m 32b 2) 2 * amx 5 64m, column-addr-8bit 16mb lsi address pins ras cycle cas cycle synchronous dram address pins function a15 a23 a23 a12 a14 a22 0 a11 bank selects bank address a13 a21 h/l a10 address precharge setting a12 a20 0 a9 a11 a19 0 a8 a10 a18 a10 a7 a9 a17 a9 a6 a8 a16 a8 a5 a7 a15 a7 a4 a6 a14 a6 a3 a5 a13 a5 a2 a4 a12 a4 a1 a3 a11 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1054 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (16) bus 32 (64m: 1m 32b 2) 1 * amx 5 64m, column-addr-8bit 8mb lsi address pins ras cycle cas cycle synchronous dram address pins function a15 a14 a22 a22 a12 a13 a21 0 a11 bank selects bank address a12 a20 h/l a10 address precharge setting a11 a19 0 a9 a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1055 of 1076 sep 24, 2013 (17) bus 64 (128m: 4m 8b 4) 8 * (SH7750r only) amx 6 128m, column-addr-10bit 128mb amxext0 lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a26 a26 a13 a15 a25 a25 a12 bank selects bank address a14 a24 0 a11 a13 a23 h/l a10 address precharge setting a12 a22 a12 a9 a11 a21 a11 a8 a10 a20 a10 a7 a9 a19 a9 a6 a8 a18 a8 a5 a7 a17 a7 a4 a6 a16 a6 a3 a5 a15 a5 a2 a4 a14 a4 a1 a3 a13 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1056 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (18) bus 64 (256m: 4m 16b 4) 4 (SH7750r only) * amx 6 256m, column-addr-9bit 128mb amxext1 lsi address pins ras cycle cas cycle synchronous dram address pins function a17 a26 a26 a14 a16 a25 a25 a13 bank selects bank address a15 a24 0 a12 a14 a23 0 a11 a13 a22 h/l a10 address precharge setting a12 a21 0 a9 a11 a20 a11 a8 a10 a19 a10 a7 a9 a18 a9 a6 a8 a17 a8 a5 a7 a16 a7 a4 a6 a15 a6 a3 a5 a14 a5 a2 a4 a13 a4 a1 a3 a12 a3 a0 address a2 not used a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1057 of 1076 sep 24, 2013 (19) bus 32 (128m: 4m 8b 4) 4 (SH7750s and SH7750r only) * amx 6 column-addr-10bit 64mb amxext 0 lsi address pins ras cycle cas cycle synchronous dram address pins function a15 a25 a25 a13 a14 a24 a24 a12 bank selects bank address a13 a23 0 a11 address precharge setting a12 a22 h/l a10 a11 a21 a11 a9 a10 a20 a10 a8 a9 a19 a9 a7 a8 a18 a8 a6 a7 a17 a7 a5 a6 a16 a6 a4 a5 a15 a5 a3 a4 a14 a4 a2 a3 a13 a3 a1 a2 a12 a2 a0 address a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1058 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (20) bus 32 (256m: 4m 16b 4) 2 (SH7750s and SH7750r only) * amx 6 256m, column-addr-9bit 64mb amxext 1 lsi address pins ras cycle cas cycle synchronous dram address pins function a16 a25 a25 a14 a15 a24 a24 a13 bank selects bank address a14 a23 0 a12 a13 a22 0 a11 a12 a21 h/l a10 address precharge setting a11 a20 0 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 not used a0 not used
SH7750, SH7750s, SH7750r group appendix f sync hronous dram address multiplexing tables r01uh0456ej0702 rev. 7.02 page 1059 of 1076 sep 24, 2013 (21) bus 64 (16m: 256k 32b 2) 2 * amx 7 16m, column-addr-8bit 4mb lsi address pins ras cycle cas cycle synchronous dram address pins function a13 a21 a21 a10 bank selects bank address a12 a20 h/l a9 address precharge setting a11 a19 0 a8 a10 a18 a10 a7 a9 a17 a9 a6 a8 a16 a8 a5 a7 a15 a7 a4 a6 a14 a6 a3 a5 a13 a5 a2 a4 a12 a4 a1 a3 a11 a3 a0 address a2 not used a1 not used a0 not used
appendix f synchronous dram address mult iplexing tables SH7750, SH7750s, SH7750r group page 1060 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 (22) bus 32 (16m: 256k 32b 2) 1 * amx 7 16m, column-addr-8bit 2mb lsi address pins ras cycle cas cycle synchronous dram address pins function a13 a12 a20 a20 a10 bank selects bank address a11 a19 h/l a9 address precharge setting a10 a18 0 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 not used a0 not used note: * example of a synchronous dram configuration
SH7750, SH7750s, SH7750r group appendix g prefetch ing of instructions and its side effects r01uh0456ej0702 rev. 7.02 page 1061 of 1076 sep 24, 2013 appendix g prefetching of instructions and its side effects this lsi incorporates an on-chip bu ffer for holding instructions that have been read ahead of their execution (prefetching of instructio ns). therefore, do not allocate programs to memory in such a way that instructions are in the last 20 bytes of any memory space. if a program is allocated in such a way, the prefetching of instructions ma y lead to a bus access for reading an instruction from beyond the memory space. the followi ng shows a case in which such bus access is a problem. pc (pro g ram counter) address of instruction for prefetchin g area 0 area 1 address h'03fffff8 h'03fffffa h'03fffffc h'03fffffe h'04000000 h'04000002 add r1,r4 jmp @r2 nop nop . . . . . . figure g.1 instruction prefetch figure g.1 depicts a case in whic h the instruction (add) indicated by the program counter and the instruction at the address h'04000002 are fetched simultaneously. the program is assumed to branch to a region other than area 1 after the subsequent jmp instruction and delay slot instruction have been executed. in this case, a bus access to area 1 (instruction pref etch), which is not visi ble in the program flow, may occur. 1. side effects of the prefetching of instructions a. an external bus access caused by an inst ruction prefetch may cause malfunctions in external devices, such as fifos, that are connected to the region accessed. b. if no device responds to an external bus request that is triggered by an instruction prefetch, execution may hang. 2. methods of preventing the inva lid prefetching of instructions a. use an mmu. b. do not allocate programs so that they run in to the last 20-byte region of any memory space.
appendix g prefetching of instructions a nd its side effects SH7750, SH7750s, SH7750r group page 1062 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group appendix h power-on and power-off procedures r01uh0456ej0702 rev. 7.02 page 1063 of 1076 sep 24, 2013 appendix h power-on and power-off procedures h.1 power-on stipulations 1. supply power to power supply v ddq and to i/o, rtc, cpg, pll1, and pll2 simultaneously. 2. perform input to the signal lines ( reset , mreset , md0 to md10, external clock, etc.) after or at the same time power is supplied to v ddq . applying input to signal lines before power is supplied to v ddq could damage the product. ? drive the reset signal low when power is first supplied to v ddq . ? input a high-level mreset signal in the same sequence as power supply v ddq when power is first supplied to v ddq . 3. it is recommended to apply power first to power supply v ddq and then to power supply v dd . 4. in addition to 1., 2., and 3. above, also observe the stipulations in h.3. furthermore: ? there are no time restrictions on the power-on sequence for power supply v ddq and power supply v dd with regard to the lsi alone. refer to figure h.1. nevertheless, it is recommended that the power-on sequence be completed in as short a time as possible. ? when the lsi is mounted on a board and connect ed to other elements, ensure that ?0.3 v < vin < v ddq + 0.3 v. in addition, the time limit for the rise of power supply v ddq and power supply v dd from gnd (0 v) to above the mini mum values in the lsi?s guaranteed operation voltage range (v ddq (min.) and v dd (min.)) is 100 ms (max .), as shown in figure h.2. the product may be damaged if this time limit is exceeded. it is recommended that the power-on sequence be completed in as short a time as possible. h.2 power-off stipulations 1. power off power supply v ddq and i/o, rtc, cpg, pll1, and pll2 simultaneously. 2. there are no timing restrictions for the reset and mreset signal lines at power-off. 3. cut off the input signal level for signal lines other than reset and mreset in the same sequence as power supply v ddq . 4. it is recommended to first power off power supply v dd and then power supply v ddq . 5. in addition to 1., 2., 3., and 4. above, also observe the stipulations in h.3. furthermore: ? there are no time restrictions on the power-off sequence for power supply v ddq and power supply v dd with regard to the lsi alone. refer to figure h.1. nevertheless, it is recommended that the power-off sequence be completed in as short a time as possible.
appendix h power-on and power-off procedures SH7750, SH7750s, SH7750r group page 1064 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 ? when the lsi is mounted on a board and connect ed to other elements, ensure that ?0.3 v < vin < v ddq + 0.3 v. in addition, the time limit for the fall of power supply v ddq and power supply v dd from the minimum values in the lsi?s guaranteed operation voltage range (v ddq (min.) and v dd (min.)) to gnd (0 v) is 150 ms (max.), as shown in figure h.2. the product may be damaged if this time limit is exceed ed. it is recommende d that the power-off sequence be completed in as short a time as possible. h.3 common stipulations for power-on and power-off 1. always ensure that v ddq = v dd ? cpg = v dd ? rtc = v dd ? pll1/2 . refer to 9.8.5, hardware standby mode timing (SH7750s, SH7750r only), regarding v dd ? rtc in hardware standby mode on the SH7750s and SH7750r. 2. ensure that ? 0.3 v < v dd < v ddq + 0.3 v. 3. ensure that v ss = v ssq = v ss ? pll1/2 = v ss ? cpg = v ss ? rtc = gnd (0 v). the product may be damaged if conditions 1., 2., and 3. above are not satisfied. gnd [v] [t] 0.3 v (max) 0.3 v (max) power-on power-off power supply v ddq power supply v dd figure h.1 power-on procedure 1
SH7750, SH7750s, SH7750r group appendix h power-on and power-off procedures r01uh0456ej0702 rev. 7.02 page 1065 of 1076 sep 24, 2013 gnd [v] t pwu t pwu <100 ms (max) v ddq (min) v dd (min) unstable period at power-on:t pwu t pwd t pwd <150 ms (max) unstable period at power-off: t pwd [t] power-on power-off power supply v ddq power supply v dd normal operation period figure h.2 power-on procedure 2
appendix h power-on and power-off procedures SH7750, SH7750s, SH7750r group page 1066 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group appendix i product lineup r01uh0456ej0702 rev. 7.02 page 1067 of 1076 sep 24, 2013 appendix i product lineup table i.1 SH7750/SH7750s/SH7750r product lineup product name voltage operating frequency operating temperature * 1 part number * 2 package SH7750 1.95 v 200 mhz ?20 to 75c hd6417750bp200m (v) 256-pin bga 1.8 v 167 mhz ?20 to 75c hd6417750f167 (v) 208-pin qfp 1.5 v 128 mhz ?20 to 75c hd6417750vf128 (v) SH7750s 1.95 v 200 mhz ?20 to 75c hd6417750sbp200 (v) 256-pin bga ?20 to 75c hd6417750sba200v ?20 to 75c hd6417750sf200 (v) 208-pin qfp 1.8 v 167 mhz ?20 to 75c hd6417750sf167 (v) 208-pin qfp 1.5 v 133 mhz ?20 to 75c hd6417750svf133 (v) ?30 to 70c hd6417750svbt133 (v) 264-pin csp SH7750r 1.5 v 240 mhz ?20 to 75c hd6417750rbp240 (v) 256-pin bga ?20 to 75c hd6417750rba240hv ?20 to 75c hd6417750rf240 (v) 208-pin qfp ?20 to 75c hd6417750rbg240 (v) 292-pin bga 1.5 v 200 mhz ?20 to 75c hd6417750rbp200 (v) 256-pin bga ?20 to 75c hd6417750rf200 (v) 208-pin qfp ?20 to 75c hd6417750rbg200 (v) 292-pin bga notes: 1. contact a renesas sales office regar ding product versions with specifications for a wider temperature range (?40 to +85c). the wide temperature range (?40 to +85c) is the standard specification for the hd6417751rba240hv. 2. all listed products are available in le ad-free versions. lead-free products have a ?v? appended at the end of the part number . for example, hd6417750bp200mv, hd6417750f167v, etc.
appendix i product lineup SH7750, SH7750s, SH7750r group page 1068 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
SH7750, SH7750s, SH7750r group appendi x j version registers r01uh0456ej0702 rev. 7.02 page 1069 of 1076 sep 24, 2013 appendix j version registers the configuration of the registers related to the product version is shown below. table j.1 register configuration name abbreviation read/write initial value p4 address area 7 address access size processor version register pvr r * h'ff000030 h'1f000030 32 product register prr r * h'ff000044 h'1f000044 32 note: * refer to table below. pvr and prr initial values product name pvr prr SH7750 h'0402 05xx h'xxxx xxxx SH7750s h'0402 06xx h'xxxx xxxx SH7750r h'0405 00xx h'0000 010x legend: x: undefined 1. processor version register (pvr ) initial value example for SH7750r bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 version information initial value: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 version information ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? r/w: r r r r r r r r ? ? ? ? ? ? ? ?
appendix j version register s SH7750, SH7750s, SH7750r group page 1070 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 2. product register (prr) initial value example for SH7750r bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 version information initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 version information ? ? ? ? initial value: 0 0 0 0 0 0 0 1 0 0 0 0 ? ? ? ? r/w: r r r r r r r r r r r r ? ? ? ?
SH7750, SH7750s, SH7750r group index r01uh0456ej0702 rev. 7.02 page 1071 of 1076 sep 24, 2013 index a address space........................................... 79 b bus arbitration ....................................... 536 bus state controller................................ 357 address multip lexing ......................... 451 areas........................................... 365, 433 burst access ....................................... 454 burst rom interface .......................... 497 byte control sram interface ............ 529 dram interface ................................. 447 edo mode.......................................... 455 endian................................................. 421 i/o card interface ........................ 368, 500 ic memory card interface ........... 368, 500 master mode....................................... 539 mpx interface .................................... 511 partial-sharing master mode.............. 541 pcmcia interface.............................. 500 pcmcia support ............................... 368 ras down mode ............................... 456 refresh timing ................................... 461 refreshing........................................... 484 slave mode ......................................... 540 sram interface.................................. 438 synchronous dram interface ........... 465 wait state c ontrol .............................. 453 waits between access cycles............. 534 c caches..................................................... 111 address array............. 131, 133, 137, 139 cache fill ............................................. 125 data array .................. 132, 135, 138, 141 ic index mode .................................... 131 instruction cache ................ 111, 112, 128 oc index mode................................... 124 operand cache.................... 111, 112, 116 prefetch ............................................... 143 prefetch operation .............................. 125 ram mode ......................................... 123 store queues ....................................... 142 tag .............................................. 119, 129 u bit .................................................... 119 v bit ............................................ 119, 129 write-back buffer .............................. 122 write-through buffer ......................... 122 clock oscillation circuits....................... 287 bus clock divisi on ratio ................... 299 changing the frequency ..................... 298 clock operating modes ...................... 293 pll circuit ......................................... 298 clock pulse generator .............................. 287 control registers ................................ 54, 62 dbr ...................................................... 63 debug base register............................... 63 gbr ...................................................... 63 global base register............................... 63 saved general register 15 ...................... 63 saved program counter ......................... 63 saved status register.............................. 63 sgr....................................................... 63 spc ....................................................... 63 sr ......................................................... 62 ssr ....................................................... 63 status register........................................ 62 vbr ...................................................... 63 vector base register............................... 63
index SH7750, SH7750s, SH7750r group page 1072 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 d data format .............................................. 66 direct memory access controller.......... 545 address modes ................................... 577 burst mode ......................................... 581 bus modes .......................................... 580 channel prio rities ............................... 573 cycle steal mode ............................... 580 dma transfer .................................... 576 dma transfer requests ..................... 569 dual address mode ............................ 578 ending dma transfer........................ 599 fixed mode......................................... 573 on-demand data transfer mode ....... 603 round robin mode ............................ 573 single address mode.......................... 577 e effective address ..................................... 211 exceptions .............................................. 149 address error.............................. 169, 170 exception types ................................. 152 fpu exception ............................ 177, 193 general exceptions............................. 164 general fpu disable exception......... 174 general illegal instruction .................. 193 general illegal instruction exception............................................ 172 initial page write exception............... 166 instruction tlb protection violation exception............................ 168 slot fpu disabl e exception ............... 175 slot illegal instruction exception......... 193 slot illegal instru ction exception ....... 173 tlb miss exception................... 164, 165 tlb multiple-hit exception ...... 162, 163 tlb protection violation exception .. 167 unconditional trap............................. 171 user breakpoint trap ......................... 176 external memory space map ................. 366 f floating-point regist ers.............. 55, 59, 189 floating-point unit ................................. 185 denormalized numbers ...................... 188 floating-point format......................... 185 geometric operation instructions....... 195 nan............................................. 187, 188 non-numbers...................................... 187 pair single-precision data transfer.... 196 g general registers................................ 54, 57 graphics support functions.................... 195 h hitachi user debug interface ................. 879 tap control........................................ 891 i i/o ports.................................................. 803 instruction set ................................. 209, 215 arithmetic operation instructions ...... 218 branch instructions ..................... 222, 252 data transfer instructions .................... 249 double-precision floating-point instructions.......................................... 255 fixed-point arithmetic instructions ..... 250 fixed-point transfer instructions ....... 216 floating-point contro l instructions .... 226 floating-point double-precision instructions ......................................... 226 floating-point graphics acceleration instructions ......................................... 227
SH7750, SH7750s, SH7750r group index r01uh0456ej0702 rev. 7.02 page 1073 of 1076 sep 24, 2013 floating-point single-precision instructions ......................................... 225 fpu system control instructions ......... 256 graphics acceleration instructions ...... 256 logic operation in structions .............. 220 shift instructions......................... 221, 252 single-precision floating-point instructions.......................................... 254 system control instructions......... 223, 253 interrupt controller................................. 825 interrupt priority ................................. 833 on-chip peripheral module interrupts............................................. 831 interrupts................................................. 178 ati ..................................................... 333 bri ..................................................... 770 eri...................................... 718, 770, 796 irl interrupts ............................. 179, 829 nmi .................................................... 178 nmi interrupt ..................................... 828 peripheral module interrupts .............. 180 pri...................................................... 333 rxi ..................................... 718, 770, 796 tei...................................................... 718 ticpi .................................................. 355 tuni................................................... 355 txi ..................................... 718, 770, 796 m memory management unit............... 71, 501 address array............................. 103, 106 address space identifier....................... 85 address translation .............................. 85 address translation method................. 90 asid..................................................... 85 avoiding synonym problems............... 95 data array .................................. 104, 107 external memory space................... 79, 82 itlb ..................................................... 90 ldtlb.................................................. 93 mmu exceptions.................................. 96 mmu functions.................................... 93 physical address space .................... 72, 79 time sharing system............................... 71 tlb................................................. 71, 86 utlb .................................................... 86 virtual address space ...................... 72, 83 virtual memory system.......................... 71 p pipelining ................................................ 231 execution cycles ........................ 242, 249 parallel-execu tability.......................... 238 pipeline st alling .................................. 242 power-down modes ............................... 259 clock pause function ......................... 271 deep sleep mode................................ 269 exit from standby mode..................... 271 hardware stan dby mode .................... 274 high impedance control..................... 264 module standby function................... 272 pull-up control................................... 265 sleep mode ......................................... 268 programming model ................................. 53 banks .................................................... 54 data formats......................................... 53 privileged mode.................................... 54 r realtime cl ock........................................ 311 alarm function ................................... 332 crystal oscillator circuit .................... 333 cui ..................................................... 333 time setting........................................ 329 registers bamra.............................................. 856 bamrb .............................................. 859
index SH7750, SH7750s, SH7750r group page 1074 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013 bara................................................. 855 barb ................................................. 859 basra............................................... 856 basrb............................................... 859 bbra ................................................. 857 bbrb ................................................. 861 bcr1 .................................................. 372 bcr2 .................................................. 381 bdrb ................................................. 859 brcr ................................................. 861 ccr .................................................... 114 chcr ................................................. 555 dar.................................................... 553 dmaor ............................................. 564 dmatcr ........................................... 554 fpscr ................................................ 191 fpul .................................................. 192 frqcr............................................... 295 gpioic............................................... 818 icr ..................................................... 837 ipr...................................................... 835 mcr ................................................... 401 pcr .................................................... 409 pctra ............................................... 814 pctrb ............................................... 816 pdtra ............................................... 815 pdtrb ............................................... 817 qacr0 ............................................... 114 r64cnt ............................................. 315 rcr1 .................................................. 323 rcr2 .................................................. 325 rdayar ........................................... 322 rdaycnt......................................... 318 rfcr.................................................. 420 rhrar .............................................. 321 rhrcnt............................................ 317 rminar ............................................ 320 rmincnt.......................................... 316 rmonar........................................... 323 rmoncnt ........................................ 318 rsecar............................................. 320 rseccnt .......................................... 316 rtcnt ............................................... 418 rtcor ............................................... 419 rtcsr................................................ 415 rwkar ............................................. 321 rwkcnt ........................................... 317 ryrcnt ............................................ 319 sar..................................................... 552 scbrr1 ............................................. 676 scbrr2 ............................................. 744 scfcr2.............................................. 745 scfdr2.............................................. 749 scfrdr2 ........................................... 730 scfsr2 .............................................. 737 scftdr2 ........................................... 731 sclsr2 .............................................. 756 scrdr1 ............................................. 660 scrsr1.............................................. 659 scrsr2.............................................. 729 scscmr1 .......................................... 778 scscr1...................................... 664, 780 scscr2.............................................. 734 scsmr1 ..................................... 661, 779 scsmr2 ............................................. 731 scsptr1.................................... 671, 819 scsptr2.................................... 750, 821 scssr1 ...................................... 667, 781 sctdr1 ............................................. 661 sctsr1 .............................................. 660 sctsr2 .............................................. 730 sdbpr................................................ 886 sddr.................................................. 885 sdir ................................................... 883 sdmr ................................................. 413 stbcr................................................ 262 stbcr2.............................................. 265 tcnt.................................................. 344 tcor.................................................. 344 tcpr2 ................................................ 350
SH7750, SH7750s, SH7750r group index r01uh0456ej0702 rev. 7.02 page 1075 of 1076 sep 24, 2013 tcr .................................................... 345 tocr ................................................. 341 tstr .................................................. 342 wcr1 ................................................. 388 wcr2 ................................................. 391 wcr3 ................................................. 399 wtcnt .............................................. 301 wtcsr .............................................. 302 resets...................................................... 159 h-udi reset ............................... 161, 892 manual reset ...................................... 160 power-on reset.................................. 159 rounding ................................................ 193 s serial communica tion interface ............. 655 asynchronous mode ................... 684, 686 bit rate ............................................... 676 break................................................... 719 framing error.............................. 696, 719 multiprocessor communication function.............................................. 698 overrun error .............................. 696, 719 parity error.................................. 696, 719 synchronous mode...................... 684, 707 serial communication interface with fifo ............................................... 725 asynchronous mode........................... 757 break................................................... 771 smart card in terface............................... 775 bit rate................................................. 787 system registers................................. 54, 63 floating-point status /control register .... 64 fpscr .................................................. 64 mach .................................................. 63 macl................................................... 63 multiply-and-accumulate register high .......................................... 63 multiply-and-accumulate register low ........................................... 63 pc ......................................................... 63 pr ......................................................... 63 procedure register ................................. 63 program counter.................................... 63 t timer unit............................................... 337 auto-reload count operation ............ 352 input capture function ....................... 353 tcnt count timing........................... 352 u user break controller ............................. 851 instruction access cycle break .......... 866 operand access cycle break.............. 867 user break debug support function .. 872 user break operation sequence ......... 865 w watchdog timer ............................. 287, 300 interval timer mode ........................... 307 watchdog timer mode ....................... 306
index SH7750, SH7750s, SH7750r group page 1076 of 1076 r01uh0456ej0702 rev. 7.02 sep 24, 2013
renesas 32-bit risc microcomputer SH7750, SH7750s, SH7750r group user's manual: hardware publication date: 1st edition, june, 1998 rev.7.02, september 24, 2013 published by: renesas electronics corporation
http://www.renesas.com 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 arcadiastrasse 10, 40472 d tel: +49-211-65030, fax: +49-211-6503-1327 sseldorf, germany dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics canada limited renesas electronics europe limited renesas electronics america inc. renesas electronics (china) co., ltd. renesas electronics (shanghai) co., ltd. renesas electronics europe gmbh renesas electronics taiwan co., ltd. renesas electronics singapore pte. ltd. renesas electronics hong kong limited renesas electronics korea co., ltd. renesas electronics malaysia sdn.bhd. sales offices ? 2013 renesas electronics corporation. all rights reserved. colophon 1.3

?? SH7750, SH7750s, SH7750r group user?s manual: hardware r01uh0456ej0702 (previous number: rej09b0366-0700)

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